Supercomputing Status und Trends (Conference Report) Peter Wegner
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1 (Conference Report) Peter Wegner SC2004 conference Top500 List BG/L Moors Law, problems of recent architectures Solutions Interconnects Software Lattice QCD machines QCDOC Conclusions
2 Technical Program SC2004 Exhibition Research : ~150 Industry : ~200
3 Supercomputing = (Processor Performance) + Network Speed + Storage Capacity SCinet Aggregate WAN transport delivered to the Industry and Research Exhibitors is expected to exceed 150 Gbps StorCloud 1 PetaByte of randomly accessible storage 1 GigaByte per second backup bandwidth
4 Top 500 List (Linpack Benchmark, Jack Dongarra, Erich Strohmaier, Hans W. Meuer ) Rank Computer/Processors/Manufactor R max R peak Installation Site Country/Year Inst. type Installation Area 1 BlueGene/L beta-system BlueGene/L DD2 beta-system (0.7 GHz PowerPC 440) / IBM United States/2004 Research 2 Columbia SGI Altix 1.5 GHz, Voltaire Infiniband / SGI NASA/Ames Research Center/NAS United States/2004 Research 3 Earth-Simulator / 5120 NEC The Earth Simulator Center Japan/2002 Research 4 MareNostrum eserver BladeCenter JS20 (PowerPC GHz), Myrinet / 3564 IBM Barcelona Supercomputer Center Spain/2004 Research 5 Thunder Intel Itanium2 Tiger4 1.4GHz - Quadrics / 4096 California Digital Corporation Lawrence Livermore National Laboratory United States/2004 Research
5
6 IBM CMOS CU µm technology.
7 HITACHI: SR11000 model H1, 16 POWER5 processors (1.9GHz) per node ( ) NEC: SX-7 Vector Computer ( Cray : X1 Vector Computer (
8 Moors Law Gordon Moore from INTEL predicted at the beginning of IC mass production in the 1970 that within every period of 18 month the complexity (number of transistors on one chip) will be doubled. No prediction about power consumption, about performance, about efficiency Problems: memory bandwidth, performance loss due to the increase in pipeline size, cooling Solutions: multi-core CPUs, multithreaded architectures (or both), software prefetch (HITACHI),
9 CPU efficiency at increasing clock speed PIII cpu efficiency (performance / MHz) P4 clock speed Marc Tremblay, SUN
10 Multi-core multithreaded Architectures Marc Tremblay, SUN
11 Reconfigurable co-processors Cray XD1: Compute System 12 AMD Opteron 32/64 bit, x86 processors per shelf Packaged as six 2-way SMP s Linux Very densely packaged RapidArray Interconnect System 12 communications processors 1 terabit per second switch fabric 30X Gigabit ethernet performance Active Management System Dedicated processor High availability Single system management and control Application Acceleration System 6 FPGA co-processors
12 Reconfigurable co-processors Cray XD1:
13 Reconfigurable co-processors Clearspeed: Linux Networks?
14 X86 architectures, bottlenecks
15 X86 architectures, dual chipset XEON Motherboards Akira Ukawa, University of Tsukuba German-Japanese Workshop 27 November, 2004 A Similar Architecture using Infiniband interconnect was presented on SC2004 by James Ballew from Raytheon
16 Interconnects Infiniband absolute winner, but in the a good chance future for low latency 10GBit Ethernet (10Gig will get to copper in a year or two ) PathScale HTX-Adaptor - Hypertransport connector reduced infiniband protocol, accepted by Infiniband switches, 1.5 µs MPI latency, FPGA ready, ASIC Q2/2005 Myrinet, QsNET, Dolphin Interconnect (SCALI)
17 Software PathScale EKOPATH Compiler Suite for AMD64 and EM64T PGI Compiler Intel Compiler Absoft TotalView (Etnus) Allinea DDT (Distributed Debugging Tool) PBS Pro SUN Gridengine (SUN, RAYTHEON) LSF
18 NIC FZJ, DESY NIC/FZJ JUMP Supercomputer (IBM Regatta, 8.9 TFlops, Rank 30 of Top500 list) Graphical User Interface for Job Monitoring NIC/DESY APE massive parallel computers (550 GFlops/3 TFlops)
19 Lattice QCD, NIC/DESY Zeuthen poster : APEmille
20 NIC/DESY FZJ
21 Lattice QCD QCDOC Columbia University RIKEN/Brookhaven National Laboratory (BNL) UKQCD, IBM
22 Columbia University RIKEN/Brookhaven National Laboratory (BNL) UKQCD, IBM MIMD machine with distributed memory system-on-a-chip design (QCDOC = QCD on a chip)technology: IBM SA27E = CMOS 7SF = 0.18 mm lithography process ASIC combines existing IBM components and QCD-specific, customdesigned logic: 500 MHz PowerPC 440 processor core with 64-bit, 1 GFlops FPU 4 MB on-chip memory (embedded DRAM) Nearest-neighbor serial communications unit (SCU) 6-dimensional communication network (4-D Physics, 2-D partitioning) Silicon chip of about 11 mm square, consuming 2 W
23 Conclusions A wide range of supercomputing architectures - high end supercomputers Hitachi SR1100, Cray X1, NEC SX7/8 -commodity clusters as HPC solution Linux Networks, IBM, DELL, SGI, SUN, HP, Rack Server - more than 20 systems with more than 1500 dual CPU nodes in Top500 list - Blade servers - SMP systems IBM (Power5), HP(Itanium), SUN(Sparc, Opteron), SGI (Itanium) - special designs with integrated commodity CPUs Cray XD1, Linux Networks? -special purpose systems BG/L, QCDOC, apenext, GRAPE6 (Japan) No significant systems performance increase using classical technologies, therefore Direct CPU-Memory connection (AMD) Multi-core CPUs (IBM, Intel, AMD) Multi-core multithreaded CPUs (SUN, MTA) Increasing fraction of Opteron HPC systems Infiniband as a special High Performance Link beats products like Myrinet and QsNet, in future Gbit10 Ethernet? All commercial compiler vendors are offering optimized compilers for 64-Bit x86 systems (Opteron, EM64T)
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