On Jitter by Dan Lavry, Lavry Engineering, Inc.

Transcription

1 On Jier by Dan Lavry, Lavry Engineering, Inc. Copyrigh 1997 Lavry Engineering The firs par of his aricle for people who wan o gain some inuiive undersanding abou clock jier problems, bu wish o avoid he somewha complicaed mahemaics associaed wih he subjec. The second par deals wih hardware relaed problems and pracical consideraions. Undersanding Jier A ime error in he sampling clock may cause a deviaion from desired sample value. Such errors occur when he sample / hold circui for an analog o digial converer is driven by an unseady clock. Similarly, he reconsrucion of an analog signal by a digial o analog circui requires a jier free clock. When sampling or reconsrucing a DC signal, iming is unimporan, bu fas changing signals may deviae oo far during shor iming errors. The plo below shows slow and fas sloping lines, wih iming errors a sample #5. oe ha he deviaion from sraigh line is larger for he fas rising case. JFas Fas JSlow Slow When examining a sine wave one, we can recognize he ime porion of he signals ha are less suscepible o jier. The peak (lef plo) as well as he dip are low slope regions. Conversely, here are ime regions (righ plo) of high suscepibiliy o iming errors. Maximum slopes occur during he highes frequency and he highes ampliude signals. Lower damage due o jier occurs a lower frequency and ampliude signals VOUT2K VOUT2K

2 2 The nex plo shows he oucome of inroducing a random amoun of ime error o he sampling clock. oe ha he error is small when he signal reaches peak (and deep) values. Larger errors occur a he high slope regions. The random sampling ime errors inerac wih he signal, yielding a signal dependen error. 1 A Error We now inroduce a non random jier error. The plo below shows he effec of a 1KHz sinusoidal jier modulaion on 2KHz, 1KHz and 2KHz ones. The plos are based on 1ns jier ampliude (sampling frequency is se o KHz). The jier adds a pair of sideband ones o each of he signals. The sideband frequencies are 1KHz away from he one (for he case of 1KHz jier modulaion). oe ha sideband ampliude increases proporionally wih increased one frequency. The horizonal axis is frequency and he verical is a db scale. f2kj1ps f1kj1ps f2kj1ps We nex examine a plo showing jier modulaion by a dual one signal, 1KHz and 3KHz. The sidebands frequencies are locaed 1KHz and 3KHz away from he 1KHz one. VO2one

3 3 Increasing he jier frequency increases he frequency inerval beween he one and he sidebands. Wha will happen when he jier modulaion is above yquis? The nex plo shows a 1KHz one jier modulaed by a 23.5KHz one (1KHz above yquis). The sidebands are locaed a 1KHz away from abou 12KHz. The "new cener frequency" is f(yquis) - f(signal) = = 12.5KHz VOA Le us raise he jier one frequency o 1KHz above he sampling frequency (45.1KHz jier). The oucome is idenical o ha of he 1KHz case. One may view he "mechanism" as a ime difference beween wo waves, one being he clock signal and he oher an analog wave. A relaive moion beween he waves causes no error if he clock "wobble" is a complee full cycle during he ime beween wo sampling clocks. Modulaing he clock a exacly he sampling frequency will "complee he cycle" a he sampling imes, which are he only poins of ineres. Modulaion by,say, 1KHz above he sampling frequency leaves an undesirable ime error due o he moion above he sampling speed.. 12 VOAS There are a number of aricles wrien abou "Jier bandwidh". I have seen claims o he effec ha jier above yquis does no maer. Ohers claim ha jier frequencies above sampling causes no harm. Such claims may be rue in some conex (which I am sill unaware of a he ime of wriing his aricle). In general, one has o be cauious abou ignoring jier a any frequency.

4 4 The case of single or dual one jier is no commonly encounered. I is useful for undersanding various frequency and ampliude relaionships. The case of muliple one becomes pracical when examining elecrical coupling of digial daa energy o clock circuiry. Le us examine he coupling of MSB digial daa energy ino he clock circui. When esing a sine wave, he mos significan bi (MSB) follows a square wave paern a he one frequency. I hus can be viewed as a decaying sum of odd harmonics. The impac due o such jier is shown below for a 2KHz one. VMSB oe: The more informed reader may be puzzled. Clearly, a modulaion by he mos significan bi (square wave) conains only odd harmonics. Should we no expec sidebands a odd muliples of he fundamenal frequency (6, 1, 14, 18KHz...)? The previous cases of one modulaion were based on a jier source independen from he one frequency. In he case of coupling some of he daa bis energy o he clock, he clock deviaion depends on he signal iself (in a ime relaed manner), hus he unexpeced side lobe frequencies. Le us expand he case of signal independen jier. In pracice, we rarely face a pure one jier modulaion. In fac, much of he jier problem is random in naure. We will nex widen our invesigaion o a jier source wih he energy spread randomly beween 1KHz and 4KHz. As expeced, he "side bands" energy resides in he frequency regions 1KHz o 4KHz away from he one: VBL

5 Le us view he impac of he same band limied jier on a dual one (6KHz and 13KHz) oe ha he higher frequency one is associaed wih higher energy side band regions. V2f When raising he lower one o 7.5KHz, we noice ha he upper one sidbands dominae he energy in he overlap region (above 1KHz). v2f Much has been wrien abou he level of accepable jier. The plos below show he sidebands a wo jier ampliudes. Jier ampliude of 1pS (lef plo) and 1pS (righ plo) wih 3KHz clock modulaion: V1ps V1ps

6 6 How much jier is accepable? All he plos so far were based on infinie word lengh. Jier side lobes are more noiceable wih more bis. The plos below show he impac of same jier on a 16 bi sysem. The sidebands wih 1pS jier (lef plo) are above he noise floor. The righ plo (1pS) shows ha 16 bi runcaion dominaes he noise floor v1ps 8 v1ps We have seen he impac of sample ime errors on analog o digial conversion. The subjec of jier is well covered by lieraure covering modulaion heory (specifically narrow band FM). This aricle concenraed on PCM coding. Much insigh may be gained by classifying jier in o wo caegories: a: Sysemaic jier such as narrow band and pure ones end o generae unwaned energy concenraion a frequencies relaed o he signal and jier frequencies (he frequency relaionships are no always rivial). Sysemaic jier occurs mosly due o coupling of periodic signals ino he clock circui. b:wideband random jier ends o modulae (shape) he noise floor in a signal dependen manner (more impac when higher frequency and ampliude signals are presen). Random jier is ofen due o inheren imperfecions of he clock circuiry iself, and o coupling of high speed digial daa ha is unrelaed o signal waveform. Mos coupling mechanisms are due o noisy power supplies, improper ground pah and elecromagneic inerference. Good design can remove much of he clock jier and provide clean seady clock o he conversion process. Hardware relaed issues The pervious secion poins ou he undesirable impac of jier on signal recording and reproducion. This secion will poin ou a number of common sources for jier in analog o digial and digial o analog converers.

7 Oscillaor Jier 7 A/D and D/A converers require low jier clocks. I is easies o achieve he lowes jier when using an inernal crysal clock, bu such a seup is no always pracical. Many cases require lock o exernal clock (muliple devices, sand alone D/A, house sync and more). Crysals are inherenly very low jier devices, and wih proper oscillaor circuiry, offer very high immuniy o power supply noise and oher inerference. Crysals can be cu in various ways. Some are made o oscillae in a fundamenal frequency mode, and ohers are made for harmonic oscillaion (for higher frequency applicaions). RLC half bridge, Feedback bridge, Modified Meacham and Pierce oscillaor circuis are all good circuis for fixed frequency fundamenal oscillaions. The inegraed circui single inverer Pierce configuraion is he mos widely used due o is cos effeciveness. Clock synchronizaion requires he abiliy o vary he frequency over a a specified range. The crysal cu is hinner, increasing he series resonance capaciy (moional capaciy). When coupled wih exernal volage conrolled capaciors (varacors), one may vary he frequency of oscillaions over some limied range (up o a few hundred pars per million is possible). Such VCXO circuis (volage conrolled crysal oscillaor) are more complex. A few basic poin o keep in mind: 1. Mos VCXO's are based on fundamenal frequency oscillaions (i is very difficul o pull a crysal a an harmonic frequency). 2. I is easier o cu a VCXO crysal for a given a pull range a higher frequencies. 3. Crysals can be made o resonae in series mode or in parallel mode. The auhor of his aricle has been geing lower jier wih series resonance circuis. A good "sand alone" crysal oscillaor yield very low level of jier, ye here are wo area of concern regarding jier: 1. Proper clock inerfacing o he converer. 2. oisy or unseady oscillaor conrol volage (for he pullable crysal case). Inerfacing he clock The oscillaor clock edge provides he iming of he converer circui (ofen hrough a series of frequency dividers). Sample iming occurs when he clock edge crosses a given logic level. Finie rise (or fall) ime, propagaion delays and noisy logic hreshold can modulae clock iming. This facors are depend on supply volage hus noisy supplies can cause jier. The problem is exacerbaed when he coupling beween he clock supply and he converer supply is poor. The following plo shows a firs order approximaion for CMOS gae wih 1% power supply noise. The clock V() crossing of he hreshold Vh() in noise dependen. An increase in supply volage speeds up he rise ime (earlier crossing) and pulls up he hreshold, (laer crossing) hus some cancellaion occurs when using clock rise ime. The converse is rue when using clock fall ime (slower fall and lower hreshold have an addiive impac). V 5 Vh

8 8 The power supply impac on rise/fall ime for HCMOS echnology is in he order of magniude of 1nS per vol of noise (abou 5pS per vol o he hreshold mid poin). Oher echnologies and circui opologies may yield higher levels of power supply noise immuniy. While a faser rise ime echnology could yield beer resuls in heory, some faser logic families acually exacerbae he problem because he fas ransiions become he cause of power supply noise and elecromagneic inerference. ECL logic (emier coupled logic) provide a good soluion for clean high speed swiching, bu a a cos of higher power dissipaion. As always, achieving opimal resuls requires he designer o ake ino accoun he various jier generaing mechanisms and find he opimal se of radeoffs. The above discussion was focused on clock o converer inerface. Any addiional circuiry beween he clock and he converer (dividers, buffers ec) may add o he jier wih mechanisms described above. oisy or unseady oscillaor conrol volage We now proceed o cover he bigger offender: he impac of unwaned volage variaion in he pullable oscillaor. Le us examine a ypical VCXO, operaing a say MHz (256 X sampling rae), wih a +/- 15ppm (pars per million) pull range. From a ime poin of view, each clock period may be pulled by abou +/- 13pS, which seem small, ye a KHz sampling rae requires couning of 256 such clocks periods for each sample. The accumulaed ime difference hus becomes abou 3.4nS. Clearly, such full scale clock modulaion is inappropriae, bu wih +/-3.4nS due o -5V conrol volage change yields 136pS of peak o peak jier for 1mV of conrol volage flucuaions. Much of he volage flucuaion is due o he PLL circuiry, hough power supply noise becomes a conribuing facor wih some specific ypes of PLL. Very lile of he flucuaion is due o semiconducor noise volage. PLL circuis Achieving lock beween he oscillaor and he incoming clock requires generaion of a conrol signal, for he purpose of forcing he VCXO o rack he ime varying inpu clock. The phase and frequency comparison is commonly done by a phase deecor, generaing a correcion signal for he pullable oscillaor. Such negaive feedback usually incorporaes some filering beween he phase deecor and he oscillaor. The smoohing (filering) of he phase deecor signal is designed o respond fas enough for racking he variaions in he inpu clock rae, bu slow enough o filer ou as much noise as possible. Mos circuis uilize a 2 pole filer a 1-1Hz. Higher order filers are more difficul o operae in he conex of a negaive feedback loop. Some devices uilize wo or more PLL circuis. The improvemen due o addiional poles is marginal, and he main idea is o lower he filer frequency of he second PLL (noise volage improvemen is proporional o square roo of he bandwidh).

9 9 Exclusive Or phase deecor When using a simple exclusive-or logic gae as he phase deecion circui, he oscillaor locks o he inpu clock a 9 degree phase shif. The plo below shows he wo waveforms wih power supply noise imposed on he circui. The waves are shifed verically o ease he visual separaion. 5 Inpu Osc ex we show he oupu of he exclusive-or gae. The oupu signal PLL() sill conains power supply noise. 5 PLL The filer does no have o provide perfec smoohing of he square wave ino a DC signal. The fundamenal and harmonics of he square wave fall a ineger muliples of he sampling rae, and jier modulaion is ransparen a such frequencies. Similarly, he filer does remove mos of he random noise coupled from he supply line. A random noise source of.1v ampliude wih fla frequency specrum from o 2MHz bandwidh yield only 3uV of noise when filered by a 2Hz low pass filer. The real offender is any significan noise energy below he filer cuoff poin. Such energy is mosly due o he coupling of digial logic signals hrough supply and ground lines. Anoher problem associaed wih he exclusive or gae is he phase shif (9 degrees) beween inpu an oupu. Some may argue ha he fixed 1uS exra ime delay is a problem in iself. The auhor of his aricle is no convinced of ha, bu in any case, an inpu clock variaion of only 1ppm a KHz ranslaes ino abou 22pS shif in ime. Any sysemaic (or periodic) low frequency conen becomes jier.

10 1 The commonly used digial phase frequency deecor Mos phase lock loop circuis in audio are based on a digial phase deecor uilizing four memory cells (flip flop circuis) and a few logic gaes. Such circuis are found in he widely used 74HC446 inegraed circuis. The advanages of such a circui are: 1. Lock is achieved wih zero phase shif (hus no delay or phase modulaion). 2. Much freedom form supply noise effecs. Such phase deecors are "idle" mos of he ime. The (ri sae) oupu is kep a is high impedance mode unil called upon o provide a narrow correcion pulse. The inernal memory is se and rese coninuously (se by he inpu clock and rese by he oscillaor). When in lock, a pulse appears a he deecor oupu wih duraion which is he difference in ime beween he inpu and he oscillaor rising edges. Such correcion is ofen referred o as "pump up / pump down". A sequence of such pulses (wih appropriae polariy), when applied o he smoohing filer, provides he conrol volage for he VCXO. Clearly, while in lock he correcion pulses are narrow and he pump is mosly disconneced from he power supply line. Thus he improved supply immuniy. (The supply noise impacs he conrol volage only during he shor correcion pulses). The problem wih he familiar 74HC446 and similar variey, is ha phase deecor has a "dead zone" (referred o as backlash) of abou 2nS of ime, when he deecor does no respond o he inpu condiions. When he inpu frequency moves away from he oscillaor frequency, a leas 2nS are required before he deecor sars generaing an oupu pulse. The oucome is an undesirable "moor boaing" effec. Lowering he filer cuoff slows down he modulaion bu he overall effec can no be filered ou. The backlash and he varying loop gain over he conrol volage range make such phase deecors problemaic. Special praise is in order for he designers of he laes generaion 74HC946 a Philips Semiconducors. This device operaes on he same principles bu overcomes he backlash, variable gain and ineracion wih circui capaciy problems. The 74HC946 uilizes a swiched curren charge pump, wih no dead zone. The curren pump provides an addiional benefi of beer power supply noise immuniy. A Lavry Engineering we will no use he 446, bu we found a couple of slos for he 946. Oher sources of jier While covering of all jier issues is beyond he scope of any aricle, he reader mus have figured ou by now ha classical phase lock loop echniques offer lile in he way of rejecion below he loop filer cuoff frequency. Even wih a perfec VCXO, power supply, ground, phase deecor and all, incoming jier residing in he frequency band below he cuoff frequency will be passed on o he VCXO. Achieving and mainaining lock wih he classical PLL approach ses limis as o how far one can lower he cuoff frequency. Much has been said and demonsraed regarding he clock inerference caused by he daa embedded in digial audio signals. Such inerference is a is wors when boh audio daa and he clock are combined ino a composie signal, where ransmission bandwidh limiaions conribue grealy o jier. Given any audio one, one can find some sysemaic and periodic digial paern behavior. Thus a large scale (5V) digial periodic bi paern inerference source. The coupling of digial paerns due o audio frequencies below he loop cuoff may remain unfilered and cause jier.

11 11 CrysalLock (TM) is a beer approach We nex describe he basics of he lock circuiry found in Lavry Engineering D/A converers (and some of our A/D converers). Le us describe he case for an MHz VCXO wih pull range of +/- 15ppm. We generae he -5V conrol volage wih a 12 bi D/A circui. The D/A sep size is abou 1.2mV. Each sep changes he clock period by.64ps, so afer 256 clocks we end up wih abou 1.6pS of jier over a KHz clock ime period. Le us now run he VCXO wih a fixed D/A code for a while, say for 1 seconds, allowing i o compleely disregard any variaions in inpu jier. Afer 1 seconds have elapsed, we sep he D/A up (or down) by one code, varying he oscillaor frequency by.73 ppm (3ppm pull range divided by 496 seps). Abou 1 seconds laer, we may (or may no) sep he D/A again bu again, only by.73ppm. Such clock is exremely seady bu can we ignore he inpu daa rae flucuaions? Can we "break" he igh relaionship beween clock rae and inpu daa rae? If he clock is slighly faser hen he daa rae, are we no going o "run ou of daa"? If he clock rae is slighly slower hen he daa rae, do no we have "oo much daa" for our clock? The answer is simple: we pre sore jus enough daa in a emporary buffer memory, and clock one sample a a ime from he memory wih our seady clock. While reading daa ou of he memory (wih he seady clock), new inpu daa coninues o fill he memory from is inpu side. Filling he memory may be done wih a lo of jier ye he oupu side is ignoring i compleely. The process can no coninue indefiniely, because a difference in inpu and oupu clock raes will evenually overflow (or underflow) he memory. To avoid he overflow (or underflow), we uilize a processor, responsible o measure and deermine if he memory is geing oo full or oo empy. The processor checks for an average long erm rend and makes he small single sep clock adjusmen as describe above. A single sep adjusmen goes a long way: Assume ha he D/A is off by one sep, hen we can operae wih "wo word deep" memory buffer wihou overflow for 3 seconds! In pracice, he buffer memory is more hen wo words, because he average inpu frequency is no consan. An "unrealisic" 1ppm per second inpu rae drif requires pre sorage of abou 5 words of daa for 1 second D/A sepping, or an 5 word memory for 1 seconds of D/A updae rae. Our DA924 converer operaes a an updae rae of abou 1-2 seconds. The very small and infrequen sepping reflec only he very long average drif of incoming daa, hus in effec provide a brick wall filer wih an "equivalen cuoff frequency" 1 imes lower hen he bes classical PLL circuis. The conrol volage D/A oupu is highly filered wih a large ime consan o smooh he iny seps, and, hough inherenly cleaner hen CMOS gaes, o rejec any remaining power supply noise and oher inerference.