Challenges in the Design of High-Speed Clock and Data Recovery Circuits

Transcription

1 TOPICS IN CIRCUITS FOR COMMUNICTIONS Challenges in he esign of High-Speed Clock and aa Recovery Circuis ehzad Razavi, Universiy of California, Los ngeles STRCT This aricle describes he challenges in he design of monolihic clock and daa recovery circuis used in high-speed ransceivers. Following an overview of general issues, he ask of phase deecion for random daa is addressed. Nex, Hogge, lexander, and half-rae phase deecors are inroduced and heir rade-offs oulined. Finally, a number of clock and daa recovery archiecures are presened. INTROUCTION Clock and daa recovery (CR) is a criical funcion in high-speed ransceivers. Such ransceivers serve in many applicaions, including opical communicaions, backplane rouing, and chip-o-chip inerconnecs. The daa received in hese sysems are boh asynchronous and noisy, requiring ha a clock be exraced o allow synchronous operaions. Furhermore, he daa mus be reimed such ha he jier accumulaed during ransmission is removed. CR circuis mus saisfy sringen specificaions defined by communicaion sandards, posing difficul challenges o sysem and circui designers. This aricle presens he challenges in he design of high-speed CR circuis, focusing on monolihic implemenaions in very large scale inegraed (VLSI) echnologies. The nex secion of he aricle addresses general issues in CR design dealing wih phase deecors for random daa. We also describe a number of CR archiecures and heir design rade-offs. GENERL CONSIERTIONS In order o perform synchronous operaions such as reiming and demuliplexing on random daa, high-speed receivers mus generae a clock. s illusraed in Fig. 1a, a clock recovery circui senses he daa and produces a periodic clock. flipflop (FF) driven by he clock hen reimes he daa (i.e., i samples he noisy daa), yielding an oupu wih less jier. s such, he flipflop is someimes called a decision circui. The clock generaed in he circui of Fig. 1a mus saisfy hree imporan condiions [1]: I mus have a frequency equal o he daa rae; for example, a daa rae of 10 Gb/s (each bi 100 ps wide) ranslaes o a clock frequency of 10 GHz (wih a period of 100 ps). I mus bear a cerain phase relaionship wih respec o daa, allowing opimum sampling of he bis by he clock; if he rising edges of he clock coincide wih he midpoin of each bi, he sampling occurs farhes from he preceding and following daa ransiions, providing maximum margin for jier and oher iming uncerainies. I mus exhibi a small jier since i is he principal conribuor o he reimed daa jier. Simple CR Circui We now consider a simple CR circui, analyzing is behavior and shorcomings. s illusraed in Fig. 1a, o generae he clock waveform we employ a volage-conrolled oscillaor (VCO), and o define is frequency and phase we phase-lock he VCO o he inpu daa using a FF operaing as a phase deecor (P). The low-pass filer () suppresses ripple on he oscillaor conrol line. lso, o reime he daa, we add anoher FF ha is clocked by he VCO oupu. Noe ha he recovered clock, ou, drives he pu of he phase deecor and he clock inpu of he reimer. The circui of Fig. 1b operaes as follows. Upon urnon, he FF muliplies he edge-deeced daa by he VCO oupu, generaing a bea ha drives he VCO frequency oward he inpu bi rae. If he iniial difference beween he VCO frequency and he daa rae is sufficienly small, he loop locks, esablishing a well-defined phase relaionship beween and ou. In fac, wih he bang-bang characerisic provided by he FF phase deecor, he daa edges sele around he zero-crossing poins of he clock. Even for a sligh /02/$ IEEE IEEE Communicaions Magazine ugus 2002

2 phase error, he P generaes a large oupu, driving he loop oward lock. The simple CR circui of Fig. 1b suffers from a number of drawbacks. Firs, he P may produce full digial oupus for run lenghs greaer han one, hereby creaing subsanial ripple on he oscillaor conrol volage and hence jier a he oupu. Second, since he P samples he clock by he daa, whereas he decision circui samples he daa by he clock, daa reiming exhibis significan phase offse a high speeds. Typical flipflops display unequal delays from he pu o he oupu and from he clock inpu o he oupu. Thus, if, for example, he -o- delay is longer han he -o- delay by T, he P locks such ha he daa leads he clock by T, sampling he clock closer o he zero crossing afer he daa experiences he inrinsic delay of he P. The VCO oupu suffers from even more delay as i propagaes hrough he decision circui, sampling he daa far from he middle of he eye. In oher words, if he difference beween he -o- and -o- delays is equal o T, he reiming suffers from a skew of 2 T. The hird drawback of he simple CR archiecure of Fig. 1b relaes o he feedhrough of daa o he VCO oupu hrough boh flipflops. The oupu phase is disurbed on arrival of each daa ransiion, requiring ha he VCO be followed by a buffer sage providing significan reverse isolaion. Clock recovery circui ecision circui VCO Figure 1. a) The role of a CR circui in reiming daa; b) an example of CR implemenaion. FF 1 Reimer ou ou PHSE ETECTORS FOR RNOM T s menioned earlier, Ps for random daa mus provide wo essenial funcions: aa ransiion deecion Phase difference deecion Furhermore, he skew effec described above makes i desirable o reime he daa inside he phase deecor, hus eliminaing he explici decision circui and he skew associaed wih i. This observaion immediaely leads o anoher: if he daa is o be reimed by he VCO oupu, hen he flipflop(s) in he phase deecor mus be srobed by he laer raher han he former. In oher words, unlike he FF P of Fig. 1b, he phase deecor mus sample he incoming daa by he VCO signal. THE HOGGE PHSE ETECTOR How can a P deec daa ransiions if i samples he daa by he VCO oupu? single FF fails o operae as a phase deecor if i is used in such a mode. However, recognizing ha a FF produces a delayed replica of he inpu daa, we can arrive a a synchronous edge deecor (Fig. 2a). Since sample changes only on he edges, = conains pulses whose widh represens he phase difference beween and. I is imporan o noe ha he circui produces a pulse for each daa ransiion, providing edge deecion, and he widh of he oupu pulses varies linearly wih he inpu phase difference, suggesing ha he circui can operae as a linear P. We call his ype of oupu proporional pulses. FF 1 FF 2 Figure 2. a) simple P using synchronous edge deecion; b) a Hogge phase deecor. X IEEE Communicaions Magazine ugus

3 The Hogge opology is a linear phase deecor, generaing a small average as he phase difference approaches zero. Thus, a charge pump driven by a Hogge P experiences lile aciviy when he CR loop is locked. Clock early Clock lae S 2 S 3 S 1 S 1 S 2 S 3 S 1 S 2 FF 1 FF 1 2 S 3 S 1 S 3 X S S 0 2 FF 3 FF 4 S 3 S 1 S 0 S 2 T 1 (c) Figure 3. a) Three-poin sampling of daa by clock; b) an lexander phase deecor. I may appear ha he opology of Fig. 2a saisfies he requiremens of a phase deecor and can herefore be used as such. Unforunaely, however, he average value of he oupu is a funcion of he daa ransiion densiy, failing o uniquely represen he phase difference for various daa paerns. For example, he average oupu remains unchanged if he ransiion densiy falls by a facor of wo and he phase difference rises by he same facor. In oher words, wo differen phase errors may resul in he same dc oupu, leading o false lock. To overcome he above ambiguiy, he proporional pulses mus be accompanied by reference pulses. The laer are pulses ha appear only on daa edges bu exhibi a consan widh, eliminaing he paern dependency. How can reference pulses be generaed? We noe ha if he reimed daa (a poin ) in Fig. 2a is delayed by half a clock cycle, T /2, and XORed wih iself, pulses of widh T /2 are produced for each daa ransiion. s depiced in Fig. 2b, he difference beween he areas under X and can be viewed as he P oupu, eliminaing he ambiguiy due o ransiion densiy. Noe ha under locked condiion, X and produce equal pulse widhs. This circui is called he Hogge phase deecor [2]. Le us summarize our hough process hus far. In order o avoid skews in he decision circui, we choose o sample he daa by he clock even in he P. This in urn requires explici edge deecion, carried ou by a FF and an XOR gae. Finally, we produce a reference pulse o eliminae ambiguiy for differen daa ransiion densiies. Recall ha he principal moivaion behind he above developmen is o reime he daa inside he P. oes he Hogge P accomplish his? Indeed, boh flipflops in Fig. 2b operae as decision circuis as well, hereby providing reimed daa. I is insrucive o examine he behavior of he Hogge P he presence of finie delays in he flipflops. Owing o he -o- delay, T, of FF 1, changes T seconds afer he clock rises, yielding a pulse a he oupu ha is T s wider han he acual phase difference beween and. On he oher hand, he -o- delay of FF 2 simply shifs he pulses a by T, sill producing a pulsewidh equal o one clock period. s a resul, X coninues o produce pulses of widh T /2 for each daa ransiion. This means, wih a zero inpu phase difference, he proporional pulses are wider han he reference pulses by T s. Thus, under locked condiion, and mus susain a skew of T o equalize he widhs of he X and pulses. The above skew effec becomes a serious issue a high speeds. Since T can be a significan fracion of he clock period, a sysemaic phase offse of several ens of degrees may arise afer he loop is locked, degrading he clock phase margin and hence he jier olerance. In order o resolve his difficuly, we can eiher narrow he proporional pulses by T [2] or widen he reference pulses by he same amoun. drawback of he Hogge P sems from he half-cycle skew beween he wo XOR oupus [3, 4]. Under locked condiion, he P produces he reference pulse afer he proporional pulse, hereby creaing a skew of T /2 beween he 96 IEEE Communicaions Magazine ugus 2002

4 wo. s a resul, he VCO phase (which is proporional o he inegral of he conrol volage) is severely disurbed. The phase deecor can be modified o ameliorae his issue [4]. The Hogge opology is a linear P, generaing a small average as he phase difference approaches zero. Thus, a charge pump driven by a Hogge P experiences lile aciviy when he CR loop is locked. This behavior is in conras o ha of he bang-bang P of Fig. 1b. THE LEXNER PHSE ETECTOR The lexander configuraion is anoher example of Ps providing inheren daa reiming. Following our reasoning for he Hogge P, we noe ha his propery requires ha he daa be sampled by he clock, bu a single FF does no suffice. Noneheless, if he clock srobes he daa waveform a muliple poins in he viciniy of expeced ransiions, he resuling samples can provide he necessary informaion. Figure 3a illusraes he lexander P principle, also known as he early-lae deecion mehod. Uilizing hree daa samples aken by hree consecuive clock edges, he P can deermine wheher a daa ransiion is presen, and wheher he clock leads or lags he daa. In he absence of daa ransiions, all hree samples are equal and no acion is aken. If he clock leads (is early), he firs sample, S 1, is unequal o he las wo. Conversely, if he clock lags (is lae), he firs wo samples, S 1 and S 2, are equal bu unequal o he las sample, S 3. Thus, S 1 S 2 and S 2 S 3 provide he earlylae informaion: If S 1 S 2 is high and S 2 S 3 is low, he clock is lae. If S 1 S 2 is low and S 2 S 3 is high, he clock is early. If S 1 S 2 = S 2 S 3, no daa ransiion is presen. The foregoing observaions lead o he circui opology shown in Fig. 3b [5]. Flipflops FF 1 and FF 2 sample heir pus on he rising edge of, producing S 3 and S 1, respecively. Flipflop FF 3 samples on he falling edge of, and flipflop FF 4 delays his sample by half a clock cycle, generaing S 2. Noe ha he sampling poins are defined by FF 1 and FF 3 ; he oher wo FFs merely serve as delay elemens. Le us examine he waveforms a various poins in he lexander P o gain more insigh ino is operaion. s depiced in Fig. 3c, he firs rising edge of samples a high daa level. The second rising edge of hen accomplishes wo asks: i produces a delayed version of he firs sample a he oupu of FF 2 and samples he low level on he inpu daa. The values of S 1 and S 2 are herefore valid for comparison a = T 1, remaining consan for one clock period. On he firs rising edge of in Fig. 3c, FF 1 samples a high level on he inpu daa, and on he nex rising edge, FF 2 reproduces his level. The key poin here is ha he choice of clock phases for he four FFs ensures ha S 1, S 2, and S 3 reach valid levels for comparison a = T 1, and remain a hese levels for one clock period. s a resul, he XOR gaes always generae valid oupus simulaneously. The lexander P is a bang-bang sysem, exhibiing a very high gain in he viciniy of φ = 0. Consequenly, a CR loop uilizing his P locks such ha S 2 coincides wih he daa zero crossings. While exhibiing a bang-bang characerisic, he lexander P offers wo criical advanages over a simple FF P. Firs, i reimes he daa auomaically, producing a valid daa waveform a he oupu of FF 1 and FF 2 in Fig. 3b. Second, in he absence of daa ransiions, i generaes a zero dc oupu, leaving he oscillaor conrol undisurbed. s a resul, for long daa runs, he VCO frequency drifs only due o device elecronic noise raher han due o a high or low level on he conrol line. HLF-RTE PHSE ETECTORS very high speeds, i may be difficul o design oscillaors ha provide an adequae uning range wih reasonable jier. For his reason, CR circuis may sense he inpu random daa a full rae bu uilize a VCO running a half he inpu rae. This echnique also relaxes he speed requiremens of he phase deecor and, in some CR configuraions, he frequency dividers. Called half-rae archiecures, such CR opologies require a phase deecor ha provides a valid oupu while sensing a full-rae random daa sream and a half-rae clock. I is imporan o noe ha none of he hree Ps sudied hus far can operae wih a half-rae clock. However, daa ransiions may be deeced properly if boh edges of he half-rae clock are uilized o sample he inpu daa. Consider he opology shown in Fig. 4a, where wo laches, L 1 L 2, operae on opposie edges of he clock. Noe ha each lach is ransparen for half of he clock cycle, passing daa ransiions o is oupu. ssuming leads by T and L 1 is ransparen when is high, we observe ha 1 goes high before falls and remains high unil rises. In oher words, L 1 produces a pulse widh equal o T /2 + T. On he oher hand, if L 2 is ransparen when is low, 2 goes high when falls and remains high only unil falls. Tha is, L 2 generaes a pulse widh of T /2 T. Thus, 1 2 exhibis a pulse of widh T for each daa ransiion. The above sudy implies ha he simple opology of Fig. 4a can indeed operae as a linear phase deecor because i: eecs daa edges Produces proporional pulses However, as wih he Hogge opology, his circui mus also provide a reference oupu o uniquely represen he phase error for differen daa ransiions. To his end, le us follow he laches wih wo more (creaing a maser-slave flipflop in each pah) and XOR he oupus (Fig. 4b). In he presence of daa ransiions, he oupus of L 3 and L 4 change on he falling and rising edges of he clock, respecively. s a resul, C conains a pulse widh of T /2 for each inpu daa edge, serving as he reference oupu [6]. How does a CR loop employing he P of Fig. 4b lock o random daa? If he clock edge is o srobe he daa in he middle of he eye, he proporional pulses are T /4 s wide, whereas very high speeds, i may be difficul o design oscillaors ha provide an adequae uning range wih reasonable jier. For his reason, CR circuis may sense he inpu random daa a full rae bu uilize a VCO running a half he inpu rae. IEEE Communicaions Magazine ugus

5 criical difficuly in modern CR circuis sems L 1 from he use of T low supply volages. The gain of VCOs mus increase as + V ou1 V ou1 he supply is scaled down L 2 because he uning V ou1 V ou2 range mus remain a consan percenage of he cener frequency. L 1 L 3 s a resul, for a given ripple on is conrol line, he VCO suffers from C ou1 V ou1 greaer jier. L 2 L 4 ou2 V ou2 Figure 4. a) simple linear half-rae P; b) a complee half-rae P. he reference pulses are T /2 s wide. The dispariy beween he average values of hese oupus is removed by scaling down he effec of he oupu of he second XOR by a facor of wo, ha is, halving he corresponding curren source in he charge pump. The half-rae P of Fig. 4b also reimes and demuliplexes he daa, producing wo sreams a he oupus of L 3 and L 4. The linear characerisic of he circui allows simple formulaion of he loop dynamics. Le us now consider he early-lae mehod for half-rae operaion. Since he lexander P already requires sampling on boh clock edges for full-rae deecion, i mus employ addiional phases of he clock if i is o operae in he half-rae mode. Shown in Fig. 5a, he soluion involves sampling he daa by boh he in-phase and quadraure phases of he clock, I and, respecively. Now, 1, 2, and 3 play he same role as he consecuive samples in a full-rae counerpar. s depiced in Fig. 5b, he implemenaion incorporaes hree FFs sampling he daa by I and, and wo XOR gaes producing 1 2 and 2 3. Under he locked condiion, he rising edge of occurs in he viciniy of he daa zero crossings. CR RCHITECTURES Wih our foregoing sudy of Ps, we can now develop complee CR archiecures. Each archiecure mus include: Frequency and phase acquisiion o ensure lock despie process and emperaure variaions of he VCO frequency aa reiming inside he P o avoid sysemaic skews criical difficuly in modern CR circuis sems from he use of low supply volages. The gain of VCOs mus increase as he supply is scaled down because he uning range mus remain a consan percenage of he cener frequency. s a resul, for a given ripple on is conrol line, he VCO suffers from greaer jier. mehod of alleviaing his issue is o decompose he VCO conrol ino fine and coarse inpus, allowing he laer o remain quie afer he sysem is phase-locked. This concep is described in he conex of some CR archiecures. FULL-RTE REFERENCELESS RCHITECTURES Frequency deecors capable of handling random daa obviae he need for exernal reference frequencies. Figure 6a depics a referenceless archiecure [7], where loop I employs a frequency 98 IEEE Communicaions Magazine ugus 2002

6 I Figure 5. a) The use of quadraure clocks for half-rae phase deecion; b) a half-rae binary P. deecor (F) [7] and loop II incorporaes one of he Ps sudied in an earlier secion. Upon sarup or loss of phase lock, he F produces a dc level ha drives VCO frequency oward he inpu daa rae. When he frequency error falls wihin he capure range of loop I, he P akes over, phase-locking he clock o he daa. The above archiecure enails wo issues. Firs, as he CR circui ransfers he conrol of he VCO from he F o he P, he wo loops may inerac so heavily ha he overall sysem fails o phase-lock. In his case, he wo loops coninue o figh indefiniely. Second, wih he acual random daa produced in a nework, shor-erm specral lines close bu unequal o he nominal daa rae may appear occasionally, possibly confusing he frequency deecor. For hese reasons, he bandwidh of he frequency-locked loop (FLL) is ypically chosen o be much smaller han ha of he PLL. These issues mus be sudied carefully for each specific design and applicaion. Noe ha his archiecure employs only one conrol line for he oscillaor and mus herefore ensure a very small ripple. I is possible o modify he sysem as shown in Fig. 6b, where loop II drives only he coarse conrol. This modificaion I also permis independen choice of he PLL and FLL bandwidhs. RCHITECTURES WITH EXTERNL REFERENCES Recall ha i is desirable o decompose he VCO conrol ino fine and coarse inpus. CR archiecure uilizing such a scheme is shown in Fig. 7a [8]. Here, loop I phase-locks VCO 1 o he inpu daa hrough fine conrol. Since he gain of VCO 1 wih respec o fine inpu is relaively low, ripple on his line ranslaes o a small jier a he oupu. Of course, he fine conrol may no provide enough uning range o encompass process and emperaure variaions. Loop II is herefore added o lock VCO 2, a replica of VCO 1,o Nf REF, wih he resuling conrol volage applied o he coarse inpu of VCO 1 as well. If Nf REF is exacly equal o he inpu daa rae and he wo VCOs mach perfecly, he fine conrol of VCO 1 sabilizes a a volage equal o ha on he coarse conrol. The low-pass filer consising of R 1 and C 1 suppresses he ripple generaed in loop II, hereby presening a low-noise conrol o VCO 2. While reducing he effec of ripple, he archiecure of Fig. 7a faces wo issues. Firs, ineviable random mismaches beween he wo X Upon sarup or loss of phase lock, he F produces a dc level ha drives VCO frequency oward he inpu daa rae. When he frequency error falls wihin he capure range of loop I, he P akes over, phase-locking he clock o he daa. Reired daa Reimed daa P P I VCO I VCO Coarse Fine Figure 6. CR archiecures wih a) F and P; b) coarse and fine VCO conrol. IEEE Communicaions Magazine ugus

7 Loop I Loop I P V fine VCO f ou P CP VCO f ou C 1 V course R 1 Lock deecor CP Loop II f REF PF VCO 2 PF %N Loop II f %N f REF Figure 7. CR archiecure using a) wo VCOs; b) sequenial locking. VCOs lead o a subsanial cener frequency mismach even hough he oscillaors share he same coarse inpu. For his reason, loop I mus sill achieve a sufficienly wide capure range o guaranee lock despie he iniial frequency error. Wih a ypical frequency mismach of a few percen, random daa Ps may no provide adequae capure range. Second, even if he oscillaors mach perfecly, he incoming daa rae is no exacly equal o Nf REF because he reference frequency in he far-end ransmier is derived from a crysal oscillaor ha may suffer an error of 5 10 ppm wih respec o he f REF generaor in TOPICS IN CIRCUITS FOR COMMUNICTIONS PULISHE IN COLLORTION WITH THE IEEE CIRCUITS N SSTEMS SOCIET SERIES EITORIL OR EITOR Mihai anu gere Sysems 600 Mounain ve., Room 2-328, Murray Hill, NJ 07974, US el: ; fax: [email protected] oung-kai Chen ell Labs, Lucen Technologies 600 Mounain ve. Room 1C-325 Murray Hill, NJ 07974, US el: fax: [email protected] ram Naua Universiy of Twene Elecrical Engineering EL/TN 3242, P.O. ox E Enschede The Neherlands el: (2644) fax: [email protected] SSOCITE EITORS Jan Sevenhans lcael Francis Wellesplein nwerpen, elgium Tel: Fax: [email protected] Erneso H. Perea STMicroelecronics Wireless Communicaion ivision 12, rue Jules Horowiz -.P Grenoble Cedex, France el: (33) GSM: (33) fax: (33) [email protected] he receiver. Consequenly, VCO 1 and VCO 2 operae a slighly differen frequencies, possibly pulling each oher hrough he subsrae or supply lines. The use of differenial swings for boh VCOs alleviaes his issue, bu asymmeries in each circui sill give rise o a finie amoun of crossalk. I is ineresing o noe ha he large bandwidh of loop II parially correcs for he pulling experienced by VCO 2. Loop I, on he oher hand, has a bandwidh commensurae wih he communicaion sandard and hence canno counerac pulling effecs on VCO 1. noher general concern in he archiecure of Fig. 7a relaes o he layou of he wo VCOs. If boh oscillaors incorporae LC anks, he large area occupied by on-chip inducors creaes difficulies in rouing he signal and power lines. Figure 7b shows a relaively simple CR archiecure ha acquires frequency and phase in wo seps. Using a single VCO, he circui firs enables loop II, hereby beginning o lock he oscillaor o Nf REF. The lock deecor moniors he difference beween f and f REF, disabling loop II and enabling loop I when he frequency error drops o a sufficienly small value (e.g., 0.1 percen). Thus, loop I begins wih a frequency error well wihin is capure range, locking he VCO o he daa. The lock deecor coninues o operae so ha loop II can be acivaed again if loop I loses lock as a resul of unexpeced noise. I is insrucive o compare he CR archiecures of Figs. 7a and 7b. oh opologies require an exernal reference, bu he laer need no deal wih frequency mismaches or oscillaor pulling. However, he former allows he use of fine and coarse conrols for he oscillaor, whereas he laer does no. noher issue in he archiecure of Fig. 7b relaes o he ransiion from loop II o loop I. If he swiches ha perform his ransiion disurb he conrol volage significanly, he VCO frequency may jump by a large amoun, falling ou of he capure range of loop I. Thus, he charge injecion and clock feedhrough of he swiches mus be examined carefully. 100 IEEE Communicaions Magazine ugus 2002

8 CONCLUSION High-speed CR design mus deal wih many circui and archiecure issues, including jier, skews, and acquisiion of lock. This aricle has focused on he difficulies in he design of phase deecors and CR archiecures, presening a number of high-speed opologies. In paricular, Hogge, lexander, and half-rae Ps prove useful as he daa raes coninue o increase. The design of VCOs also presens many ineresing challenges, and he reader is referred o [1] and various papers on he subjec for deails. REFERENCES [1]. Razavi, esign of Inegraed Circuis for Opical Communicaions, Chicago: McGraw Hill, [2] C. R. Hogge, Self-Correcing Clock Recovery Circui, IEEE J. Lighwave Tech., vol. 3, ec. 1985, pp [3] L. evio e al., 52MHz and 155MHz Clock Recovery PLL, ISSCC ig. Tech. Papers, Feb. 1991, pp [4] L. evio, Versaile Clock Recovery rchiecure and Monolihic Implemenaion, Monolihic Phase-Locked Loops and Clock Recovery Circuis,. Razavi, Ed., New ork: IEEE Press, [5] J.. H. lexander, Clock Recovery from Random inary aa, Elec. Le., vol. 11, Oc. 1975, pp [6] J. Savoj and. Razavi, 10-Gb/s CMOS Clock and aa Recovery Circui wih a Half Rae Linear Phase eecor, IEEE J. Solid-Sae Circuis, vol. 36, May 2001, pp [7]. Pobacker, U. Langmann, and H. U. Schreiber, Si ipolar Phase and Frequency eecor for Clock Exracion up o 8 Gb/s, IEEE J.Solid-Sae Circuis, vol. 27, ec. 1992, pp [8] J. C. Schey, G. Hanke, and U. Langmann, 0.155, 0.622, and Gb/s uomaic i Rae Selecing Clock and aa Recovery IC for i Rae Transparen SH Sysems, ISSCC ig. Tech. Papers, Feb. 1999, pp IOGRPH EHZ RZVI ([email protected]) received his.sc. degree in elecrical engineering from Sharif Universiy of Technology in 1985, and his M.Sc. and Ph.. degrees in elecrical engineering from Sanford Universiy in 1988 and 1992, respecively. He was wih T&T ell Laboraories and Hewle-Packard Laboraories unil Since Sepember 1996, he has been associae professor and subsequenly professor of elecrical engineering a he Universiy of California, Los ngeles. His curren research includes wireless ransceivers, frequency synhesizers, phase-locking and clock recovery for high-speed daa communicaions, and daa converers. He was an adjunc professor a Princeon Universiy, New Jersey, from 1992 o 1994, and a Sanford Universiy in He served on he Technical Program Commiee of he Inernaional Solid-Sae Circuis Conference (ISSCC) from 1993 o 2002 and is presenly a member of he Technical Program Commiee of Symposium on VLSI Circuis. He has also served as gues edior and associae edior of IEEE Journal of Solid-Sae Circuis, IEEE Transacions on Circuis and Sysems, and Inernaional Journal of High Speed Elecronics. He received he earice Winner ward for Ediorial Excellence a he 1994 ISSCC, he bes paper award a he 1994 European Solid-Sae Circuis Conference, he bes panel award a he 1995 and 1997 ISSCC, he TRW Innovaive Teaching ward in 1997, and he bes paper award a he IEEE Cusom Inegraed Circuis Conference in He was he co-recipien of boh he Jack Kilby Ousanding Suden Paper ward and he earice Winner ward for Ediorial Excellence a he 2001 ISSCC. He is an IEEE isinguished Lecurer and he auhor of Principles of aa Conversion Sysem esign (IEEE Press, 1995), and RF Microelecronics (Prenice Hall, 1998), among oher books. High-speed CR design mus deal wih many circui and archiecure issues, including jier, skews, and acquisiion of lock. CLL FOR PPERS IEEE COMMUNICTIONS MGZINE FETURE TOPIC - GMPLS Scope: The Generalized MuliProocol Label Swiching (GMPLS) is a very ho opic, which is currenly under sandardizaion by IETF and ITU. GMPLS is he nex sep of MPLS; i provides a generalized signaling conrol proocol sandard for he muliple ypes of swiching. I is our expecaion ha GMPLS is going o shape a new conrol plane for he fuure IP-neworks and o simplify he conrol funcions supporing muliple ypes of swiching. In paricular, he so-called GMPLS-oriened Label Swiching Rouer (LSR) archiecure is concreed for beer performance, and impacs many aspecs of fuure IP-neworks. This Feaure Topic of IEEE Communicaions Magazine seeks o presen a series of sae-of-he-ar aricles on GMPLS-relaed opics. In paricular, we are ineresed in uorial and survey aricles on, bu no limied o, he following opics: GMPLS rchiecure GMPLS-oriened Label Swiching Rouer (LSR) Sysem GMPLS-oriened os GMPLS-oriened Link Managemen GMPLS-oriened OM GMPLS-oriened Mobile IP-Neworks GMPLS-oriened Wireless Handoff GMPLS-oriened ll-opical IP-Neworks GMPLS-oriened Scalabiliy GMPLS-oriened New Issues Schedule: Submission eadline: November 1, 2002 ccepance Noificaion: January 15, 2003 Final Manuscrip ue: March 31, 2003 Publicaion ae: June 1, 2003 Submission: Please submi your complee paper in a.doc or.pdf file o our Edior-in-Chief, [email protected] for paper review. IEEE Communicaions Magazine ugus