M68HC08. Microcontrollers MC68HC908LJ24 MC68HC908LK24. nc... Freescale Semiconductor, I. Data Sheet. Freescale Semiconductor, Inc.

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1 nc. M68HC08 Microcontrollers MC68HC908LJ24 MC68HC908LK24 Data Sheet MC68HC908LJ24/D Rev. 2 8/2003 MOTOROLA.COM/SEMICONDUCTORS

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3 nc. MC68HC908LJ24 MC68HC908LK24 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. This product incorporates SuperFlash technology licensed from SST. Motorola, Inc., 2003 MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA 3

4 nc. Revision History Revision History Date Revision Level Description Page Number(s) 8/ First general release. Data Sheet MC68HC908LJ24/LK24 Rev. 2 4 MOTOROLA

5 nc. Data Sheet MC68HC908LJ24 List of Sections Section 1. General Description Section 2. Memory Map Section 3. Random-Access Memory (RAM) Section 4. FLASH Memory (FLASH) Section 5. Configuration Registers (CONFIG) Section 6. Central Processor Unit (CPU) Section 7. Oscillator (OSC) Section 8. Clock Generator Module (CGM) Section 9. System Integration Module (SIM) Section 10. Monitor ROM (MON) Section 11. Timer Interface Module (TIM) Section 12. Real Time Clock (RTC) Section 13. Infrared Serial Communications Interface Module (IRSCI) Section 14. Serial Peripheral Interface Module (SPI)..287 Section 15. Multi-Master IIC Interface (MMIIC) Section 16. Analog-to-Digital Converter (ADC) Section 17. Liquid Crystal Display (LCD) Driver Section 18. Input/Output (I/O) Ports Section 19. External Interrupt (IRQ) MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA List of Sections 5

6 nc. List of Sections Section 20. Keyboard Interrupt Module (KBI) Section 21. Computer Operating Properly (COP) Section 22. Low-Voltage Inhibit (LVI) Section 23. Break Module (BRK) Section 24. Electrical Specifications Section 25. Mechanical Specifications Section 26. Ordering Information Appendix A. MC68HC908LK Data Sheet MC68HC908LJ24/LK24 Rev. 2 6 List of Sections MOTOROLA

7 nc. Data Sheet MC68HC908LJ24 Table of Contents Section 1. General Description 1.1 Contents Introduction Features MCU Block Diagram Pin Assignments Pin Functions Power Supply Pins (V DD and V SS ) Analog Power Supply Pin (V DDA ) LCD Bias Voltage (V LCD ) Oscillator Pins (OSC1 and OSC2) External Reset Pin (RST) External Interrupt Pin (IRQ) External Filter Capacitor Pin (CGMXFC) ADC Voltage High Reference Pin (V REFH ) ADC Voltage Low Reference Pin (V REFL ) Port A Input/Output (I/O) Pins (PTA7 PTA0) Port B I/O Pins (PTB7 PTB0) Port C I/O Pins (PTC7 PTC0) Port D I/O Pins (PTD7 PTD0) Port E I/O Pins (PTE7 PTE0) Port F I/O Pins (PTF7 PTF0) LCD Backplane and Frontplane (BP0-BP2, BP3/FP0, FP1 FP10, FP27 FP32) MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA Table of Contents 7

8 nc. Table of Contents Section 2. Memory Map 2.1 Contents Introduction Unimplemented Memory Locations Reserved Memory Locations Input/Output (I/O) Section Section 3. Random-Access Memory (RAM) 3.1 Contents Introduction Functional Description Section 4. FLASH Memory (FLASH) 4.1 Contents Introduction Functional Description FLASH Control Register FLASH Page Erase Operation FLASH Mass Erase Operation FLASH Program Operation FLASH Block Protection FLASH Block Protect Register Section 5. Configuration Registers (CONFIG) 5.1 Contents Introduction Functional Description Configuration Register 1 (CONFIG1) Configuration Register 2 (CONFIG2) Data Sheet MC68HC908LJ24/LK24 Rev. 2 8 Table of Contents MOTOROLA

9 nc. Table of Contents Section 6. Central Processor Unit (CPU) 6.1 Contents Introduction Features CPU Registers Accumulator Index Register Stack Pointer Program Counter Condition Code Register Arithmetic/Logic Unit (ALU) Low-Power Modes Wait Mode Stop Mode CPU During Break Interrupts Instruction Set Summary Opcode Map Section 7. Oscillator (OSC) 7.1 Contents Introduction Internal Oscillator X-tal Oscillator I/O Signals Crystal Amplifier Input Pin (OSC1) Crystal Amplifier Output Pin (OSC2) Oscillator Enable Signal (SIMOSCEN) Internal RC Clock (ICLK) CGM Oscillator Clock (CGMXCLK) CGM Reference Clock (CGMRCLK) MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA Table of Contents 9

10 nc. Table of Contents 7.6 Low Power Modes Wait Mode Stop Mode Oscillator During Break Mode Section 8. Clock Generator Module (CGM) 8.1 Contents Introduction Features Functional Description Oscillator Module Phase-Locked Loop Circuit (PLL) PLL Circuits Acquisition and Tracking Modes Manual and Automatic PLL Bandwidth Modes Programming the PLL Special Programming Exceptions Base Clock Selector Circuit CGM External Connections I/O Signals External Filter Capacitor Pin (CGMXFC) PLL Analog Power Pin (V DDA ) PLL Analog Ground Pin (V SSA ) Oscillator Output Frequency Signal (CGMXCLK) CGM Reference Clock (CGMRCLK) CGM VCO Clock Output (CGMVCLK) CGM Base Clock Output (CGMOUT) CGM CPU Interrupt (CGMINT) CGM Registers PLL Control Register PLL Bandwidth Control Register PLL Multiplier Select Registers PLL VCO Range Select Register PLL Reference Divider Select Register Data Sheet MC68HC908LJ24/LK24 Rev Table of Contents MOTOROLA

11 nc. Table of Contents 8.7 Interrupts Special Modes Wait Mode Stop Mode CGM During Break Interrupts Acquisition/Lock Time Specifications Acquisition/Lock Time Definitions Parametric Influences on Reaction Time Choosing a Filter Section 9. System Integration Module (SIM) 9.1 Contents Introduction SIM Bus Clock Control and Generation Bus Timing Clock Start-up from POR or LVI Reset Clocks in Stop Mode and Wait Mode Reset and System Initialization External Pin Reset Active Resets from Internal Sources Power-On Reset Computer Operating Properly (COP) Reset Illegal Opcode Reset Illegal Address Reset Low-Voltage Inhibit (LVI) Reset Monitor Mode Entry Module Reset (MODRST) SIM Counter SIM Counter During Power-On Reset SIM Counter During Stop Mode Recovery SIM Counter and Reset States Exception Control Interrupts Hardware Interrupts SWI Instruction MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA Table of Contents 11

12 nc. Table of Contents Interrupt Status Registers Interrupt Status Register Interrupt Status Register Interrupt Status Register Reset Break Interrupts Status Flag Protection in Break Mode Low-Power Modes Wait Mode Stop Mode SIM Registers SIM Break Status Register SIM Reset Status Register SIM Break Flag Control Register Section 10. Monitor ROM (MON) 10.1 Contents Introduction Features Functional Description Entering Monitor Mode Data Format Break Signal Baud Rate Commands Security ROM-Resident Routines PRGRNGE ERARNGE LDRNGE MON_PRGRNGE MON_ERARNGE MON_LDRNGE EE_WRITE EE_READ Data Sheet MC68HC908LJ24/LK24 Rev Table of Contents MOTOROLA

13 nc. Table of Contents Section 11. Timer Interface Module (TIM) 11.1 Contents Introduction Features Pin Name Conventions Functional Description TIM Counter Prescaler Input Capture Output Compare Unbuffered Output Compare Buffered Output Compare Pulse Width Modulation (PWM) Unbuffered PWM Signal Generation Buffered PWM Signal Generation PWM Initialization Interrupts Low-Power Modes Wait Mode Stop Mode TIM During Break Interrupts I/O Signals TIM Clock Pins (PTD4/KBI4/T1CLK, PTD5/KBI5/T2CLK) TIM Channel I/O Pins (PTB2/T1CH0, PTB3/T1CH1, PTB4/T2CH0, PTB5/T2CH1) I/O Registers TIM Status and Control Register TIM Counter Registers TIM Counter Modulo Registers TIM Channel Status and Control Registers TIM Channel Registers MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA Table of Contents 13

14 nc. Table of Contents Section 12. Real Time Clock (RTC) 12.1 Contents Introduction Features I/O Pins Functional Description Time Functions Calendar Functions Alarm Functions Chronograph Functions Timebase Interrupts RTC Interrupts RTC Clock Calibration and Compensation Calibration Error RTC Register and Bit Write Protection Low-Power Modes Wait Mode Stop Mode RTC Registers RTC Calibration Control Register (RTCCOMR) RTC Calibration Data Register (RTCCDAT) RTC Control Register 1 (RTCCR1) RTC Control Register 2 (RTCCR2) RTC Status Register (RTCSR) Alarm Minute and Hour Registers (ALMR and ALHR) Second Register (SECR) Minute Register (MINR) Hour Register (HRR) Day Register (DAYR) Month Register (MTHR) Year Register (YRR) Day-Of-Week Register (DOWR) Chronograph Data Register (CHRR) Data Sheet MC68HC908LJ24/LK24 Rev Table of Contents MOTOROLA

15 nc. Table of Contents Section 13. Infrared Serial Communications Interface Module (IRSCI) 13.1 Contents Introduction Features Pin Name Conventions IRSCI Module Overview Infrared Functional Description Infrared Transmit Encoder Infrared Receive Decoder SCI Functional Description Data Format Transmitter Character Length Character Transmission Break Characters Idle Characters Transmitter Interrupts Receiver Character Length Character Reception Data Sampling Framing Errors Baud Rate Tolerance Receiver Wakeup Receiver Interrupts Error Interrupts Low-Power Modes Wait Mode Stop Mode SCI During Break Module Interrupts I/O Signals PTB0/TxD (Transmit Data) MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA Table of Contents 15

16 nc. Table of Contents PTB1/RxD (Receive Data) I/O Registers SCI Control Register SCI Control Register SCI Control Register SCI Status Register SCI Status Register 2 (SCS2) SCI Data Register SCI Baud Rate Register SCI Infrared Control Register Section 14. Serial Peripheral Interface Module (SPI) 14.1 Contents Introduction Features Pin Name Conventions and I/O Register Addresses Functional Description Master Mode Slave Mode Transmission Formats Clock Phase and Polarity Controls Transmission Format When CPHA = Transmission Format When CPHA = Transmission Initiation Latency Queuing Transmission Data Error Conditions Overflow Error Mode Fault Error Interrupts Resetting the SPI Low-Power Modes Wait Mode Data Sheet MC68HC908LJ24/LK24 Rev Table of Contents MOTOROLA

17 nc. Table of Contents Stop Mode SPI During Break Interrupts I/O Signals MISO (Master In/Slave Out) MOSI (Master Out/Slave In) SPSCK (Serial Clock) SS (Slave Select) CGND (Clock Ground) I/O Registers SPI Control Register SPI Status and Control Register SPI Data Register Section 15. Multi-Master IIC Interface (MMIIC) 15.1 Contents Introduction Features I/O Pins Multi-Master IIC Registers Multi-Master IIC Address Register (MMADR) Multi-Master IIC Control Register (MMCR) Multi-Master IIC Master Control Register (MIMCR) Multi-Master IIC Status Register (MMSR) Multi-Master IIC Data Transmit Register (MMDTR) Multi-Master IIC Data Receive Register (MMDRR) Programming Considerations Section 16. Analog-to-Digital Converter (ADC) 16.1 Contents Introduction Features MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA Table of Contents 17

18 nc. Table of Contents 16.4 Functional Descriptions ADC Port I/O Pins Voltage Conversion Conversion Time Continuous Conversion Result Justification Monotonicity Interrupts Low-Power Modes Wait Mode Stop Mode I/O Signals ADC Voltage In (V ADIN ) ADC Analog Power Pin (V DDA ) ADC Analog Ground Pin (V SSA ) ADC Voltage Reference High Pin (V REFH ) ADC Voltage Reference Low Pin (V REFL ) I/O Registers ADC Status and Control Register ADC Data Register ADC Clock Control Register Section 17. Liquid Crystal Display (LCD) Driver 17.1 Contents Introduction Features Pin Name Conventions and I/O Register Addresses Functional Description LCD Duty LCD Voltages (V LCD, V LCD1, V LCD2, V LCD3 ) LCD Cycle Frame Fast Charge and Low Current Contrast Control Data Sheet MC68HC908LJ24/LK24 Rev Table of Contents MOTOROLA

19 nc. Table of Contents 17.6 Low-Power Modes Wait Mode Stop Mode I/O Signals BP0 BP3 (Backplane Drivers) FP0 FP32 (Frontplane Drivers) Seven Segment Display Connection I/O Registers LCD Control Register (LCDCR) LCD Clock Register (LCDCLK) LCD Data Registers (LDAT1 LDAT17) Section 18. Input/Output (I/O) Ports 18.1 Contents Introduction Port A Port A Data Register (PTA) Data Direction Register A (DDRA) Port B Port B Data Register (PTB) Data Direction Register B (DDRB) Port B LED Control Register (LEDB) Port C Port C Data Register (PTC) Data Direction Register C (DDRC) Port C LED Control Register (LEDC) Port D Port D Data Register (PTD) Data Direction Register D (DDRD) Port E Port E Data Register (PTE) Data Direction Register E (DDRE) Port E LED Control Register (LEDE) MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA Table of Contents 19

20 nc. Table of Contents 18.8 Port F Port F Data Register (PTF) Data Direction Register F (DDRF) Port F LED Control Register (LEDF) Section 19. External Interrupt (IRQ) 19.1 Contents Introduction Features Functional Description IRQ Pin IRQ Module During Break Interrupts IRQ Status and Control Register (INTSCR) Section 20. Keyboard Interrupt Module (KBI) 20.1 Contents Introduction Features I/O Pins Functional Description Keyboard Initialization Keyboard Interrupt Registers Keyboard Status and Control Register Keyboard Interrupt Enable Register Low-Power Modes Wait Mode Stop Mode Keyboard Module During Break Interrupts Data Sheet MC68HC908LJ24/LK24 Rev Table of Contents MOTOROLA

21 nc. Table of Contents Section 21. Computer Operating Properly (COP) 21.1 Contents Introduction Functional Description I/O Signals ICLK STOP Instruction COPCTL Write Power-On Reset Internal Reset Reset Vector Fetch COPD (COP Disable) COPRS (COP Rate Select) COP Control Register Interrupts Monitor Mode Low-Power Modes Wait Mode Stop Mode COP Module During Break Mode Section 22. Low-Voltage Inhibit (LVI) 22.1 Contents Introduction Features Functional Description Polled LVI Operation Forced Reset Operation Voltage Hysteresis Protection LVI Trip Selection LVI Status Register MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA Table of Contents 21

22 nc. Table of Contents 22.6 Low-Power Modes Wait Mode Stop Mode Section 23. Break Module (BRK) 23.1 Contents Introduction Features Functional Description Flag Protection During Break Interrupts CPU During Break Interrupts TIM1 and TIM2 During Break Interrupts COP During Break Interrupts Low-Power Modes Wait Mode Stop Mode Break Module Registers Break Status and Control Register Break Address Registers SIM Break Status Register SIM Break Flag Control Register Section 24. Electrical Specifications 24.1 Contents Introduction Absolute Maximum Ratings Functional Operating Range Thermal Characteristics V DC Electrical Characteristics V DC Electrical Characteristics V Control Timing Data Sheet MC68HC908LJ24/LK24 Rev Table of Contents MOTOROLA

23 nc. Table of Contents V Control Timing V Oscillator Characteristics V Oscillator Characteristics V ADC Electrical Characteristics V ADC Electrical Characteristics Timer Interface Module Characteristics CGM Electrical Specifications V SPI Characteristics V SPI Characteristics FLASH Memory Characteristics Section 25. Mechanical Specifications 25.1 Contents Introduction Pin Low-Profile Quad Flat Pack (LQFP) Pin Quad Flat Pack (QFP) Pin Low-Profile Quad Flat Pack (LQFP) Pin Quad Flat Pack (QFP) Section 26. Ordering Information 26.1 Contents Introduction MC Order Numbers Appendix A. MC68HC908LK24 A.1 Contents A.2 Introduction MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA Table of Contents 23

24 nc. Table of Contents A.3 Oscillator A.4 Low-Voltage Inhibit A.5 Electrical Specifications A.5.1 5V DC Electrical Characteristics A V DC Electrical Characteristics A.5.3 5V Oscillator Characteristics A V Oscillator Characteristics A.6 MC Order Numbers Data Sheet MC68HC908LJ24/LK24 Rev Table of Contents MOTOROLA

25 nc. Data Sheet MC68HC908LJ24 List of Figures Figure Title Page 1-1 MC68HC908LJ24 Block Diagram Pin QFP and LQFP Pin Assignment pin QFP and LQFP Pin Assignment Power Supply Bypassing Memory Map Control, Status, and Data Registers FLASH I/O Register Summary FLASH Control Register (FLCR) FLASH Programming Flowchart FLASH Block Protect Register (FLBPR) CONFIG Registers Summary Configuration Register 1 (CONFIG1) Configuration Register 2 (CONFIG2) CPU Registers Accumulator (A) Index Register (H:X) Stack Pointer (SP) Program Counter (PC) Condition Code Register (CCR) Oscillator Module Block Diagram CGM Block Diagram CGM I/O Register Summary CGM External Connections PLL Control Register (PCTL) MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA List of Figures 25

26 nc. List of Figures Figure Title Page 8-5 PLL Bandwidth Control Register (PBWCR) PLL Multiplier Select Register High (PMSH) PLL Multiplier Select Register Low (PMSL) PLL VCO Range Select Register (PMRS) PLL Reference Divider Select Register (PMDS) PLL Filter SIM Block Diagram SIM I/O Register Summary CGM Clock Signals External Reset Timing Internal Reset Timing Sources of Internal Reset POR Recovery Interrupt Entry Timing Interrupt Recovery Timing Interrupt Processing Interrupt Recognition Example Interrupt Status Register 1 (INT1) Interrupt Status Register 2 (INT2) Interrupt Status Register 3 (INT3) Wait Mode Entry Timing Wait Recovery from Interrupt or Break Wait Recovery from Internal Reset Stop Mode Entry Timing Stop Mode Recovery from Interrupt or Break SIM Break Status Register (SBSR) SIM Reset Status Register (SRSR) SIM Break Flag Control Register (SBFCR) Monitor Mode Circuit Low-Voltage Monitor Mode Entry Flowchart Monitor Data Format Break Transaction Read Transaction Write Transaction Data Sheet MC68HC908LJ24/LK24 Rev List of Figures MOTOROLA

27 nc. List of Figures Figure Title Page 10-7 Stack Pointer at Monitor Mode Entry Monitor Mode Entry Timing Data Block Format for ROM-Resident Routines EE_WRITE FLASH Memory Usage TIM Block Diagram TIM I/O Register Summary PWM Period and Pulse Width TIM Status and Control Register (TSC) TIM Counter Registers High (TCNTH) TIM Counter Registers Low (TCNTL) TIM Counter Modulo Register High (TMODH) TIM Counter Modulo Register Low (TMODL) TIM Channel 0 Status and Control Register (TSC0) TIM Channel 1 Status and Control Register (TSC1) CHxMAX Latency TIM Channel 0 Register High (TCH0H) TIM Channel 0 Register Low (TCH0L) TIM Channel 1 Register High (TCH1H) TIM Channel 1 Register Low (TCH1L) RTC I/O Register Summary RTC Block Diagram RTC Clock Calibration and Compensation Hz Clock Compensation RTC Write Protect State Diagram RTC Calibration Control Register (RTCCOMR) RTC Calibration Data Register (RTCCDAT) RTC Control Register 1 (RTCCR1) RTC Control Register 2 (RTCCR2) RTC Status Register (RTCSR) Alarm Minute Register (ALMR) Alarm Hour Register (ALHR) Second Register (SECR) Minute Register (MINR) Hour Register (HRR) MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA List of Figures 27

28 nc. List of Figures Figure Title Page Day Register (DAYR) Month Register (MTHR) Year Register (YRR) Day-Of-Week Register (DOWR) Chronograph Data Register (CHRR) IRSCI I/O Registers Summary IRSCI Block Diagram Infrared Sub-Module Diagram Infrared SCI Data Example SCI Module Block Diagram SCI Data Formats SCI Transmitter SCI Receiver Block Diagram Receiver Data Sampling Slow Data Fast Data SCI Control Register 1 (SCC1) SCI Control Register 2 (SCC2) SCI Control Register 3 (SCC3) SCI Status Register 1 (SCS1) Flag Clearing Sequence SCI Status Register 2 (SCS2) SCI Data Register (SCDR) SCI Baud Rate Register (SCBR) SCI Infrared Control Register (SCIRCR) SPI I/O Register Summary SPI Module Block Diagram Full-Duplex Master-Slave Connections Transmission Format (CPHA = 0) CPHA/SS Timing Transmission Format (CPHA = 1) Transmission Start Delay (Master) SPRF/SPTE CPU Interrupt Timing Missed Read of Overflow Condition Data Sheet MC68HC908LJ24/LK24 Rev List of Figures MOTOROLA

29 nc. List of Figures Figure Title Page Clearing SPRF When OVRF Interrupt Is Not Enabled SPI Interrupt Request Generation CPHA/SS Timing SPI Control Register (SPCR) SPI Status and Control Register (SPSCR) SPI Data Register (SPDR) MMIIC I/O Register Summary Multi-Master IIC Address Register (MMADR) Multi-Master IIC Control Register (MMCR) Multi-Master IIC Master Control Register (MIMCR) Multi-Master IIC Status Register (MMSR) Multi-Master IIC Data Transmit Register (MMDTR) Multi-Master IIC Data Receive Register (MMDRR) Data Transfer Sequences for Master/Slave Transmit/Receive Modes ADC I/O Register Summary ADC Block Diagram Bit Truncation Mode Error ADC Status and Control Register (ADSCR) ADRH and ADRL in 8-Bit Truncated Mode ADRH and ADRL in Right Justified Mode ADRH and ADRL in Left Justified Mode ADRH and ADRL in Left Justified Sign Data Mode ADC Clock Control Register (ADCLK) LCD I/O Register Summary LCD Block Diagram Simplified LCD Schematic (1/3 Duty, 1/3 Bias) Fast Charge Timing Static LCD Backplane Driver Waveform /3 Duty LCD Backplane Driver Waveforms /4 Duty LCD Backplane Driver Waveforms Static LCD Frontplane Driver Waveforms /3 Duty LCD Frontplane Driver Waveforms /4 Duty LCD Frontplane Driver Waveforms MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA List of Figures 29

30 nc. List of Figures Figure Title Page /4 Duty LCD Frontplane Driver Waveforms (continued) Segment Display Example BP0 BP2 and FP0 FP2 Output Waveforms for 7-Segment Display Example "f" Segment Voltage Waveform "e" Segment Voltage Waveform LCD Control Register (LCDCR) LCD Clock Register (LCDCLK) LCD Data Registers 1 17 (LDAT1 LDAT17) I/O Port Register Summary Port A Data Register (PTA) Data Direction Register A (DDRA) Port A I/O Circuit Port B Data Register (PTB) Data Direction Register B (DDRB) Port B I/O Circuit Port B LED Control Register (LEDB) Port C Data Register (PTC) Data Direction Register C (DDRC) Port C I/O Circuit Port C LED Control Register (LEDC) Port D Data Register (PTD) Data Direction Register D (DDRD) Port D I/O Circuit Port E Data Register (PTE) Data Direction Register E (DDRE) Port E I/O Circuit Port E LED Control Register (LEDE) Port F Data Register (PTF) Data Direction Register F (DDRF) Port F I/O Circuit Port F LED Control Register (LEDF) IRQ Module Block Diagram IRQ I/O Port Register Summary Data Sheet MC68HC908LJ24/LK24 Rev List of Figures MOTOROLA

31 nc. List of Figures Figure Title Page 19-3 IRQ Status and Control Register (INTSCR) KBI I/O Register Summary Keyboard Interrupt Block Diagram Keyboard Status and Control Register (KBSCR) Keyboard Interrupt Enable Register (KBIER) COP Block Diagram Configuration Register 1 (CONFIG1) COP Control Register (COPCTL) LVI I/O Register Summary LVI Module Block Diagram Break Module Block Diagram Break Module I/O Register Summary Break Status and Control Register (BRKSCR) Break Address Register High (BRKH) Break Address Register Low (BRKL) SIM Break Status Register (SBSR) SIM Break Flag Control Register (SBFCR) Typical Internal Oscillator Frequency SPI Master Timing SPI Slave Timing Pin Low-Profile Quad Flat Pack (Case No. 840F) Pin Quad Flat Pack (Case No. 840B) Pin Low-Profile Quad Flat Pack (Case No. 917) Pin Quad Flat Pack (Case No. 841B) A-1 MC68HC908LK24 Crystal Oscillator Connection A-2 MC68HC908LK24 Configuration Register 1 (CONFIG1) MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA List of Figures 31

32 nc. List of Figures Data Sheet MC68HC908LJ24/LK24 Rev List of Figures MOTOROLA

33 nc. Data Sheet MC68HC908LJ24 List of Tables Table Title Page 2-1 Vector Addresses FLASH Block Protect Register to Physical Address LVI Trip Point Selection Instruction Set Summary Opcode Map Numeric Examples VPR1 and VPR0 Programming PRE 1 and PRE0 Programming Signal Name Conventions PIN Bit Set Timing Vector Addresses Monitor Mode Signal Requirements and Options Mode Differences (Vectors) Monitor Baud Rate Selection READ (Read Memory) Command WRITE (Write Memory) Command IREAD (Indexed Read) Command IWRITE (Indexed Write) Command READSP (Read Stack Pointer) Command RUN (Run User Program) Command Summary of ROM-Resident Routines PRGRNGE Routine ERARNGE Routine LDRNGE Routine MC68HC908LJ24/LK24 Rev. 2 Data Sheet MOTOROLA List of Tables 33