CompactPCI SYSTEM SLOT SBC WITH PENTIUM PROCESSOR

Transcription

1 CompactPCI SYSTEM SLOT SBC WITH PENTIUM PROCESSOR The IPM6 is a highly integrated robust CompactPCI System Slot Controller. The design integrates on the front panel a VGA-, an Ethernet- and one or two USB connectors. All needed standard PC interfaces are available on an easy to use standard 1.27mm flat ribbon cable connector offering the ability for a one to one connection to standard IDC type DSUB connectors. The disk drives can be connected at the standard connectors on the PCB top side. The IPM6 is 100% PC/AT compatible. Fully bootable FLASH disks are supported for projects where hard disks or floppy cannot be used. The IPM6 is designed for 3.3V and 5V CompactPCI Systems with 33MHz clock and a 32 bit address/data bus. It is compatible with PICMG2.0 Rev.3.0. All these features make the IPM6 to the ideal solution for the industry where a flexible, rugged and long term available complete CompactPCI System Slot CPU is needed. Features Low power Pentium MMX processor Processor speed 166 / 266 MHz Up to 128 MB SDRAM Flash BIOS ROM Real Time Clock and setup with battery backup CompactPCI 32Bit/33MHz Interface compatible with PICMG2.0 Rev. 3.0 Hot Swap support for CompactPCI peripheral boards Integrated SXGA controller (CRT and panel support) Integrated 10/100 Mbit/s Ethernet controller Serial EEPROM for configuration data E-IDE port & FDD port Mouse-/ keyboard ports Up to two USB ports Two RS232 ports & one parallel port Two serial ports for optional RS85, IrDA,... CPU temperature sensor Programmable watchdog Low power 512 kbyte pipelined burst 2 nd level cache 2001 by MPL AG 1 MEH Rev. A

2 TABLE OF CONTENTS 1. INTRODUCTION ABOUT THIS MANUAL SAFETY PRECAUTIONS AND HANDLING ELECTROSTATIC DISCHARGE (ESD) PROTECTION EQUIPMENT SAFETY GENERAL INFORMATION AND SPECIFICATIONS ELECTRICAL SPECIFICATIONS CompactPCI Interface Processor Chipset BIOS ROM Memory RTC VGA USB Serial RS232 Ports Parallel Port E-IDE Ports Floppy Disk Ethernet Keyboard / Mouse Speaker Temperature Sensor Watchdog Indicators Software Power Supply ENVIRONMENT Temperature Range Relative Humidity DIMENSIONS Print Front Panel RELATED DOCUMENTS HARDWARE PARTS LOCATION SWITCH SETTINGS DIP Switch 1 Peripheral Settings DIP Switch 2 Display And Battery Settings USB Port 1 Switch EXTERNAL CONNECTORS /100BaseT/TX Connector USB Connector VGA CRT Connector CompactPCI Connector INTERNAL CONNECTORS High Density Connector E-IDE Connector Standard FDD Connector Speaker Connector CABLE REQUIREMENTS by MPL AG 2 MEH Rev. A

3 3.6 MODULE SOCKETS The Memory Module REMMI-Family Module Socket SOFTWARE BIOS BIOS Update BIOS Release Index DEVICE DRIVERS Links To The Latest Driver OPERATION BLOCK DIAGRAM PC/AT FUNCTIONALITY STATUS INDICATORS TEMPERATURE SENSOR PROGRAMMABLE HARDWARE WATCHDOG Programming The Watchdog BATTERY CIRCUIT BACK PANEL INPUT OUTPUT EXTENSION REGISTERS Watchdog Control ($800) Serial Interface 1 & 2 Control ($801) Programming Control & User Switch ($802) PCI Control ($803) CPU Clock Control ($80) Board ID & Revision ($805) PLD ID & Revision ($806) Reserved ($807) Video Control (M69000: Register XR71) EMC FEATURES SYSTEM MANAGEMENT BUS Devices on the onboard SMBus Serial EEPROM AT2C Temperature Sensor LM COMPACT PCI FUNCTION Hot Swap and ENUM# INTP, INTS Global Address (GA) System Slot Enable Intelligent Platform Management Bus (IPMB) Push Button Reset JTAG REQ#/GNT# by MPL AG 3 MEH Rev. A

4 1. INTRODUCTION 1.1 ABOUT THIS MANUAL This manual assists the installation and initialization procedure by providing all the information necessary to handle and configure the IPM6. The manual is written for technical personnel responsible for integrating the IPM6 into their system. 1.2 SAFETY PRECAUTIONS AND HANDLING For personal safety and safe operation of the IPM6, follow all safety procedures described here and in other sections of the manual. Power must be removed from the system before installing (or removing) the IPM6 to prevent the possibility of personal injury (electrical shock) and/or damage to the product. The IPM6 is not hot swappable. Handle the product carefully, i.e., dropping or mishandling the IPM6 can cause damage to assemblies and components. Do not expose the equipment to moisture. WARNING There are no user-serviceable components on the IPM6 1.3 ELECTROSTATIC DISCHARGE (ESD) PROTECTION Various electrical components within the product are sensitive to static and electrostatic discharge (ESD). Even a non-sensible static discharge can be sufficient to destroy or degrade a component's operation! Never touch the Components on the IPM6 with your hands. A non-sensible static discharge during the insertion in the CompactPCI rack is prevented with the included ESD discharge strip. 1. EQUIPMENT SAFETY Great care is taken by MPL that all its products are thoroughly and rigorously tested before leaving the factory to ensure that they are fully operational and conform to specification. However, no matter how reliable a product, there is always the remote possibility that a defect may occur. The occurrence of a defect on this device may, under certain conditions, cause a defect to occur in adjoining and/or connected equipment. It is the user s responsibility to ensure that adequate protection for such equipment is incorporated when installing this device. MPL accepts no responsibility whatsoever for such kind of defects, however caused by MPL AG MEH Rev. A

5 2. GENERAL INFORMATION AND SPECIFICATIONS This chapter provides a general overview over the IPM6 and its features. It outlines the electrical and physical specifications of the product and its power requirements. 2.1 ELECTRICAL SPECIFICATIONS CompactPCI Interface System Slot CPU compatible to PICMG2.0 R3.0 Compatible with 32Bit / 33MHz backplane, with optional Back Panel IO Compatible with 6Bit / 33MHz backplane (only 32 bit used but needed pull-ups supported), without Back Panel IO Supports the Push Button Reset on the backplane Compatible with 5V and 3.3V backplane signalling Processor Intel Low Power Embedded Pentium CPU Tillamook MMX TM technology 6-Bit data bus Separated 16 kbyte code and 16 kbyte write back data caches Pipelined Floating Point Unit Enhanced Branch Prediction Algorithm 0.25 Micron Process Technology Selectable clock frequency 166/266 MHz very low power consumption Chipset Intel 30TX 66 MHz host bus speed 512 kb pipelined burst 2 nd level cache (6MB DRAM cachability) 2.1. BIOS ROM 256kB flash EEPROM easy BIOS update Memory Socket for one 1 pin SO-DIMM memory module (3.3V) SDRAM and EDO/FPM DRAM supported Up to 128 Mbytes (1 module) 6-bit data bus RTC Backed with on board battery Year 2000 compliant 2001 by MPL AG 5 MEH Rev. A

6 2.1.7 VGA Chips & Technology Graphics Accelerator 6 bit graphics engine 2 MByte video memory (optional MByte) Resolutions up to 1280x102 Colors up to 16.7M Refresh-rates up to 85 Hz DPMS and DDC support Standard D-sub 15HD VGA connector Chip disable function MPL REMMI-Family module port, flexible panel support for STN and TFT panels, resolutions up to 1280x USB 2 USB 1.0 ports for serial transfers at 12 or 1.5 MBit/s USB keyboard is supported by the BIOS ESD protected Serial RS232 Ports Two serial RS232 ports, each configurable as COM1 and COM2 16C550 compatible (16Byte FIFO) All modem signals are available for each port Optionally the 2 ports can be equipped with RS85, RS22, IrDA or other serial interfaces (over the Back Panel IO) ESD protected Parallel Port Available on a high density 50-pin Hirose connector IEEE128 compliant SPP, EPP1.7, EPP1.9, ECP mode support Configurable as LPT1, LPT2, LPT3 Floppy disk on parallel port mode ESD protected E-IDE Ports pin header(internal), 2 mm pitch, for internal 2,5 notebook hard disks (primary IDE) PIO Mode and Bus Master IDE, transfers up to 1 Mbytes/s Ultra DMA/33 mode, synchronous DMA mode transfers up to 33 Mbytes/s Activity indicator on front panel Floppy Disk Up to 2.88 Mbytes FDD supported Internal standard 3-pin header, 2.5mm (0.1'') Ethernet Intel 82559er 10/100 MBit/s Ethernet controller Full 32-bit PCI bus master 10/100BaseTX (twisted pair) interface (RJ5 connector) performs all of the IEEE protocol functions Chip disable function Activity indicator for network traffic and 100 Mbit/s operation on RJ5 Device drivers for all major operation systems available ESD protected 2001 by MPL AG 6 MEH Rev. A

7 2.1.1 Keyboard / Mouse Available on high density 50-pin Hirose connector ESD protected Speaker Available on a -pin header Temperature Sensor Supervises the CPU / PCB temperature CPU clock throttling if overtemperature (thermal throttling) possible Programmable temperature threshold Watchdog Simply programmable watchdog Timeout between 250ms and 32s Indicators Power ok LED (green) Reset / CPU Stop LED (red) HDD activity LED (yellow) LAN connection LED (green, on RJ5) LAN activity LED (green flashing, on RJ5) LAN100 LED (yellow, on RJ5) Software The IPM6 is running with the well known and widely used Award BIOS Any operating system for a PC/AT can be run on the IPM Power Supply High efficiency 1 channel switching regulator Linear regulator for the IO voltage over the host bus ESD protected Power consumption: +/-12V: not required 5V: 266 MHz (operating with 128 MB SDRAM) (typ. 1.25W) 3.3V: 266 MHz (operating with 128 MB SDRAM) (typ. 8.25W) 2.2 ENVIRONMENT Temperature Range 0 C to +60 C (+32 F to +10 F). extended temperature range available Relative Humidity 10%... 90% non condensing 2001 by MPL AG 7 MEH Rev. A

8 2.3 DIMENSIONS Print 169,50 160,00 100,00 1 O N O 2 N Figure 1: Top View Length: 160 mm (6,86 ) Width: 100 mm (,12 ) Weight: 230g (with front panel and SDRAM module) Front Panel 20,32 PowOK HD Reset CompactPCI 128,70 Figure 2: Front View Aluminum front panel with EMC-lips and ESD contacts Thickness: 2.5mm Length: 128.7mm Height: mm (1,57 ) (standard version TE, single slot) 2001 by MPL AG 8 MEH Rev. A

9 2. RELATED DOCUMENTS The high integration level of equipped components offers a lot more features than could possibly be described within the scope of this manual. Several data books related to all the different components are available either directly from the respective manufacturer or distributor or by downloading from the manufacturers Internet site. However, in most cases these documents are not needed when integrating the IPM6 as a standard PC with an operating system running in a PC-environment. Integrators who want to go beyond these standard capabilities are encouraged to contact their local distributor or mailto:[email protected] by MPL AG 9 MEH Rev. A

10 N IPM6 3. HARDWARE 3.1 PARTS LOCATION 1 Pin SO-DIMM Memory Socket REMMI-T Module Connector USB Port 1 Switch Pentium I Debug Port LEDs DIP Switch 2 1 O CompactPCI Connector J2 VGA Connector USB Port 2 Connector (optional also Port1) 10/100BaseTX Connector 1 O 2 N CompactPCI Connector J1 High Density Connector Speaker Connector DIP Switch 1 Standard FDD Connector IDE Connector Figure 3: Parts Location 3.2 SWITCH SETTINGS Default switch settings are in brackets. 1 O N DIP Switch 1 Peripheral Settings Switch SW1 SW1-1 Must be (ON) Only for Factory use! Meaning SW1-2 SW1-3 SW1- SW1-5 SW1-6 SW1-7 SW1-8 (OFF) ON (OFF) ON (OFF) ON (OFF) ON (OFF) ON (OFF) ON (OFF) ON User configuration switch0 readable through extension register (refer to chapter 5.8.3) User configuration switch1 readable through extension register (refer to chapter 5.8.3) User configuration switch2 readable through extension register (refer to chapter 5.8.3) Onboard RS232 driver channel 1 disabled, BPIO enabled Onboard RS232 driver channel 1 enabled, BPIO disabled Onboard RS232 driver channel 2 disabled, BPIO enabled Onboard RS232 driver channel 2 enabled, BPIO disabled CPU works with 266MHz CPU works with 166MHz Onboard Network Controller enabled Onboard Network Controller disabled Table 1: DIP Switch by MPL AG 10 MEH Rev. A

11 3.2.2 DIP Switch 2 Display And Battery Settings SW2-1 SW2-2 SW2-3 SW2- SW Switch SW2 Meaning (OFF) Battery backup off ON Battery backup on (OFF) Onboard VGA controller enabled ON Onboard VGA controller disabled (OFF) User configuration switch3 readable through VGA controller ON (refer to chapter 5.8.9) (OFF) Video Mode set to CRT (readable through VGA controller, refer to chapter 5.8.9) ON Video Mode set to Panel Bit 5 Bit 6 Bit 7 Bit 8 Panel type (readable through VGA controller, refer to chapter 5.8.9) ON ON ON ON 2bit TFT color panel, 60 x80 OFF ON ON ON 2bit TFT color panel, 800 x 600 ON OFF ON ON 2bit TFT color panel, 102 x 768 OFF OFF ON ON 2bit TFT color panel, 1280 x 102 ON ON OFF ON Reserved OFF ON OFF ON Reserved ON OFF OFF ON Reserved OFF OFF OFF ON Reserved ON ON ON OFF Reserved OFF ON ON OFF Reserved ON OFF ON OFF Reserved OFF OFF ON OFF Reserved ON ON OFF OFF Reserved OFF ON OFF OFF Reserved ON OFF OFF OFF Reserved (OFF) (OFF) (OFF) (OFF) Reserved Table 2: DIP Switch USB Port 1 Switch The USB port 1 switch determines whether the USB Port 1 Signals are switched to the external USB port 1 connector or to the internal REMMI-Family module connector. Figure : USB Port 1 Signals Are Switched To USB Port 1 Connector Figure 5: USB Port 1 Signals Are Switched To REMMI-T Module Connector 2001 by MPL AG 11 MEH Rev. A

12 3.3 EXTERNAL CONNECTORS /100BaseT/TX Connector Standard RJ5 connector for a 100 Ohm cable. Pin number Signal Description Pin out 1 TX+ Transmit data + 2 TX- Transmit data RX+ Receive data + NC Not connected 5 NC Not connected 6 RX- Receive data - 7 NC Not connected 8 NC Not connected RJ5 Table 3: 10/100BaseT/TX Connector USB Connector Standard Type A USB connector pin out. Pin number Signal Description Pin out 1 VCC Cable Power +5V 2 -Data Balanced Data Line - 3 +Data Balanced Data Line + GND Cable Ground USB Type A Table : USB Connector VGA CRT Connector Standard DB15-HD pin out (female). Pin number Signal Description Pin out 1 Red 2 Green 3 Blue Not connected 5 5 Ground 6 Analog Ground 7 Analog Ground 10 8 Analog Ground 9 +5V Ground 11 Not connected HDSUB15 12 DDC data 13 Horizontal synchronization 1 Vertical synchronization 15 DDC clock Table 5: VGA CRT Connector 2001 by MPL AG 12 MEH Rev. A

13 3.3. CompactPCI Connector There are used two 2mm five row 110 pin connector (female) with one row shield. For the description of the signals refer to the CompactPCI Specification PICMG 2.0 R3.0 and/or to the PCI Local Bus Specification Rev PIN F E D C B A Pin out 25 GND 5V 3.3V ENUM# REQ6# 5V 2 GND ACK6# AD[0] V(I/O) 5V AD[1] 23 GND AD[2] 5V AD[3] AD[] 3.3V 22 GND AD[5] AD[6] 3.3V GND AD[7] 21 GND C/BE[0]# M66EN AD[8] AD[9] 3.3V 20 GND AD[10] AD[11] V(I/O) GND AD[12] 19 GND AD[13] GND AD[1] AD[15] 3.3V 18 GND C/BE[1]# PAR 3.3V GND SERR# 17 GND PERR# GND IPMB_SDA IPMB_SCL 3.3V 16 GND LOCK# STOP# V(I/O) GND DEVSEL# 15 GND TRDY# GND IRDY# FRAME# 3.3V 1 GND 13 GND 12 GND KEY AREA 11 GND C/BE[2]# GND AD[16] AD[17] AD[18] 10 GND AD[19] AD[20] 3.3V GND AD[21] 9 GND AD[22] GND AD[23] GND C/BE[3]# 8 GND AD[2] AD[25] V(I/O) GND AD[26] 7 GND AD[27] GND AD[28] AD[29] AD[30] 6 GND AD[31] CLK0 3.3V GND REQ0# 5 GND GNT0# GND RST# NC NC GND INTS INTP V(I/O) HEALTHY# IPMB_PWR 3 GND INTD# 5V INTC# INTB# INTA# 2 GND TDI TDO TMS 5V TCK 1 GND 5V +12V TRST# -12V 5V Table 6: System Slot Connector J1 25F 1F 25E 1E 1A 25A CompactPCI J1 Connector 2001 by MPL AG 13 MEH Rev. A

14 PIN F E D C B A Pin out 22 GND NC NC NC NC NC 21 GND RSV/3.3V RSV/3.3V RSV/3.3V GND CLK6 20 GND RSV/3.3V GND RSV/5V GND CLK5 19 GND RSV/5V RSV/5V RSV/5V GND GND 18 GND NC GND NC NC NC 17 GND GNT6# REQ6# PRST# GND NC 16 GND NC GND DEG# NC NC 15 GND GNT5# REQ5# FAL# GND NC 1 GND AD[32] GND AD[33] AD[3] AD[35] 13 GND AD[36] AD[37] V(I/O) GND AD[38] 12 GND AD[39] GND AD[0] AD[1] AD[2] 11 GND AD[3] AD[] V(I/O) GND AD[5] 10 GND AD[6] GND AD[7] AD[8] AD[9] 9 GND AD[50] AD[51] V(I/O) GND AD[52] 8 GND AD[53] GND AD[5] AD[55] AD[56] 7 GND AD[57] AD[58] V(I/O) GND AD[59] 6 GND AD[60] GND AD[61] AD[62] AD[63] 5 GND PAR6 C/BE[]# V(I/O) NC C/BE[5]# GND C/BE[6]# GND C/BE[7]# NC V(I/O) 3 GND GNT# REQ# GNT3# GND CLK 2 GND REQ3# GNT2# SYSEN# CLK3 CLK2 1 GND REQ2# GNT1# REQ1# GND CLK1 25F 1F 25E 1E 1A 25A CompactPCI J2 Connector Table 7: System Slot Connector J2 With 6 Bit Bus (Without Back Panel IO) PIN F E D C B A Pin out 22 GND NC NC NC NC NC 21 GND 3.3V 3.3V 3.3V GND CLK6 20 GND 3.3V GND 5V GND CLK5 19 GND 5V 5V 5V GND GND 18 GND NC GND NC NC NC 17 GND GNT6# REQ6# PRST# GND NC 16 GND NC GND DEG# NC NC 15 GND GNT5# REQ5# FAL# GND NC 1 GND Pull-up GND Pull-up Pull-up Pull-up 13 GND Pull-up Pull-up V(I/O) GND Pull-up 12 GND Pull-up GND Pull-up Pull-up Pull-up 11 GND Pull-up Pull-up V(I/O) GND EXTMOD1 10 GND EXTMOD2 GND TXD1 RXD1 DSR1# 9 GND RTS1# CTS1# V(I/O) GND DTR1# 8 GND RI1# GND DCD1# TXD2 RXD2 7 GND DSR2# RTS2# V(I/O) GND CTS2# 6 GND DTR2# GND RI2# DCD2# IRRX 5 GND FDMOD IRTX V(I/O) NC IRM/IRR GND Pull-up GND Pull-up NC V(I/O) 3 GND GNT# REQ# GNT3# GND CLK 2 GND REQ3# GNT2# SYSEN# CLK3 CLK2 1 GND REQ2# GNT1# REQ1# GND CLK1 25F 1F 25E 1E 1A 25A CompactPCI J2 Connector Table 8: System Slot Connector J2 With Back Panel IO (Only 32 Bit Bus System) 2001 by MPL AG 1 MEH Rev. A

15 All Back Panel IO Signals are TTL-Level compatible. Pin Signal Name Signal Description 5A IRM/IRR Infrared mode select 5D IRTX Infrared transmit data 5E INTMOD Mode Signal from the PLD to the back panel board (see also 5.8.2) 6A IRRX Infrared receive data 6B DCD2# Data carrier detect channel 2 6C RI2# Ring indicator channel 2 6E DTR2# Data terminal ready channel 2 7A CTS2# Clear to send channel 2 7D RTS2# Request to send channel 2 7E DSR2# Data set ready channel 2 8A RXD2 Receive data channel 2 8B TXD2 Transmit data channel 2 8C DCD1# Data carrier detect channel 2 8E RI1# Ring indicator channel 1 9A DTR1# Data terminal ready channel 1 9D CTS1# Clear to send channel 1 9E RTS1# Request to send channel 1 10A DSR1# Data set ready channel 1 10B RXD1 Receive data channel 1 10C TXD1 Transmit data channel 1 10E EXTMOD1 Mode Signal 1 from the Back Panel board to the PLD (see also 5.8.2) 11A EXTMOD0 Mode Signal 0 from the Back Panel board to the PLD (see also 5.8.2) Pull-up These pins have pull-ups to V(I/O) Table 9: Back Panel IO Signals On CompactPCI J2 Connector 2001 by MPL AG 15 MEH Rev. A

16 3. INTERNAL CONNECTORS 3..1 High Density Connector On this Hirose high density 50 pin connector all standard PC Interfaces are available. There are 2 serial ports, 1 parallel port, mouse and keyboard signals. The second serial port is for non modem use. The Hirose connector is designed for a one by one connection of standard flat ribbon DB9 and DB25 connectors. From MPL AG you can get the IPM86-CAK cable which is made of the Hirose HIF6-50D-1.27R connector (counterpart of the on board Hirose connector) and about 1m flat ribbon cable. On this cable you can press directly the standard DB25 female (parallel port, pin out see below in this chapter) and the standard DB9 male (serial ports, pin out see below in this chapter) flat ribbon cable connectors for the several interfaces. The mouse and keyboard connectors (female) have to be soldered to the cable (pin out see below in this chapter). On the IPM86-CAK cable you can also press two 2.5mm 26 pin flat ribbon cable connector to connect the MIP520-CAK print. This is a print which arrange the connectors for serial, parallel, mouse and keyboard ports in a little space (for further information see the MIP520-CAK manual). Pin Signal Description Pin Signal Description Pin out 1 /STROBE Strobe 26 GND Ground 2 /AUTOFD Autofeed 27 RI1 Ring indicator 3 DATA0 Data bit 0 28 DTR1 Data terminal ready /ERROR Error 29 CTS1 Clear to send 5 DATA1 Data bit 1 30 TXD1 Transmit data 6 /INIT Initialize 31 RTS1 Request to send 7 DATA2 Data bit 2 23 RXD1 Receive data 8 /SELIN Select in 33 DSR1 Data set ready 9 DATA3 Data bit 3 3 DCD1 Data carrier detect 10 GND Ground 35 GND Ground 11 DATA Data bit 36 NC Not connect GND Ground 37 NC Not connect 13 DATA5 Data bit 5 38 CTS2 Clear to send 1 GND Ground 39 TXD2 Transmit data 15 DATA6 Data bit 6 0 RTS2 Request to send GND Ground 1 RXD2 Receive data 50 pin Hirose connector 17 DATA7 Data bit 7 2 NC Not connect 18 GND Ground 3 MS_DAT Mouse data 19 /ACK Acknowledge MS_CLK Mouse Clock 20 GND Ground 5 MS_VCC Mouse Power 21 BUSY Busy 6 GND Ground 22 GND Ground 7 KB_DAT Keyboard data 23 PE Paper empty 8 KB_CLK Keyboard clock 2 GND Ground 9 KB_VCC Keyboard Power 25 SEL Select 50 GND Ground Table 10: High Density Connector 2001 by MPL AG 16 MEH Rev. A

17 In the BIOS under SPECIAL FEATURES SETUP the parallel port can be changed to a FDD port. Then the parallel port signals change to the FDD port signals described below. Pin Signal Description Pin Signal Description Pin out 1 DS0 Drive select 0 1 GND Ground 2 DRVDEN0 Drive density 0 15 MTR0 Motor On 0 3 INDEX Index 16 GND Ground HDSEL Head select 17 MEDIA_ID Media ID 1 5 TRK0 Track0 18 GND Ground 6 DIR Step direction 19 DS1 Drive select WP Write protect 20 GND Ground 8 STEP Step puls 21 MTR1 Motor on 1 9 RDATA Read data 22 GND Ground 10 GND Ground 23 WDATA Write data DSKCHG Disk change 2 GND Ground 50 pin Hirose connector 12 GND Ground 25 WGATE Write gate 13 MEDIA_ID0 Media ID The same like with 50 parallel port Serial port 1 standard DB9 pin out (male). Serial1, Serial2, MS,KB Table 11: High Density Connector With Parallel Port Floppy Pin Signal Description Pin out 1 DCD1 Data carrier detect 2 RXD1 Receive data 3 TXD1 Transmit data 1 5 DTR1 Data terminal ready 5 GND Ground 6 DSR1 Data set ready 7 RTS1 Request to send CTS1 Clear to send DSUB9 9 RI1 Ring indicator Serial port 2 standard DB9 pin out (male). Table 12: Serial Port 1 Connector Pin Signal Description Pin out 1 NC 2 RXD1 Receive data 3 TXD1 Transmit data 1 5 NC 5 GND Ground 6 NC 7 RTS1 Request to send CTS1 Clear to send DSUB9 9 NC Table 13: Serial Port 2 Connector Standard PS/2 mouse and keyboard 6-pin mini-din connector pin out (female). Pin Signal Description Pinout 1 DAT Data 2 NC Not connected GND Ground VCC +5V 3 5 CLK Clock 6 NC Not connected 2 1 Table 1: Mouse And Keyboard Connector MiniDIN by MPL AG 17 MEH Rev. A

18 Parallel Port standard DB25 pin out (female). Pin Signal Description Pin out 1 /STROBE Strobe 2 DATA0 Data bit 0 3 DATA1 Data bit 1 DATA2 Data bit 2 5 DATA3 Data bit 3 6 DATA Data bit 7 DATA5 Data bit 5 8 DATA6 Data bit 6 9 DATA7 Data bit 7 10 /ACK Acknowledge 11 BUSY Busy PE Paper empty 13 SEL Select in 1 /AUTOFD Autofeed /ERROR Error DSUB25 16 /INIT Initialize 17 /SELIN Select 18 GND Ground 19 GND Ground 20 GND Ground 21 GND Ground 22 GND Ground 23 GND Ground 2 GND Ground 25 GND Ground Table 15: Parallel Port Connector Pin out for the standard parallel port DB25 connector with floppy disk drive signals (female). Pin Signal Description Pin out 1 DS0 Drive select 0 2 INDEX Index 3 TRK0 Track0 WP Write protect 5 RDATA Read data 6 DSKCHG Disk change 7 MEDIA_ID0 Media ID 0 8 MTR0 Motor On 0 9 MEDIA_ID1 Media ID 1 10 DS1 Drive select 1 11 MTR1 Motor on WDATA Write data 13 WGATE Drive select 1 1 DRVDEN0 Drive density HDSEL Head select DSUB25 16 DIR Step direction 17 STEP Step puls 18 GND Ground 19 GND Ground 20 GND Ground 21 GND Ground 22 GND Ground 23 GND Ground 2 GND Ground 25 GND Ground Table 16: Parallel Port Connector With FDD Signals 2001 by MPL AG 18 MEH Rev. A

19 3..2 E-IDE Connector There is one E-IDE connector at the IPM6 for a 2.5 notebook HDD ( pin header / 2 mm pitch). The pin header is connected to the primary port. Pin Signal Description Pin Signal Description 1 /RESET Reset 23 IOW I/O write strobe 2 GND Ground 2 GND Ground 3 D7 Data bit 7 25 IOR I/O read strobe D8 Data bit 8 26 GND Ground 5 D6 Data bit 6 27 IORDY I/O ready 6 D9 Data bit 9 28 HDBALE Spindle sync / cable select 7 D5 Data bit 5 29 DACK DMA acknowledge 8 D10 Data bit GND Ground 9 D Data bit 31 IRQ Interrupt request 10 D11 Data bit IOCS16 I/O chipselect16 11 D3 Data bit 3 33 A1 Address 1 12 D12 Data bit 12 3 NC Not connected 13 D2 Data bit 2 35 A0 Address 0 1 D13 Data bit A2 Address 2 15 D1 Data bit 1 37 CS0 Chip Select 0 16 D1 Data bit 1 38 CS1 Chip Select 1 17 D0 Data bit 0 39 ACTLED Activity LED 18 D15 Data bit 15 0 GND Ground 19 GND Ground 1 VCC +5V 20 KEY Key / not connected 2 VCC +5V 21 DRQ DMA request 3 GND Ground 22 GND Ground GND Ground Table 17: Connector For 2.5 HDD, -Pin E-IDE connector Pin Out (2mm) 3..3 Standard FDD Connector Standard 3-pin FDD connector pin-out (2.5mm / 0.1 inch). Pin number Signal Description Pin number Signal Description 1 GND Ground 18 DIR Step direction 2 DRVDEN0 Drive density 0 19 GND Ground 3 GND Ground 20 STEP Step pulse NC Not connected 21 GND Ground 5 GND Ground 22 WDATA Write data 6 DRVDEN1 Drive density 1 23 GND Ground 7 GND Ground 2 WGATE Write gate 8 IDX Index 25 GND Ground 9 GND Ground 26 TR00 Track0 10 MTR0 Motor on 0 27 GND Ground 11 GND Ground 28 WPROT Write protected 12 DS1 Drive select 1 29 MID0 Media ID 0 13 GND Ground 30 RDATA Read data 1 DS0 Drive select 0 31 GND Ground 15 GND Ground 32 HDSEL Head select 16 MTR1 Motor on 1 33 MID1 Media ID 1 17 GND Ground 3 DSKCHG Disk change Table 18: Standard FDD Connector 2001 by MPL AG 19 MEH Rev. A

20 3.. Speaker Connector Pin number Signal Description 1 SPK+ (VCC) Speaker + 2 NC Not connected 3 NC Not connected SPK- Speaker - Table 19: Speaker Connector 3.5 CABLE REQUIREMENTS Shielded cables and I/O cords must be used for this equipment to comply with the CE regulations. Maximum cable length: VGA, keyboard and mouse cable: < 3m 3.6 MODULE SOCKETS The Memory Module A 1-pin SO-DIMM socket with JEDEC standard layout is available for system memory. SO-DIMM memory modules in sizes up to 128 Mbytes can be used. The IPM6 not only supports SDRAM modules with the following specification, but also Fast Page and EDO memory modules. Electrical and mechanical requirements: 3.3V type PC66 compliant JEDEC Standard SO-DIMM 1-Pin layout Maximum k refresh Figure 6: Mounting The Memory Module 2001 by MPL AG 20 MEH Rev. A

21 3.6.2 REMMI-Family Module Socket O 2 N O 2 N Figure 7: Remmi Modul Installation Before you begin with the module (REMMI-T, DLS, DLP) installation, please make sure that no power is applied to the system, and the old TE frontpanel is removed from the IPM6. Installation Steps: 1. Select whether the signals of the USB port 1 are routed to the REMMI-Family module connector or to the optional USB port 1 connector on the front panel using USB port 1 switch (refer to chapter 3.2.3). 2. Select the desired panel type using DIP SW (refer to chapter 3.2.2). 3. Activate the LCD panel mode using DIP SW2- (refer to chapter 3.2.2).. Install the four module socket spacers. 5. Install the board stacker with the short end into the module socket connector. Please, take care that all contact pins of the board stacker are plugged in correctly and that the connector is installed straight. 6. After this the module can be plugged on the mounted board stacker. 7. Now the module has to be fixed with the included four screws on the module socket spacers. Important: All screws must be tightened well since it is the ground connection for the module. 8. Install the two screws on the REMMI-T/DLS/DLP HD-DSUB connector. 9. Now mount the new front panel to the IPM by MPL AG 21 MEH Rev. A

22 . SOFTWARE.1 BIOS.1.1 BIOS Update BIOS upgrading with an additional utility is easily possible. For upgrading, DOS has to be loaded first without any protected mode drivers loaded (e.g., EMM386.EXE). Start the BIOS upgrade utility with the BIOS binary file named as command line parameter: Flasher [filename] After a successful replacement of the BIOS, reboot the system. Caution: If something fails (e.g., loss of power) during BIOS upgrading (specially after erasing the Flash) and the utility is not able to terminate properly, the IPM6 will no longer have a valid BIOS. For these cases, contact MPL to start up the system again..1.2 BIOS Release Index The BIOS release index is shown during boot and appears as follows: MPL IPM6 BIOS V1.0 Note: V1.0 is the BIOS release index (which may have been changed in the meantime)..2 DEVICE DRIVERS Drivers for different operating systems are available..2.1 Links To The Latest Driver The latest driver versions are also available on the internet. INTEL GD82559ER FAST ETHERNET PCI CONTROLLER: CHIPS & TECHNOLOGY GRAPHICS CONTROLLER: INTEL 30TX CHIPSET Note: Links may have been changed in the meantime. The latest links can also be found on the MPL homepage by MPL AG 22 MEH Rev. A

23 2001 by MPL AG 23 MEH Rev. A Figure 8: IPM6 Block Diagram 15-pin HDSUB Connector RJ5 Connector USB Connector 15 REMMI-T Module Socket 50 VG A LCD USB Channel 1 USB Channel 2 CompactPCI Bus PCI2050 PCI/PCI Bridge M69000 Graphics Controller GD82559er Network Controller PCI Bus Low Power Embedded Pentium Processor 166/266 MHz Northbridge MTXC 8239TX Southbridge PIIXE 82371EB Battery Host Bus CompactPCI Connector J1/J2 Memory Bus 512 KB Pipelined Burst Cache Memory Primary IDE 1 Pin SODIMM Memory Socket ISA Bus -pin Flat Cable 2mm Connector 3-pin Flat Cable Connector 256 kb FLASHBIOS Ultra IO FDC37C Serial 1 Serial 2 RS232 Interface RS232 Interface Parallel IEEE128 Keyboard Mouse HD 50-pin Connector 5.1 BLOCK DIAGRAM 5. OPERATION IPM6

24 5.2 PC/AT FUNCTIONALITY The IPM6 operates as a standard PC/AT with all dedicated registers for: Timers Interrupt controller DMA controller Real Time Clock Keyboard controller Parallel, serial ports E-IDE controller FDD controller VGA controller 5.3 STATUS INDICATORS The IPM6 provides five status indicator LED s, giving the user visual response to the actual status. LED Power ok (green LED) Reset (red LED) HDD access (yellow LED) LAN connection / activity (green LED on RJ5) LAN100 activity (yellow LED on RJ5) Table 20: Status LED s Status Power is ok Either Reset is active or CPU stops running IDE device is accessed Light up whenever a connection is detected Flash whenever activity is detected 100 MBit/s link is detected 5. TEMPERATURE SENSOR The Temperature Sensor senses the temperature of the PCB under the CPU. The print temperature is about 5K less than the CPU Package temperature with the mounted heat sink (over the whole allowable temperature range, with and without forced convection). 5.5 PROGRAMMABLE HARDWARE WATCHDOG The IPM6 provides a simply programmable hardware watchdog. The watchdog can be activated and causes a system reset after a programmable timeout between 250ms and s (optionally until 25s) Programming The Watchdog The watchdog is controlled by programming the Watchdog Control register at the address $800 (Refer to chapter 5.8.1). Setting the bit WDOG in the Watchdog Control register, enables the watchdog timer. The watchdog timer starts counting. Rewriting the Watchdog Control register with the WDOG bit set, clears the watchdog timer and restarts counting (feeding the watchdog). If the register has not been written within the specified timeout a system reset will be performed. Clearing the bit WDOG in the Watchdog Control register, disables the watchdog timer. The bits WDGCMP[6..0] set the timeout length. 5.6 BATTERY CIRCUIT An on board battery is provided to guarantee data retention of RTC in power down situations. Battery backup of these two devices is enabled at DIP-switch SW2-1 (Refer to chapter 3.2.2). The battery's capacity of 170mAh should always be sufficient for every application. 5.7 BACK PANEL INPUT OUTPUT The two serial interfaces of the Ultra IO can either be used with the on board RS232 interface or with special interfaces on a Back Panel Input Output (BPIO) Board to make RS85/RS22/IrDA/... interfaces by MPL AG 2 MEH Rev. A

25 If the on board driver are set in shutdown mode with the DIP switches SW1-5 and SW1-6 (refer to chapter 3.2.1), all needed signals are driven to the Back Panel IO on the J2 connector (for pin-out refer to chapter 3.3.). Additionally two signals from the BPIO Card (EXTMOD[1..0]) and one signal from the IPM6 (INTMOD) are available for general purpose use (refer to chapter 5.8.2). 5.8 EXTENSION REGISTERS The extension registers described below are located in the on board EPLD. The EPLD is on the ISA bus in the IO range and is selected with the Peripheral Chip Select 0 (Power Management Device 9, refer to the 82371AB [PIIX] manual from Intel ( The BIOS sets the IO base address of the Chip Select 0 to $ Watchdog Control ($800) WDGCMP6 WDGCMP5 WDGCMP WDGCMP3 WDGCMP2 WDGCMP1 WDGCMP0 WDOG R/W R/W R/W R/W R/W R/W R/W R/W WDGCMP[6..0] (R/W): Watchdog compare This is the value the watchdog counter is compared with. There is the ability to program 127 different timeouts with a resolution of 250ms ( optional 500ms, 1s or 2s). WDOG (R/W): Watchdog enable 0 = Watchdog disabled 1 = Watchdog enabled If WDOG=0, the watchdog timer is disabled. Setting WDOG=1 starts the watchdog timer. Additional writing of the WDOG bit resets the watchdog timer. If the timeout is reached, a system reset is performed Serial Interface 1 & 2 Control ($801) RES RES RES EXTMOD1 EXTMOD0 INTMOD SER2MOD SER1MOD X X 0 X X R R R R R R/W R R SER1MOD, SER2MOD (R): Serial Interface 1 And 2 Mode 0 = RS232 Mode (DIP switch ON) 1 = external Mode (DIP switch OFF) These are the values set with the DIP Switch SW1-[5..6] (Refer to the chapter 3.2.1). If SERxMOD is set to 1, then the respective channel is driven to the BPIO. INTMOD (R/W): General Purpose Output To The Back Panel IO Card 0 = Signal is low 1 = Signal is high This output can be used as general purpose output to the Back Panel IO card. EXTMOD[1..0] (R): General Purpose Inputs From The Back Panel IO Card 0 = Signals are low 1 = Signals are high These inputs can be used as general purpose inputs from the Back Panel IO card by MPL AG 25 MEH Rev. A

26 5.8.3 Programming Control & User Switch ($802) RES RES RES RES USR_SW2 USR_SW1 USR_SW0 TPSEL X X X X R R R R R R R R USR_SW[2..0] (R): User Switch 0 = Switch is ON 1 = Switch is OFF These bits describe the position of the DIP switch SW1-[2..] (Refer to the chapter 3.2.1). Every switch can be used free by the user. TPSEL (R): Testpoint Chip Select 0 = BIOSCS routed to the BIOS flash memory (DIP switch ON) 1 = BIOSCS routed to the Testpoints (DIP switch OFF) This bit indicates the position of the DIP switch SW1-1 (Refer to the chapter 3.2.1). The BIOS Chip Select out of the Southbridge is either routed to the Testpoints on the bottom layer of the PCB or to the on board BIOS flash memory equipped on the IPM6. This DIP Switch must be left ON for normal operation PCI Control ($803) RES RES RES RES RES RES VGADIS NICDIS X X R R R R R R R R NICDIS (R): Network Controller Disable 0 = Disabled (DIP switch ON) 1 = Enabled (DIP switch OFF) This bit reflects the position of DIP switch SW1-8 (Refer to the chapter 3.2.1). This switch is used to control the hardware chip-disable function of the onboard network controller. VGADIS (R): VGA Controller Disable 0 = Disabled (DIP switch ON) 1 = Enabled (DIP switch OFF) This bit reflects the position of DIP switch SW2-2 (Refer to the chapter 3.2.2). This switch is used to control the hardware chip-disable function of the onboard VGA controller CPU Clock Control ($80) RES RES RES RES RES RES RES CPUBF X R R R R R R R R CPUBF2 (R): CPU Clock Frequency 0 = 266MHz (DIP switch ON) 1 = 166MHz (DIP switch OFF) This bit reflects the position of DIP switch SW1-7 (Refer to the chapter 3.2.1). This switch is used to set the CPU clock frequency by MPL AG 26 MEH Rev. A

27 5.8.6 Board ID & Revision ($805) REV3 REV2 REV1 REV0 ID3 ID2 ID1 ID R R R R R R R R ID0..3 (R): Identification Number This register is used to identify the board version (1 = IPM6-1). REV0..3 (R): Revision Number This register is used to identify the board revision (0 = Rev. A) PLD ID & Revision ($806) REV3 REV2 REV1 REV0 ID3 ID2 ID1 ID R R R R R R R R ID0..3 (R): Identification Number This register is used to identify the code version of programmable onboard logic (0 = P00). REV0..3 (R): Revision Number This register is used to identify the code revision of programmable onboard logic (1 = V01) Reserved ($807) RES RES RES RES RES RES RES RES R R R R R R R R This register address is reserved for future use by MPL AG 27 MEH Rev. A

28 5.8.9 Video Control (M69000: Register XR71) The DIP Switch settings for the VGA Controller (DIP Switch SW2-[3..8], refer to chapter 3.2.2) are reflected in the VGA Controller Register XR71. The extension register 71 (XR71) of the graphic controller is an indexed I/O register. First you must set the index on address 3D6h to 71h then you can read the data from address 3d7h CFG15 CFG1 CFG13 CFG12 CFG11 CFG10 CFG9 CFG8 X X X X X X X X R R R R R R R R CFG8 (R): User Switch3 0 = Switch is ON 1 = Switch is OFF This bit describes the position of the DIP switch SW2-3 (Refer to the chapter 3.2.2). The Switch can be used free by the user. CFG9/15 (R): Not Used CFG10 (R): Video Mode 0 = Panel selected (DIP switch ON) 1 = CRT selected (DIP switch OFF) This bit reflects the position of DIP switch SW2- (refer to chapter 3.2.2). The switch is used to select CRT or Panel operation. CFG[11..1] (R): Panel Type These bits reflect the position of DIP switch SW2-[5..8] (refer to chapter 3.2.2). The switches are used to select the installed panel type. 5.9 EMC FEATURES The IPM6 provides all aspects of quality demanded of an industrial computer system. Development according to EMC requirements supports the user in achieving the CE conformity on the system level. This covers features like on board protection and filter devices on power and I/O lines as well as a carefully designed layout. Immunity and RF emission is kept to a minimum by the 12-layer PCB design. The arrangement of the power planes is lowering the board impedance and improving the RF behavior. RF emissions are additionally kept low by the use of series resistors in clock and high speed lines. Several interface signals contain special filter devices to reduce emitted radiation and to protect against captured radiation. The table below gives an overview over the ESD protected interfaces. The protection levels are taken from the corresponding data sheets and do not represent actual measurements. Interface Level Condition RS-232 Interface ± 8 kv IEC , contact discharge Parallel Interface ± 8 kv Human body model CRT Interface 8 kv IEC , level, contact discharge USB Interface ± kv Human body model, MIL-STD-883, method 3015 Mouse ± 25 kv MIL STD 883C - Methode Keyboard ± 25 kv MIL STD 883C - Methode Table 21: ESD Protection 2001 by MPL AG 28 MEH Rev. A

29 5.10 SYSTEM MANAGEMENT BUS The System Management Bus (SMBus) is a two wire asynchronous serial bus. It is a subset of the I 2 C-Bus from Philips Semiconductors. Through the SMBus the system can communicate with simple peripheral chips like EEPROM, temperature sensor, Clock generator or others. Devices on the onboard SMBus At the address DRAM $50 Clock generator $69 EEPROM 32k $5 LM75 $8 Table 22: Devices On The SM Bus For further information about the System Management Bus refer to the 82371AB [PIIX] manual from Intel ( Serial EEPROM AT2C32 There is a serial EEPROM at the address $5 available on the SMBus with a memory space of 32kBit. For further information about the EEPROM refer to the appropriate manual from ATMEL ( Temperature Sensor LM75 The LM75 is also located at the SMBus at the address $8. For further information about the LM75 refer to the appropriate manual from National ( COMPACT PCI FUNCTION Hot Swap and ENUM# The IPM6 is not hot swappable. But in Systems that support hot swap peripheral cards, the IPM6 can detect a new inserted card with the ENUM# pin. ENUM# is connected to the GPIO13 pin of the Southbridge. Optionally it is possible to connect ENUM# to other signals of the Southbridge INTP, INTS Both Interrupts are not supported by the IPM Global Address (GA) The IPM6 does not support Global Address System Slot Enable The IPM6 runs in a peripheral slot without damaging the system. But the CompactPCI Bus can fail because there are now additional pull ups on the bus. The PCI bridge on the IPM6 senses the system slot enable signal on the CompactPCI bus and goes in tristate mode if the IPM6 is put in a peripheral slot. Therefore in a peripheral slot the IPM6 works as a standalone industrial PC without connection to the CompactPCI Bus Intelligent Platform Management Bus (IPMB) The IPM6 supports a single-ported IPM Bus. As the Baseboard Management Controller (BMC) is used the Southbridge System Management Bus (SMB) Controller. On the SM Bus are therefor the devices on the IPM6 (see chapter 5.10) and the devices on the CompactPCI IPM Bus like peripheral cards, power supplies or others. For further information refer to the 82371AB [PIIX] manual from Intel ( and to the PICMG 2.9 R1.0 System Management Specification ( Push Button Reset PRST# on the backplane resets the whole IPM6, which resets the whole CompactPCI Bus by MPL AG 29 MEH Rev. A

30 JTAG On the JTAG pins, there are only pull-ups or pull-downs to define the signal level. The JTAG bus is not supported REQ#/GNT# The IPM6 supports 7 peripheral slots with Clock, Request and Grant signals by MPL AG 30 MEH Rev. A

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33 COPYRIGHT AND REVISION HISTORY Copyright 2001 by MPL AG Elektronikunternehmen. All rights reserved. Reproduction of this document in part or whole, by any means is prohibited, without written permission from MPL AG Elektronikunternehmen. This manual reflects Revision A of the IPM6-1. DISCLAIMER The information contained herein is believed to be accurate as of the date of this publication, however, MPL AG will not be liable for any damages, including indirect or consequential, arising out of the application or use of any product, circuit or software described herein. MPL AG reserves the right to make changes to any product herein to improve reliability, function or design. TRADEMARKS PICMG, CompactPCI and the PICMG, CompactPCI logos are registered trademarks of the PCI Industrial Computers Manufacturers Group. Brand or product names are trademarks and registered trademarks of their respective holders. Our local distributor: 2001 by MPL AG 33 MEH Rev. A