Image Processing & Video Algorithms with CUDA
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1 Image Processing & Video Algorithms with CUDA Eric Young & Frank Jargstorff 8 NVIDIA Corporation.
2 introduction Image processing is a natural fit for data parallel processing Pixels can be mapped directly to threads Lots of data is shared between pixels Advantages of CUDA vs. pixel shader-based image processing CUDA supports sharing image data with OpenGL and DirectD applications 8 NVIDIA Corporation.
3 overview CUDA for Image and Video Processing Advantages and Applications Video Processing with CUDA CUDA Video Extensions API YUVtoARGB CUDA kernel Image Processing Design Implications API Comparison of CPU, D, and CUDA CUDA for Histogram-Type Algorithms Standard and Parallel Histogram CUDA Image Transpose Performance Waveform Monitor Type Histogram 8 NVIDIA Corporation.
4 advantages of CUDA Shared memory (high speed on-chip cache) More flexible programming model C with extensions vs HLSL/GLSL Arbitrary scatter writes Each thread can write more than one pixel Thread Synchronization 8 NVIDIA Corporation.
5 applications Convolutions Median filter FFT Image & Video compression DCT Wavelet Motion Estimation Histograms Noise reduction Image correlation Demosaic of CCD images (RAW conversion) 8 NVIDIA Corporation.
6 shared memory Shared memory is fast Same speed as registers Like a user managed data cache Limitations 6KB per multiprocessor Can store 64 x 64 pixels with 4 bytes per pixel Typical operation for each thread block: Load image tile from global memory to shared Synchronize threads Threads operate on pixels in shared memory in parallel Write tile back from shared to global memory Global memory vs Shared Big potential for significant speed up depending on how many times data in shared memory can be reused 8 NVIDIA Corporation.
7 convolution performance G8 Separable Convolution Performance Mpixels / sec CUDA OpenGL Filter size (pixels) 8 NVIDIA Corporation.
8 separable convolutions Filter coefficients can be stored in constant memory Image tile can be cached to shared memory Each output pixel must have access to neighboring pixels within certain radius R This means tiles in shared memory must be expanded with an apron that contains neighboring pixels Only pixels within the apron write results The remaining threads do nothing 8 NVIDIA Corporation.
9 tile apron Image Image Apron Tile Tile with Apron 8 NVIDIA Corporation.
10 image processing with CUDA How does image processing map to the GPU? Image Tiles Grid/Thread Blocks Large Data Lots of Memory BW D Region Shared Memory (cached) 8 NVIDIA Corporation.
11 define tile sizes #define TILE_W 6 #define TILE_H 6 #define R // filter radius #define D (R*+) // filter diameter #define S (D*D) // filter size #define BLOCK_W (TILE_W+(*R)) #define BLOCK_H (TILE_H+(*R)) 8 NVIDIA Corporation.
12 simple filter example global void d_filter(int *g_idata, int *g_odata, unsigned int width, unsigned int height) { shared int smem[block_w*block_h]; int x = blockidx.x*tile_w + threadidx.x - R; int y = blockidx.y*tile_h + threadidx.y - R; // clamp to edge of image x = max(, x); x = min(x, width-); y = max(y, ); y = min(y, height-); unsigned int index = y*width + x; unsigned int bindex = threadidx.y*blockdim.y+threadidx.x; // each thread copies its pixel of the block to shared memory smem[bindex] = g_idata[index]; syncthreads(); 8 NVIDIA Corporation.
13 simple filter example (cont.) // only threads inside the apron will write results if ((threadidx.x >= R) && (threadidx.x < (BLOCK_W-R)) && (threadidx.y >= R) && (threadidx.y < (BLOCK_H-R))) { float sum = ; for(int dy=-r; dy<=r; dy++) { for(int dx=-r; dx<=r; dx++) { float i = smem[bindex + (dy*blockdim.x) + dx]; sum += i; } } g_odata[index] = sum / S; } } 8 NVIDIA Corporation.
14 sobel edge detect filter Two filters to detect horizontal and vertical change in the image Computes the magnitude and direction of edges We can calculate both directions with one single CUDA kernel C horizontal C vertical = = Magnitude Sobel = norm Ghorizontal + G vertical Direction Sobel G = arctan G vertical horizontal 8 NVIDIA Corporation.
15 sobel edge detect filter x window of pixels for each thread C vertical C horizontal = G = G vertical horizonta Magnitude = norm G + G Sobel horizontal vertical 8 NVIDIA Corporation.
16 sobel edge detect filter x window of pixels for each thread C vertical C horizontal = G = G vertical horizonta Magnitude = norm G + G Sobel horizontal vertical 8 NVIDIA Corporation.
17 sobel edge detect filter x window of pixels for each thread C vertical C horizontal = G = G vertical horizonta Magnitude = norm G + G Sobel horizontal vertical 8 NVIDIA Corporation.
18 sobel edge detect filter x window of pixels for each thread C vertical C horizontal = G = G vertical horizonta Magnitude = norm G + G Sobel horizontal vertical 8 NVIDIA Corporation.
19 sobel edge detect filter x window of pixels for each thread C vertical C horizontal = G = G vertical horizonta Magnitude = norm G + G Sobel horizontal vertical 8 NVIDIA Corporation.
20 sobel edge detect filter x window of pixels for each thread C vertical C horizontal = G = G vertical horizonta Magnitude + Sobel = norm Ghorizontal Gvertical 4 8 NVIDIA Corporation.
21 sobel edge detect filter x window of pixels for each thread C vertical C horizontal = G = G vertical horizonta Magnitude = norm G + G Sobel horizontal vertical 8 NVIDIA Corporation.
22 sobel edge detect filter x window of pixels for each thread C vertical C horizontal = G = G vertical horizonta Magnitude = norm G + G Sobel horizontal vertical 8 NVIDIA Corporation.
23 fast box filter Allows box filter of any width with a constant cost Rolling box filter Uses a sliding window Two adds and a multiply per output pixel Adds new pixel entering window, subtracts pixel leaving Iterative Box Filter Gaussian blur Using pixel shaders, it is impossible to implement a rolling box filter Each thread requires writing more than one pixel CUDA allows executing rows/columns in parallel Uses texd to improve read performance and simplify addressing 8 NVIDIA Corporation.
24 fast box filter Separable, two pass filter. First row pass, then column pass Source Image (input) Output Result 8 NVIDIA Corporation.
25 fast box filter (row pass pixel ) Assume r =, each thread works pixels along the row and sums (r+) pixels Then average (r+) pixels and writes to destination ( i, j ) (r + ) = 8 NVIDIA Corporation.
26 fast box filter (row pass pixel ) Take previous sum from pixel, - pixel ( i - (r+), j ), + pixel ( i +(r+), j) Average (r+) pixels and Output to ( i, j ) 8 NVIDIA Corporation.
27 fast box filter (finish row pass) Each thread continues to iterate until the entire row of pixels is done Average then Write to ( i, j ) in destination image A single thread writes the entire row of pixels Note: Writes are not coalesced Solution: Use shared memory to cache results per warp, call syncthreads(), then copy to global mem to achieve Coalescing 8 NVIDIA Corporation.
28 Column Filter Pass (final) Threads (i, j) read from global memory and sum along the column from row pass image, we get Coalesced Reads Compute pixel sums from previous pixel, - pixel, + pixel Average result and Output to (i, j). We get Coalesced Writes 8 NVIDIA Corporation.
29 Video processing with CUDA GPU has different engines Video Processor (decoding video bitstreams) CUDA (image and video processing) DMA Engine (transfers data host GPU) CUDA enables developers to access these engines 8 NVIDIA Corporation.
30 CUDA Video Extensions NVCUVID: video extension for CUDA Access to video decoder core requires VP (> G8) Similar to DXVA API, but will be platform OS independent. Interoperates with CUDA (surface exchange) with OpenGL and DirectX CUDA SDK.: cudavideodecode 8 NVIDIA Corporation.
31 Video Processor (VP) VP is a dedicated video-decode engine on NVIDIA GPUs. Supports: MPEG-, MPEG- H.64 Can operate in parallel with GPU s DMA engines and D Graphics engine. Very low power. 8 NVIDIA Corporation.
32 YUV to RGB conversion Video Processor Decodes directly to a NV surface 4:: that can be mapped directly to a CUDA surface Y samples (bytes) are packed together, followed by interleaved Cb, Cr samples (bytes) sub sampled x CUDA Kernel performs YUV to RGB R..4 G = B..77 Y C C b r 8 NVIDIA Corporation.
33 YUV to RGB CUDA kernel global void YUVRGB(uint *yuvi, float *R, float *G, float *B) { float luma, chromacb, chromacr; // Prepare for hue adjustment (-bit YUV to RGB) luma = (float)yuvi[]; chromacb = (float)((int)yuvi[] - 5.f); chromacr = (float)((int)yuvi[] - 5.f); } // Convert YUV To RGB with hue adjustment *R = MUL(luma, consthuecolorspacemat[]) + MUL(chromaCb, consthuecolorspacemat[]) + MUL(chromaCr, consthuecolorspacemat[]); *G = MUL(luma, consthuecolorspacemat[]) + MUL(chromaCb, consthuecolorspacemat[4]) + MUL(chromaCr, consthuecolorspacemat[5]); *B = MUL(luma, consthuecolorspacemat[6]) + MUL(chromaCb, consthuecolorspacemat[7]) + MUL(chromaCr, consthuecolorspacemat[8]); 8 NVIDIA Corporation.
34 NVCUVID API Five entry-points for Decoder object: cuvidcreatedecoder(...); cuviddestroydecoder(...); cuviddecodepicture(...); cuvidmapvideoframe(...); cuvidunmapvideoframe(...); Sample application also uses helper library for Parsing video streams. Provided in binary as part of SDK 8 NVIDIA Corporation.
35 cudavideodecode Demo 8 NVIDIA Corporation.
36 Image Processing (contd.) Image Processing: CPU vs. D APIs vs. CUDA Design implications CUDA for Histogram-Type Algorithms Standard and Parallel Histogram CUDA Image Transpose Performance Waveform Monitor Type Histogram 8 NVIDIA Corporation.
37 API Comparison API CPU Code D API (DX/GL) CUDA Code Image Data Heap Allocated Texture/FB CUDA D Allocate Alignment Matters n/a Matters Cached Yes Yes No Access (r/w) Random/random Random/fixed Random/random Access order Matters (general purpose caches) Minimized (D Caching Schemes) Matters (coalescing, CUDA Array -> Texture HW) In-Place Good n/a Doesn t matter Threads Few per Image (Programmer s decision. But typically one per tile; one tile per core) One Per Pixel (Consequence of using Pixel Shaders) One per few Pixels (Programmer s decision. Typically one per input or output pixel) Data Types All bit-float (half-float maybe) Storage Types All Tex/FB Formats All All (Double precision, native instructions not for all though) 8 NVIDIA Corporation.
38 Histogram Extremely Important Algorithm Histogram Data used in large number of compound algorithms: Color and contrast improvements Tone Mapping Color re-quantization/posterize Device Calibration (Scopes see below) 8 NVIDIA Corporation.
39 Histogram Performance D API not suited for histogram computation. CUDA Histogram is x faster than previous GPGPU approaches: 64 bins 56 bins CUDA¹ 65 MB/s 676 MB/s RVB².8 MB/s 4.6 MB/s CPU³ 86 MB/s 96 MB/s ¹ ² Efficient Histogram Generation Using Scattering on GPUs, T. Sheuermann, AMD Inc, ID 7 ³ Intel GHz 8 NVIDIA Corporation.
40 Histogram Algorithm Distribution of intensities/colors in an image Standard algoritm: for all i in [, max_luminance]: h[i] = ; for all pixel in image: ++h[luminance(pixel)] How to parallelize? Reinhard HDR Tonemapping operator 8 NVIDIA Corporation.
41 Histogram Parallelization Subdivide for-all-pixel loop Thread works on block of pixels (in extreme, one thread per pixel) Need ++h[luminance(pixel)] to be atomic (global atomics >= compute_) Breaking up Image I into sub-images I = UNION(A, B): H(UNION(A, B)) = H(A) + H(B) Histogram of concatenation is sum of histograms 8 NVIDIA Corporation.
42 Better Parallel Histogram Have one histogram per thread Memory consumption! Consolidate sub-histograms in parallel (parallel-reduction). CUDA: Histograms in shared memory 64bins * 56threads = 6kByte (8bit bins) Approach not feasible for >64 bins 8 NVIDIA Corporation.
43 >64bins Parallel Histogram Compute capability. has sharedmemory atomic-operations. Victor Podlozhnyuk Manual shared memory per-warp atomics (CUDA SDK histogram56 sample) Have groups of threads work on one sub-histogram, reduce as before. 8 NVIDIA Corporation.
44 Real-World Problems with Histograms My attempt to implement a waveform monitor for video using CUDA. One histogram per column of the input video frame. In order to achieve good performance need to solve various memory-access related issues. 8 NVIDIA Corporation.
45 Accessing 8-bit Pixels Input video produces Y-channel (luma) as planar data in row-major form. Coalescing: 6 threads access bit word in subsequent locations. 8 NVIDIA Corporation.
46 SMEM Exhausted! => 6xM thread blocks => 64 columns processed by each block. => 64 histograms in smem: 64 * 56 * 4 = 64kByte. Max 6 kbyte! 8 NVIDIA Corporation.
47 Thread-Block Dimensions 6xM TB dimensions desirable but impossible for Y-surface read Nx TB dimensions desirable for manual atomics in waveform code Solution: Fast transpose input image! Also: Result histograms could be copied efficiently (shared->global) horizontally. 8 NVIDIA Corporation.
48 Image Transpose Problem: Writing a fast Transpose vs. writing Transpose fast. Naïve implementation: kernel(char * pi, int si, char * po, int so, int w, int h) { int x = blockidx.x * blockdim.x + threadidx.x; int y = blockidx.y * blockdim.y + threadidx.y; } if (y < w && x < h) OUTPUT_PIXEL(y, x) = INPUT_PIXEL(x, y); 8 NVIDIA Corporation.
49 Problems with Naïve Code Memory reads AND writes not coalesced because reading/writing bytes, not words. Bandwidth: ~ GByte/s (of ~4max) Idea: Need to read (at least) 6 words in subsequent threads. Need to write (at least) 6 words in subsequent threads. 8 NVIDIA Corporation.
50 Improved Transpose Idea Subdivide image into micro-blocks of 4x4 pixels (6Byte). Thread blocks of 6x6 threads. Each thread operates on a microblock. Shared memory for micro-blocks: 6 x 6 x 4 x 4 = 4kByte. 8 NVIDIA Corporation.
51 Basic Algorithm Each thread reads its micro-block into shared memory. Each thread transposes its microblock. Each thread writes its micro-block back into global memory. 8 NVIDIA Corporation.
52 Reading and Writing MicroBlocks Reading one row of MicroBlock via unsigned int rather than 4x unsigned char 8 NVIDIA Corporation.
53 6x6 Thread Blocks One (6-thread) warp reads one row of MicroBlocks. t t t t5 t6 t7 t8 t One 6x6 block of threads deals with a 64x64 pixel region (8-bit luminance pixels). 8 NVIDIA Corporation.
54 Pseudo Code Assume single 64x64 image. kernel(...) { int i = threadidx.x; int j = threadidx.y; } readmicroblock(image, i, j, shared, i, j); transposemicroblock(shared, i, j); writemicroblock(shared, i, j, image, j, i); Problem: Non-coalesced writes! 8 NVIDIA Corporation.
55 Write Coalescing for Transpose readmicroblock(image, i, j, shared, i, j); writemicroblock(shared, i, j, image, j, i); Input Image Output Image t t t t5 t t6 t t6 t7 t8 t t t7 t 8 NVIDIA Corporation.
56 Coalesced Writes Simple fix: kernel(...) { int i = threadidx.x; int j = threadidx.y; } readmicroblock(image, i, j, shared, i, j); transposemicroblock(shared, i, j); syncthreads(); writemicroblock(shared, j, i, image, i, j); Must syncthreads() because T i,j now writes data produced by T j,i. 8 NVIDIA Corporation.
57 Transpose Performance Algorithm 56x56 5x5 4^ 48^ 496^ CUDA Naive CUDA Opt IPPI Unit: GB/s throughput. GPU: GeForce GTX 8 (GT) CPU: Intel Core Duo 8 NVIDIA Corporation.
58 Summary Memory access crucial for CUDA performance. Shared memory as user-managed cache. 8-bit images especially tricky. Extra pass may improve over all performance. 8 NVIDIA Corporation.
59 Waveform Demo 8 NVIDIA Corporation.
60 Questions? Eric Young Frank Jargstorff 8 NVIDIA Corporation.
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