Training Program. Advanced Design Program in Semiconductors Technology

Transcription

1 Advanced Design Program in Semiconductors Technology Training Program

2 PADTS A program supported by the Jalisco State Governement Consejo Estatal de Ciencia y Tecnología CoecytJal A program hosted by Cinvestav-CTS Centro de Tecnología de Semiconductores CTS PADTS objectives To train 500 ASIC-MPU embedded-soc design engineers in a period of 5 years To impel the development of the design industry in the region To attract new investments to the region To seed the grains of the future High-Tech Jalisco s companies Cinvestav Design & Education Center Industry

3 CTS Organization Chart DIECC Director J. Luis Leyva Assistant Carolina Mata Administration CTS R&D Manager Jorge Gamboa Academic Counselor Manuel Ramírez General Administrator Rosa Michel Facilities Services Elvia López VoIP Project Manager Miguel Ramírez Computer Sc. Coord. Felix Ramos Accountable Veronica Muñoz 3M Project Manager Rodrigo Morones Autom. Control Coord. Antonio Ramírez Reception Aurora Corona HP Project Manager Carlos López Electronic Des. Coord. Federico Sandoval Messanger & Driver Patricio Mata Phogenix Project Manager Javier Rico Power Eng. Coord. J. Manuel Rodriguez Software Project CDS Felix Ramos Telecom. Coord. Deni Torres PADTS, 500 ASIC-SoC SoC Designers Antonio Martinez Library Resp. Aracely Calzado Planning Francisco. de la Torre

4 Why CTS? Experience of developing products for the industry Support to R&D groups Creation of new companies Semiconductors & SW Applications Design House CTS has 15 years experience in the field supporting the electronic industry

5 Mission of PADTS Create a semiconductor technology educational center in Guadalajara Leadership in the formation of world class high performance designers - Continues formation of professional designers - Keep up with cutting edge technologies and design methodologies - Keep up a program driven by technology, market and business trends - Funding by developing industry projects Contribute in the development of the economy of semiconductors design industry in Mexico. - Keep up with the best practices in high technology business - Incubate and spin off new semiconductors design houses Objective for the next 5 years designers Spin off Design Houses

6 Business model and new CTS organization Strategy Reinforce the current CTS lab infrastructure Develop CTS intellectual property (IP) Develop marketing, business, finance and sales forces Develop Business Plan and involve Venture Capital Incubate new design houses in the region PADTS is the educational program while CTS-R&D lab is the Hands on industry projects partner

7 Schedule B C D E F G H I J K L M N O P Q R S H1-02 H2-02 H1-03 H2-03 H1-04 H2-04 H1-05 H2-05 H1-06 H2-06 H1-07 H2-07 H1-08 Phase 1 Conceptualization and program set up Phase 2 PADTS Program New CTS Program 25 Associated Designers 25 Associated Designers Phase Designers (TBD) Phase Designers (TBD) Phase Designers (TBD) Phase Designers (TBD) Develop Business Infrastructure Business ramp up & IP generation Creation of new DESIGN HOUSES

8 Budget Program set up Sep-02 to Feb Associated Designers 03 and early 04

9 Training strategy Based in teaching the Know-How First 6 months Review of a set of theoretical courses Learn the use of the design automation tools Learn the ASIC design Know-How based in uprocessor structures Following months Work in CTS design projects for industry It is our objective that at the end of first six months, the trainee could be incorporated in CTS design projects under the tutoring of a Senior engineer

10 Training strategy (model) Engineering level requirements Industry projects Associated Designer Level System Designer Level Design Leader Level Scientific Designer Level Specialization lectures and seminars

11 Training strategy (cont.) Scientific Designers Design Leaders/ Design Mgr. CTS System Designer Associated Designer Technical Design Support

12 The business vision

13 PADTS program 1 month 2 months. Prerequisites courses Calculus and differential equations Electric circuits Object programming (C++ and JAVA reference) Personality development Regular courses Linear algebra, Taylor and Fourier series and Fourier transforms Semiconductors fundaments Boolean algebra and digital design Micropocessors and computer architectures RTOS fundamentals (Linux) PLC, design specs and quality concepts Emotional intelligence development dynamics English Full time availability is required

14 PADTS program (cont.) 4 months ASIC design (ASIC design flow from modeling to net list generation) MPU 8 bits design ( Design for methodologies and clues) Design project Following months Industry projects (be part of a design team working on real industry projects)

15 Scholarship program Covers: 100% of the cost of lectures and seminars labs usage and lab s material library usage Prerequisites to be accepted and obtain the scholarship Pass all prerequisites courses exams with a minimum note of 8.0 Pass interviews round with instructors and PADTS personnel Full time availability

16 Key dates Information sessions at CINVESTAV campus GDL - January 29 (12:00pm) - February 1 (12:00 pm) Students sign up starting January 29 Interviews Feb 3-13 Start of prerequisites course Feb 16 (1 month duration)

17 Information Aida Iruegas, PADTS Academic Coordinator - aida.iruegas@cts-design.com - Tel (33) x 2036 Jesús Vázquez, Special Seminars & Lectures Coordinator - jesus.vazquez@cts-design.com - Tel (33) x2012 Francisco de la Torre, CINVESTAV University Liaison - nexo@gdl.cinvestav.mx - Tel (33) x 2079 Web site

18 Industry Sponsors Details of Industry sponsoring program is under definition

19 Similar programs in the world International Education Centers ECSI European Electronic Chips & System Integration SED Indian School of Electronics Design (Sirius) VDEC Japan VLSI Design & Education Center ISLI Scotland Institute for System Level Integration IDEC Korean IC Design Education Center Education Centers Universities Industry Recreate industry context

20 A new paradigm of design training in Mexico