Experiment 4 Op-Amp Circuits

Transcription

1 Experiment 4 Op-Amp Circuits Purpse: In this experiment, yu will learn abut peratinal amplifiers (r p-amps). Simple circuits cntaining peratinal amplifiers can be used t perfrm mathematical peratins, such as additin, subtractin, and multiplicatin, n signals. They can als be used t take derivatives and integrals. Anther imprtant applicatin f an p-amp circuit is the vltage fllwer, which serves as an islatr between tw parts f a circuit. Backgrund: Befre ding this experiment, students shuld be able t Analyze simple circuits cnsisting f cmbinatins f resistrs, inductrs and capacitrs Measure resistance using a Multimeter and capacitance using a cmmercial impedance bridge. D a transient (time dependent) simulatin f circuits using Capture/PSpice D an AC sweep (frequency dependent) simulatin f circuits using Capture/Pspice, determining bth the magnitude and the phase f input and utput vltages. Build simple circuits n prtbards and measure input and utput vltages vs. time. Review the backgrund fr the previus experiments. Learning Outcmes: Students will be able t Cnnect an p-amp chip (DIP package) in a standard cnfiguratin n a prtbard (signal and pwer) Investigate the perfrmance f standard inverting and nn-inverting p-amp circuits three ways: Determine the gain f standard inverting and nn-inverting p-amp circuits Simulate the peratin f standard inverting and nn-inverting p-amp circuits using PSpice Experimentally determine the gain f standard inverting and nn-inverting p-amp circuits Identify perating cnditins under which practical p-amps perate clse t their ideal predictins. Investigate standard p-amp vltage fllwers (but n physical experiment). Investigate the perfrmance f standard p-amp integratrs and differentiatrs fllwing the same apprach as with inverting and nn-inverting amplifiers. Build and analyze practical integratrs (aka Miller Integratrs) that perate like their ideal cunterparts Build and analyze practical differentiatrs that perate like their ideal cunterparts Investigate p-amp adders (but n physical experiment). Perfrm basic mathematical peratins n electrical signals using p-amp circuits. Equipment Required: Analg Discvery (with Wavefrms Sftware) DC Vltage Surces (tw 9V batteries) Analg I/O ( Analg Discvery) Prtbard Sme Resistrs (5, 1k, 1k and 1kΩ) 741 p-amp Nte that there is n special equipment required fr this experiment, s the wrk can be dne anywhere. Yu still have t get checked ff in class, but yu have a lt f flexibility in where yu cmplete mst f the tasks. Helpful links fr this experiment can be fund n the Links by Experiment page fr this curse. Be sure t check ut the key links and at least glance thrugh the entire list fr this experiment. It is particularly imprtant t cmpletely read, and keep handy, the handut n Integratrs and Differentiatrs. Pre-Lab Required Reading: Befre beginning the lab, at least ne team member must read ver and be generally acquainted with this dcument and the ther required reading materials listed under Experiment 4 n the EILinks page. Hand-Drawn Circuit Diagrams: Befre beginning the lab, hand-drawn circuit diagrams must be prepared fr all circuits either t be analyzed using PSpice r physically built and characterized using yur Analg Discvery bard. K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

2 Part A Intrductin t Op-Amp Circuits Backgrund Elements f an p-amp circuit: Figure A-1 belw is a schematic f a typical circuit built with an p-amp. Rf eedback 1k Vin Rin 1k U ua741 V2 9Vdc V+ 5 OS2 6 OUT 1 OS1 V- V1 9Vdc Vut Rlad Figure A-1. Drawn with the 741 p-amp (Rlad 1kΩ). The circuit perfrms a mathematical peratin n an input signal. This particular p-amp circuit will invert the input signal, Vin, and make the amplitude 1 times larger. This is equivalent t multiplying the input by -1. Nte that there are tw DC vltage surces in additin t the input. These tw DC vltages pwer the p-amp. The circuit needs additinal pwer because the utput is bigger than the input. Op-amps always need pwer surces. The tw resistrs R feedback and R in determine hw much the p-amp will amplify the utput. If we change the magnitude f these resistrs, we d nt change the fact that the circuit multiplies by a negative cnstant; we nly change the magnitude f the multiplier. The lad resistr R lad is nt part f the amplifier. It represents the resistance f the lad n the amplifier. Pwering the p-amp: The tw DC surces, (labeled as V+ and V-, but als ften labeled as ± V CC ), that prvide pwer t the p-amp are typically set t have an equal magnitude but ppsite sign with respect t the grund f the circuit. This enables the circuit t handle an input signal which scillates arund V, like mst f the signals we use in this curse. (Nte the signs n the surces in the circuit abve.) The schematic in Figure A-2 shws a standard ± V CC cnfiguratin fr p-amps. The schematic symbls fr a battery are used in this schematic t remind us that these supplies need t be a cnstant DC vltage. They are nt signal surces. Figure A-2. WE WILL Use tw 9V batteries fr pwer. Batteries are self-explanatry. Nte that in PSpice, there are tw ways t represent a surce with a negative sign. Figure A-3 shws the tw ptins: yu can either set the vltage surce t a negative value, r yu can reverse the plarity f the surce. K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

3 Figure A-3. The p-amp chip: Study the chip layut f the 741 p-amp shwn in Figure A-4. The standard prcedure n DIP (dual in-line package) "chips" is t identify pin 1 with a ntch in the end f the chip package. The ntch always separates pin 1 frm the last pin n the chip. Pin 2 is the inverting input. Pin 3 is the nn-inverting input, and the amplifier utput, V O, is at pin 6. These three pins are the three terminals that nrmally appear in an p-amp circuit schematic diagram. The +V CC and -V CC cnnectins (7 and 4) MUST be cmpleted fr the p-amp t wrk, althugh they usually are mitted frm simple circuit schematics t imprve clarity. Figure A-4. The balance (r null ffset) pins (1 and 5) prvide a way t eliminate any ffset in the utput vltage f the amplifier. The ffset vltage (usually dented by Vs) is an artifact f the integrated circuit. The ffset vltage is additive with V O (pin 6 in this case). It can be either psitive r negative and is nrmally less than 1mV. Because the ffset vltage is s small, in mst cases we can ignre the cntributin V OS makes t V O and we leave the null ffset pins pen. Pin 8, labeled "NC", has n cnnectin t the internal circuitry f the 741, and is nt used. Op-amp limitatins: Just like all real circuit elements, p-amps have certain limitatins which prevent them frm perfrming ptimally under all cnditins. The ne yu are mst likely t encunter in this class is called saturatin. An p-amp becmes saturated if it tries t put ut a vltage level beynd the range f the pwer surce vltages, ±V CC, Fr example, if the gain tries t drive the utput abve 9V, the p-amp is nt supplied with enugh vltage t get it that high and the utput will cut ff at the mst it can prduce. This is never quite as high as 9V because f the lsses inside the p-amp. Anther cmmn limitatin is amunt f current an p-amp can supply. Large demands fr current by a lw resistance lad can interfere with the amunt f current available fr feedback, and result in less than ideal behavir. Als, because f the demands f the internal circuitry f the device, there is nly s much current that can pass thrugh the p-amp befre it starts t verheat. A third limitatin is called the slew rate and is the result f limited internal currents in the p-amp. Delays caused by the slew rate can prevent the p-amp circuit frm displaying the expected utput instantaneusly after the input changes. The final cautin we have abut p-amps is that the equatins fr p-amps are derived using the assumptin that an p-amp has infinite intrinsic (internal) gain, infinite input impedance, zer current at the inputs, and zer utput impedance. Naturally these assumptins cannt be true, hwever, the characteristics f real p-amps are clse enugh t the assumptins that circuit behavir is clse t ideal ver a large range. K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

4 The inverting amplifier: Figure A-5 shws an inverting amplifier. Its behavir is gverned by the fllwing equatin: Figure A-5. V ut R f = Vin. The negative sign indicates that the circuit R will invert the signal. (When yu invert a signal, yu switch its sign. This is equivalent t an18 phase shift f a sinusidal signal.) The circuit will als amplify the input by R f /R in. Therefre, the ttal gain fr this circuit is (R f /R in ). Nte that mst p-amp circuits invert the input signal because p-amps stabilize when the feedback is negative. Als nte that even thugh the cnnectins t V+ and V- (±V CC ) are nt shwn, they must be made in rder fr the circuit t functin in bth PSpice and n yur prtbard. The nn-inverting amplifier: Figure A-6 shws a nn-inverting amplifier. Its behavir is gverned by the fllwing R equatin: Vut Vin R = in Figure A-6. This circuit multiplies the input by 1+(R 2 /R 1 ) and, unlike the previus p-amp circuit, the utput is nt an inversin f the input. The verall gain fr this circuit is, therefre, 1+(R 2 /R 1 ). The inverting amplifier is mre cmmnly used than the nn-inverting amplifier. That is why the smewhat dd term nn-inverting is used t describe an amplifier that des nt invert the input. If yu lk at the circuits, yu will see that in the inverting p-amp, the chip is cnnected t grund, while in the nn-inverting amplifier it is nt. This generally makes the inverting amplifier behave better. When used as a DC amplifier, the inverting amp can be a pr chice, since its utput vltage will be negative. Hwever, fr AC applicatins, inversin des nt matter since sines and csines are psitive half the time and negative half the time anyway. Experiment The Inverting Amplifier In this part f the experiment, we will wire a very simple p-amp circuit using PSpice and lk at its behavir. Wire the circuit shwn in Figure A-7 belw in PSpice. K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

5 Figure A-7. The input shuld have 2mV pk-pk amplitude, 1kHz and n DC ffset. The p-amp is called ua741 and is lcated in the EVAL library. Be careful t make sure that the + and inputs are nt switched and that the tw DC vltage supplies have ppsite signs. Nte the lcatin f the input vltage, Vin. Rin is the input resistr, s the marker ges t its left. Run a transient simulatin f this circuit that displays three cycles. What des the equatin fr this type f circuit predict fr its behavir? Use the cursrs t mark the amplitudes f the input and utput f the circuit. Calculate the actual gain n the circuit. Is this clse t the gain predicted by the equatin? Cpy this plt and include it with yur reprt. Run a transient f the circuit with a much higher input amplitude. Change the amplitude f the surce t 5V and rerun the simulatin. What des the equatin predict fr the behavir this time? Des the circuit display the utput as expected? What happened? Use the cursrs t mark the maximum value f the input and utput f the circuit. What is the magnitude f the utput f the circuit at saturatin? Cpy this plt and include it with yur reprt. Build an Inverting Amplifier In this part f the circuit, yu will build an inverting amplifier. Build the circuit using the 741 p-amp. Use 2 batteries t prvide the +9V and 9V pwer surces. Build the inverting p-amp circuit in Figure A-7 n yur prtbard. Dn t neglect t wire the DC pwer vltages at pins 4 and 7. D nt cnnect either pin 4 r 7 t grund (Black). Fllw the battery cnnectin guidance shwn abve. Remember t use Scpe Channel 1+ (Orange), Scpe Channel 2+ (Blue) fr the tw vltage measurements and Wavefrm Generatr W1 (Yellw) as yur surce. Als, cnnect Analg Discvery grund and the negative leads (1- & 2-) fr channels 1 & 2 t circuit grund (als the reference fr the batteries). Examine the behavir f yur circuit. K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

6 Take a picture with the Analg Discvery scpe display f the input and utput f the circuit at 1kHz and 2mV amplitude and include it in yur reprt. Always measure bth input and utput, even when yu are nt specifically asked t. What was the gain f yur circuit at this amplitude and frequency? [Use the signals t calculate the gain, nt the values f the resistrs.] Saturatin: Change R feedback t a 22kΩ resistr. Vary the amplitude f the functin generatr until the pamp utput starts t saturate. At abut what input amplitude des this happen? What is the magnitude f the utput f the circuit at saturatin? Hw des this cmpare with the saturatin vltage fund using PSpice? Des it saturate at the same psitive and negative vltage? Summary As lng as ne remains aware f sme f their limitatins, p-amp circuits can be used t perfrm many different mathematical peratins. That is why cllectins f p-amp circuits have been used in the past t represent dynamic systems in what is called an analg cmputer. There are sme very gd pictures f analg cmputers and ther cmputers thrugh the ages at H.A. Layer s Mind Machine Web Museum. A link is lcated n the curse links page. Part B Vltage Fllwers Backgrund The vltage fllwer: The p-amp cnfiguratin in Figure B-1 is called a vltage fllwer r buffer. Nte that the circuit abve has n resistance in the feedback path. Its behavir is gverned by the equatin: V = V. ut in Figure B-1. V = V, this circuit wuld appear t d nthing at all. In circuit design, If ne cnsiders nly the equatin ut in hwever, vltage fllwers are very imprtant and extremely useful. What they allw yu t d is cmpletely separate the influence f ne part f a circuit frm anther part. The circuit supplying V in will see the buffer as a very high impedance, and (as lng as the impedance f the input circuit is nt very, very high), the buffer will nt lad dwn the input. (This is similar t the minimal effect that measuring with the scpe has n a circuit.) On the utput side, the circuit sees the buffer as an ideal surce with n internal resistance. The magnitude and frequency f this surce is equal t V in, but the pwer is supplied by ± V CC. The vltage fllwer is a cnfiguratin that can serve as an impedance matching device. Fr an ideal p-amp, the vltages at the tw input terminals must be the same and n current can enter r leave either terminal. Thus, the input and utput vltages are the same and Z in = V in /I in. In practice Z in is very large which means that the vltage fllwer des nt lad dwn the surce. Experiment A Vltage Fllwer Applicatin In this part, we will investigate the usefulness f a vltage fllwer using PSpice. Begin by creating the circuit pictured in Figure B-2 belw in PSpice. K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

7 R1 1k V V VOFF = V VAMPL =.1V V1 FREQ = 1k AC =.1V R2 1k R3 1 Figure B-2. The surce has amplitude f 1mV and a frequency f 1kHz. The impedance f the functin generatr is assumed t be negligible and has been left ut. R1 and R2 are a vltage divider and R3 is the lad n the vltage divider. Run a simulatin that displays three cycles f the input. Run the simulatin, mark the amplitude f the vltages shwn, and cpy the plt fr yur reprt. If we cmbine R2 and R3 in parallel, we can demnstrate that the amplitude f the utput is crrect fr this circuit. What if ur intentin when we built this circuit was t have the input t the 1Ω resistr be the utput f the vltage divider? i.e. We want the vltage acrss the lad (R3) t be ½ f the input vltage. Clearly the relatinship between the magnitudes f the 1Ω resistr and the 1kΩ resistr in the vltage divider will nt let this ccur. A vltage fllwer is needed. Mdify the circuit yu created by adding an p-amp vltage fllwer between R1 and R2, as shwn in Figure B-3: V 9Vdc V3 VOFF = V VAMPL =.1V FREQ = 1k AC =.1V V1 R1 1k R2 1k V Vdc V- OS1 OUT OS2 V+ V ua741 U1 V R3 1 K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

8 Figure B-3. The p-amp is called ua741 and is lcated in the EVAL library. Be careful t make sure that the + and inputs are nt switched and that the tw DC vltage supplies have ppsite signs. Rerun the simulatin Place vltage markers at the three lcatins shwn. Rerun the simulatin, mark the amplitude f the vltages shwn, and cpy the plt fr yur reprt. What is the vltage acrss the 1Ω lad nw? Have we slved ur prblem? The vltage fllwer has islated the vltage divider electrically frm the lad, while transferring the vltage at the center f the vltage divider t the lad. Because every piece f a real circuit tends t influence every ther piece, vltage fllwers can be very handy fr eliminating these interactins when they adversely affect the intended behavir f ur circuits. It is said that the vltage fllwer is used t islate a signal surce frm a lad. Frm yur results, can yu explain what that means? Vltage fllwers are nt perfect. They are nt able t wrk prperly under all cnditins. T see this, change R3 t 1Ω. Rerun the simulatin, mark the amplitude f the vltages shwn, and cpy the plt fr yur reprt. What d yu bserve nw? Can yu explain it? Refer t the spec sheet fr the 741 p-amp n the links page. Hw have we changed the current thrugh the chip by adding a smaller lad resistance? Finally, it was nted abve that the input impedance f the vltage fllwer shuld be very large. Determine the input impedance by finding the rati f the input vltage t the input current fr the fllwer. Return the value f R3 back t the riginal 1Ω. Recall that R=V/I. We can btain the vltage we need by placing a vltage marker at the nn-inverting input (U1:+) f the p-amp. PSpice will nt allw us it place a current marker at the psitive p-amp input. We can find the current anyway by finding the difference between the current thrugh R1 and R2. Place a current marker n R1 and anther n R2. Summary Set up an AC sweep fr the circuit frm 1 t 1kHz. Frm yur AC sweep results, add a trace f V(U1:+)/(I(R1)-I(R2)). (Nte that yur vltage divider resistrs might have different names if yu placed them n the schematic in a different rder.) Include this plt in yur reprt. What is the input impedance f the p-amp in the vltage fllwer at lw frequencies? (Since PSpice tries t be as realistic as pssible, yu shuld get a large but nt infinite number.) Run the sweep again frm 1kHz t 1MegHz. Is the input impedance still high at very high frequencies? (Nte M is mega and m is milli in PSPice vltage displays.) The vltage fllwer is ne f the mst useful applicatins f an p-amp. It allws us t islate a part f a circuit frm the rest f the circuit. Circuits are typically designed as a series f blcks, each with a different functin. The utput f ne blck becmes the input t the next blck. Smetimes the influence f ther blcks in a circuit prevents ne blck frm perating in the way we intended. Adding a buffer can alleviate this prblem. Part C Integratrs and Differentiatrs Backgrund If yu have nt read the handut n Integratrs and Differentiatrs, please d s nw. K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

9 Ideal differentiatr: Figure C-1 shws an ideal differentiatr. Its behavir is gverned by the fllwing equatin: dvin V ut = RC. dt Figure C-1. The utput f this circuit is the derivative f the input INVERTED and multiplied by RC. Fr a sinusidal input, the magnitude f the gain fr this circuit depends n the values f the cmpnents and als the input frequency. It is equal t (ωrc). The circuit will als cause a phase shift f -9. It is imprtant t remember that there is an inversin in this circuit. Fr instance, if the input is sin(t), then yu wuld expect the utput f a differentiatr t be +cs(t) (a +9 phase shift). Hwever, because f the inversin, the utput phase f this circuit is -9 (+9-18). Als nte that, because ne cannt build a circuit with n input resistance, there is n such thing as an ideal differentiatr. A real differentiatr differentiates nly at certain frequencies. This distinctin is discussed in the PwerPint ntes fr the curse. Ideal integratr: The circuit shwn belw in Figure C-2 is an ideal integrating amplifier. Its behavir is gverned 1 by the fllwing equatin: V ut = Vin dt. RC Figure C-2. The utput f this circuit is the integral f the input INVERTED and multiplied by 1/(RC). Fr a sinusidal input, the magnitude f the gain fr this circuit depends n the values f the cmpnents and als the input frequency. It is equal t 1/(ωRC). The circuit will als cause a phase shift f +9. It is imprtant t remember that there is an inversin in this circuit. Fr instance, if the input is sin(t), then yu wuld expect the utput f an integratr t be - cs(t), a -9 phase shift. Hwever, because f the inversin, the utput phase shift f this circuit is +9 ( ). Als, because the integratin f a cnstant DC ffset is a ramp signal and there is n such thing as a real circuit with n DC ffset (n matter hw small), wiring an ideal integratr will result in an essentially useless circuit. A Miller integratr is an ideal integratr with an additinal resistr added in parallel with C. It will integrate nly at certain frequencies. This distinctin is discussed in the pwer pint ntes fr the curse. Experiment Using an Op-amp Circuit t Integrate an AC Signal in PSpice In this sectin, we will bserve the peratin f a Miller integratr n a sinusid. Yu will examine the way in which the prperties f the integratr change bth the amplitude and the phase f the input. K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

10 Build the integratin circuit shwn belw in Figure C-3. V1 shuld have a 2mV amplitude and 1kHz frequency. R2 1k C1 1uF V+ 9Vdc V VOFF = VAMPL =.2 FREQ = 1k AC =.2 R1 1k Vin U ua741 7 V+ V- 4 OS2 OUT OS1 V- -9Vdc V Vut Rlad 1k Figure C-3. Run a transient analysis. We want t set up the transient t shw five cycles, but we als want t display the utput starting after the circuit has reached its steady state. Set the run time t 15ms, the start time t 1ms, and the step size t 5us. Yu shuld cnfirm that steady-state has been reached. Obtain a plt f yur results. Just like in mathematical integratin, integratrs can add a DC ffset t the result. Adjust yur utput s that it is centered arund zer by adding a trace that adds r subtracts the apprpriate DC value. After yu have dne this, mark the amplitude f yur input and utput with the cursrs. Cpy this plt and include it in yur reprt. Use the equatins fr the ideal integratr t verify that the circuit is behaving crrectly. The equatin that gverns the behavir f this integratr at high frequencies is given by: 1 1 if ω c >> then vut ( t) vin( t) dt R2C1 R1C 1 Recall that the integratin f sin(ωt) = (-1/ω)cs(ωt). Therefre, the circuit attenuates the integratin f the input by a cnstant equal t -1/ωR1C1. The negative sign means that the utput shuld als be inverted. What is there abut the transient respnse that tells yu that the circuit is wrking crrectly? Is the phase as expected? The amplitude? Abve what frequencies shuld we expect this kind f behavir? Nw we can lk at the behavir f the circuit fr all frequencies. D an AC sweep frm 1m t 1kHz. Add a secnd plt and plt the phase f the vltage at Vut. (Either add a p(vut) trace r add a phase marker at the utput f the circuit.) What shuld the value f the phase be (apprximately) if the circuit is wrking mre-r-less like an integratr? Mark the regin n the plt where the phase is within ±2 f the expected value. Cpy this plt Yu will mark this sweep with the data frm the circuit that yu build. We can als use PSpice t check the magnitude t see when this circuit acts best as an integratr. Rerun the sweep. D nt add the phase this time. Using the equatin abve, we knw that at frequencies abve f c, V ut = -V in /(ωrc), where R = R1, C = C1, and ω = 2πf. [We plt the negatin f the input because the equatin fr the transfer functin f the circuit has an inversin. In a sweep, nly the amplitude matters, s the sign is nt imprtant.] K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

11 Change the plt fr the AC sweep f the vltage t shw just V ut and -V in /(ωr1c1). Nte that yu need t input the frequency ω as 2*pi*Frequency in yur PSpice plt. (Pspice recgnizes the wrd pi as the value f π and the wrd Frequency as the current input frequency t the circuit. Als nte that yu must enter numbers fr R1 and C1.) When are these tw signals apprximately equal? It is at these frequencies that the circuit is acting like an integratr. Mark the pint at which the tw traces are within 1mV f each ther. Calculate f c =1/(2πR2C1). Hw clse are the amplitudes f the tw signals at that frequency? At a frequency much greater than f c, the circuit shuld start behaving like an integratr. Mark the crner frequency n yur plt. Cpy this plt. Using an Op-amp Integratr t Integrate a DC Signal Anther way t demnstrate that integratin can be accmplished with this circuit is t replace the AC surce with a DC surce and a switch. Fr Experiment: Cnnect 1+ at the green prbe Fr Experiment: Cnnect 2+ at the red prbe Figure C-4. Mdify yur circuit by replacing the AC surce with a DC surce and a switch as shwn in Figure C-4. Nte that the switch is set t clse at time t=.1sec. Use a vltage f.1v t avid saturatin prblems. The switch is called Sw_tClse and is in the EVAL library. Analyze the circuit with PSpice. D a transient analysis fr times frm t 15ms with a step f 1us. Rather than pltting the utput vltage (vltage at Vut), plt the negative f the utput vltage. Yu shuld see that this circuit des seem t integrate reasnably well. Cpy this plt fr yur reprt. Hw clse is the utput f yur circuit t an integratin f the input? The integratin f a cnstant shuld be a ramp signal f slpe equal t the cnstant. The utput f an integrating p-amp circuit shuld be the inversin f the ramp signal multiplied by a cnstant equal t (1/(R1C1)). K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

12 Calculate the apprximate slpe f the utput. Write it n yur utput plt. Als write the theretical slpe n the plt. Fr what range f times des it integrate reasnably well? (This is smewhat subjective.) Mdify the feedback capacitr Decrease C1 t.1µf and repeat the simulatin. Only run it frm t 14ms this time. Dn t frget t plt the negative f the utput vltage. Cpy yur utput. Mark the theretical slpe n the plt. Calculate the theretical slpe f the utput. Dn t frget that the cnstant, 1/(R1C1), is different because C1 has changed. Des the circuit integrate -- even apprximately -- fr any perid f time? Can yu think f any reasn why we might prefer t use a smaller capacitr in the feedback lp, even thugh the circuit des nt integrate as well ver as lng a perid f time? Create an ideal integratr The circuit we have been lking at is a Miller integratr. An ideal integratr des nt have an extra resistr in the feedback path. What wuld happen if we changed ur circuit t an ideal integratr? Set the feedback capacitr back t its initial value f 1uF. Remve the resistr frm the feedback lp and run yur transient analysis again. Yu shuld see that the circuit n lnger wrks. Negate the utput vltage again. Cpy yur utput. What is wrng with the utput? The ideal integratr circuit will perate n bth the AC and DC inputs. In any real circuit -- n matter hw gd yur equipment is -- nise will create a small variable DC ffset vltage at the inputs. The prblem with this circuit is that there is n DC feedback t keep the DC ffset at the input frm being integrated. Therefre, the utput vltage will cntinuusly increase and, in additin, it will be amplified by the full intrinsic gain f the p-amp. This immediately saturates the p-amp. Building an Op-amp Integratr and an Op-amp Differentiatr In this part f the experiment, we will build an p-amp integratr and an p-amp differentiatr n the prtbard and lk at the utput fr a variety f inputs. Build the p-amp integratr circuit as shwn in Figure C-3. Observe the behavir f the circuit at three representative frequencies. Use the sine wave frm the wavefrm generatr fr the vltage surce, set the amplitude t.2v (.4V P-P ). Obtain measurements f the input and utput vltages at frequencies f 5Hz, 1kHz, and 5kHz. Add yur experimental pints fr bth the amplitude and phase t yur PSpice AC sweep plt fr the abve circuit. Obtain a picture f each f these signals with the Analg Discvery sftware. Observe the utput f the integratr fr different types f inputs Set the functin generatr t a frequency that gives reasnable signal amplitude and integrates fairly well. This is smewhat subjective; we just want yu t see the shapes f the utputs fr different input wave shapes. Set the functin generatr t the fllwing types f inputs: sine wave triangular wave square wave What shuld the integratin f each f these types f inputs be? Take a picture f the utput fr each input with the Analg Discvery sftware. Create a differentiatr. K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

13 Figure C-5. Remve the feedback capacitr, C2. Replace R1 with an input capacitr, C1=1µF. Replace the feedback resistr with a 1k resistr, R2. Yur circuit shuld nw lk like Figure C-5. Set the functin generatr t a frequency that gives a reasnable signal amplitude and differentiates fairly well. This is smewhat subjective; we just want yu t see the shapes f the utputs fr different input wave shapes. Yu may find that yur utput is very nisy and thus it is hard t clearly see whether r nt the circuit is acting like a differentiatr. Read the handut n Integratrs and Differentiatrs t find a suggestin fr hw t address the nise issue. Observe the utput f the differentiatr fr different types f inputs. Set the functin generatr t the fllwing types f inputs: sine wave triangular wave square wave What shuld the differentiatin f each f these types f inputs be? Take a picture f each situatin with the Analg Discvery sftware. Summary Op-amp circuits can be used t d bth integratin and differentiatin. The ideal versins f bth circuits are nt realizable. Therefre, the real versins f these circuits d nt wrk well at all frequencies. Als, as bth types f circuits apprach ptimal mathematical perfrmance, the amplitude f the utput decreases. This makes designing an integratr r a differentiatr a trade-ff between the desired mathematical peratin and signal strength. K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

14 Part D Using Op-Amps t Add and Subtract Signals Backgrund Op-amp adders: Figure D-1 belw shws an adder. Its behavir is gverned by the fllwing equatin: V1 V 2 V ut = Rf +. R1 R2 Figure D-1. The gain fr each input t the adder depends upn the rati f the feedback resistance f the circuit t the value f the resistr at that input. The adder is smetimes called a weighted adder because it prvides a means f multiplying each f the inputs by a separate cnstant befre adding them all tgether. It can be used t add any number f inputs and multiply each input by a different cnstant. This makes it useful in applicatins like audi mixers. The differential amplifier: The circuit in Figure D-2 is a differential amplifier, als called a difference amplifier. Its Rf behavir is gverned by the fllwing equatin: V ut = ( V1 V 2). Rin Figure D-2. It amplifies the difference between the tw input vltages by Rf/Rin, which is the verall gain fr the circuit. Nte that the ability f this amplifier t effectively take the difference between tw signals depends n the fact that it uses tw pairs f identical resistances. Als nte that the signal that is subtracted ges int the negative input t the pamp. Be careful with the term differential. In spite f its similarity t the term differentiatin, the differential amplifier des nt differentiate its input. Amplifying the utput f a bridge circuit: Yu will see in Experiment 5, that it is difficult t measure the AC vltage acrss the utput f a bridge circuit because bth f the utput cnnectins will have a finite DC vltage. The differential amplifier allws us t get by this prblem, since neither input is grunded. A very large fractin f K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

15 measurement circuits use sme kind f a bridge cnfiguratin r are based n sme kind f cmparisn between tw vltages. Thus, the peratin f the differential amplifier is very imprtant t understand fr prject 2. Experiment PSpice Simulatin f an Adder Set up the circuit shwn in Figure D-3 in PSpice. Nte the plarity f the vltage surces prviding ±Vcc t the p-amp. Nte that the amplitude f the surce, V3, is 2V and that the amplitude f the surce, V4, is 1V. Run a simulatin that shws 3 cycles f the input. What is the gain f the adder? What shuld it d t the tw input signals? Is the adder wrking crrectly? Include this simulatin with yur reprt. Adders are ften used as mixers that give different emphasis t each input signal and then cmbine the inputs tgether int ne signal. What wuld we have t set R2 t, if we wanted twice as much f the signal frm V3 t pass thrugh the adder as the signal frm V4. [Nte: This des nt mean changing nthing because V3 already has twice the amplitude as V4. It means mixing in twice as much f the amplitude f V3 as the amplitude f V4 int the final utput signal.] Mdify resistr R2, rerun the simulatin, and verify that the utput f the signal is as expected. Include the utput f the simulatin in yur reprt. Summary Figure D-3. In this experiment we used an adder t add tw signals. Then, we mdified it s that it wuld cmbine the signals with different emphasis, as in an audi mixer. K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

16 Checklist and Cnclusins The fllwing shuld be included in yur experimental checklist. Everything shuld be labeled and easy t find. Partial credit will be deducted fr pr labeling r unclear presentatin. ALL PLOTS SHOULD INDICATE WHICH TRACE CORRESPONDS TO THE SIGNAL AT WHICH POINT. Hand-Drawn Circuit Diagrams fr all circuits that are t be analyzed using PSpice r physically built and characterized using yur Analg Discvery bard. Part A Intrductin t Op-Amp Circuits (14 pints) Include the fllwing plts: 1. PSpice transient f inverting amplifier with input amplitude f 2mV and bth traces marked. (2 pt) 2. PSpice transient f inverting amplifier with input amplitude f 5V and bth traces marked. (2 pt) 3. Analg Discvery picture f input and utput vltages fr the inverting amplifier circuit. (2 pt) Answer the fllwing questins: 1. What is the theretical gain f yur inverting amplifier? What gain did yu find with PSpice when the input amplitude was 2mV? Hw clse are these? (2 pt) 2. What was the actual gain yu gt fr the inverting amplifier yu built? Hw did this cmpare t the theretical gain? Hw did this cmpare t the PSpice gain? (2 pt) 3. What value did yu get fr the saturatin vltage f the 741 p-amp in PSpice? What value did yu get fr the saturatin vltage f the real p-amp in yur circuit? Hw d they cmpare? (2 pt) 4. At what input vltage did the p-amp in the amplifier yu built n the prtbard begin t saturate? (2 pt) Part B - Vltage Fllwers (1 pints) Include the fllwing plts: 1. PSpice transient f the vltage divider with 1Ω lad and n vltage fllwer. (1 pt) 2. PSpice transient f the vltage divider with 1Ω lad and a vltage fllwer. (1 pt) 3. PSpice transient f the vltage divider with 1Ω lad and a vltage fllwer. (1 pt) 4. PSpice AC sweep f the input impedance fr the vltage fllwer. (2 pt) Answer the fllwing questins: 1. Cmpare the transients f the utput with and withut the buffer circuit in place. What is the functin f the buffer circuit? (2 pt) 2. Why is the fllwer unable t wrk prperly with a small lad resistr? (1 pt) 3. What is the typical value f the input impedance f the vltage fllwer when it is wrking prperly at lw frequencies? (1 pt) 4. Is the magnitude f the input impedance f the vltage fllwer high enugh at high frequencies fr it t wrk effectively? (1 pt) Part C Integratrs and Differentiatrs (38 pints) Include the fllwing plts: 1. PSpice transient plt f the integratr. (1 pt) 2. AC sweep f amplitude (with three experimental pints marked) and phase (with three experimental pints marked.) The frequency at which the phase gets clse t ideal shuld als be marked. (3 pt) 2. AC sweep plt f the integratr vltage and -Vin/ωRC with the lcatin f fc and the place where the vltage gets clse t ideal indicated. (2 pt) 3. PSpice plts f the integratr with DC surce with slpe and theretical slpe (if any) indicated n plt. One shuld be when C2=1uF and the ther fr C2=.1uF (2 plts) (2 pt) 4. PSpice plt f the ideal integratr (withut feedback resistr) (1 pt) 5. Analg Discvery pictures f yur circuit trace (input vs. utput) at 5Hz, 1kHz and 5kHz. (3 plts) (3 pt) K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

17 6. Analg Discvery pictures f yur integratr input and utput with sine wave, triangular wave and square wave inputs (input vs. utput) (3 plts) (3 pt) 7. Analg Discvery picture f yur differentiatr utput with sine wave, triangular wave and square wave inputs (input vs. utput) (3 plts) (3 pt) Answer the fllwing questins: 1. Using the rules fr analyzing circuits with p-amps, derive the relatinship between V ut and V in fr the integratr circuit. (3 pt) 2. Why is the integratr als called a lw-pass filter? Take the limits f the transfer functin at high and lw frequencies t demnstrate this. (3 pt) 3. What are the features f the AC sweep and transient analysis f an integratr that shw it is wrking mrer-less as expected accrding t the transfer functin? Fr abut what range f frequencies des it act like an inverting amplifier? Fr abut what range f frequencies des it act like an integratr? (3 pt) 4. Cnsider the phase shift and the change in amplitude f the utput in relatin t the input when the circuit is behaving like an integratr. Use the expected change in phase and amplitude (frm the ideal equatin) t demnstrate that the circuit is actually integrating. (3 pt) 5. Why wuld we prefer t use the.1uf capacitr in the feedback lp even thugh the circuit des nt integrate quite as well ver as large a range? (1 pt) 6. What happens when we try t use an ideal integratr? (1 pt) 7. In the hardware implementatin, yu used a square-wave input t demnstrate that the integratr was wrking apprximately crrectly. If it were a perfect integratr, what wuld the utput wavefrm lk like? Is it clse? (3 pt) 8. When we built the differentiatr, what did the utput wavefrm lk like fr the square-wave input? What did the differentiatr circuit utput lk like fr a triangular wave input? If it were a perfect differentiatr, what wuld the utput wavefrm lk like? Is it clse? (3 pt) Part D Using Op-Amps t Add and Subtract Signals (1 pints) Include the fllwing plts: 1. Transient simulatin f the utput f the adder with bth input resistrs set t 1k. (1 pt) 2. Transient simulatin frm PSpice with R2 mdified. (1 pt) Answer the fllwing questins: 1. Demnstrate that the riginal adder circuit (plt D-1) wrks as expected. (3 pt) 2. Demnstrate that the mdified adder circuit (plt D-2) wrks as expected. (3 pt). 3. Give an example f a system (electrical, mechanical, chemical r sme cmbinatin) with negative feedback and an example f a system with psitive feedback. (2 pt) Overall (8 pints) 1. Material shuld be in lgical rder, easy t fllw and cmplete. (6pt) 2. List member respnsibilities. (2 pt) List grup member respnsibilities. Nte that this is a list f respnsibilities, nt a list f what each partner did. It is very imprtant that yu divide the respnsibility fr each aspect f the experiment s that it is clear wh will make sure that it is cmpleted. Respnsibilities include, but are nt limited t, reading the full write up befre the first class; cllecting all infrmatin and writing the reprt; building circuits and cllecting data (i.e. ding the experiment); setting up and running the simulatins; cmparing the thery, experiment and simulatin t develp the practical mdel f whatever system is being addressed, etc. K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

18 Summary/Overview ( t -1 pts) There are tw parts t this sectin, bth f which require revisiting everything dne n this experiment and addressing brad issues. Grading fr this sectin wrks a bit differently in that the verall reprt grade will be reduced if the respnses are nt satisfactry. 1. Applicatin: Identify at least ne applicatin f the cntent addressed in this experiment. That is, find an engineered system, device, prcess that is based, at least in part, n what yu have learned. Yu must identify the fundamental system and then describe at least ne practical applicatin. 2. Engineering Design Prcess: Describe the fundamental math and science (ideal) picture f the system, device, and prcess yu address in part 1 and the key infrmatin yu btained frm experiment and simulatin. Cmpare and cntrast the results frm each f the task areas (math and science, experiment, simulatin) and then generate ne r tw cnclusins fr the practical applicatin. That is, hw des the practical system mdel differ frm the riginal ideal? Nte that 2 is almst dne fr yu in the handut n Integratrs and Differentiatrs, but yu shuld include yur versin f the discussin here. Engineering Design Prcess Ttal: 8 pints fr experiment packet t -1 pints fr Summary/Overview 2 pints fr attendance 1 pints Attendance (2 pssible pints) 2 classes (2 pints), 1 class (1 pints), class ( pints) Minus 5 pints fr each late. N attendance at all = N grade fr this experiment. K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA

19 Experiment 4 Sectin: Reprt Grade: Name Name Checklist w/ Signatures fr Main Cncepts Fr all plts that require a signature belw, yu must explain t the TA r instructr: the purpse f the data (using yur hand-drawn circuit diagram), what infrmatin is cntained in the plt and why yu believe that the plt is crrect. Any member f yur grup can be asked fr the explanatin. PART A: Intrductin t Op-Amp Circuits 1. PSpice transient f inverting amplifier input Amp=2mV bth traces 2. PSpice transient f inverting amplifier input Amp=5V bth traces 3. Analg Discvery picture f inverting amplifier circuit Questin 1-4 PART B: Vltage Fllwers 1. PSpice transient f vltage divider: 1Ω lad and n vltage fllwer 2. PSpice transient f vltage divider: 1Ω lad and a vltage fllwer 3. PSpice transient f vltage divider: 1Ω lad and a vltage fllwer 4. PSpice AC sweep f the input impedance fr the vltage fllwer Questins 1-4 PART C: Integratrs and Differentiatrs 1. PSpice transient plt f the integratr 2. AC sweep f amplitude with markings listed abve 3. AC sweep plt f the integratr vltage with markings listed abve 4. PSpice plts f the integratr with DC surce: Slpe and theretical slpe One shuld be when C2=1uF and C2=.1uF 5. PSpice plt f the ideal integratr 6. IO Bard pictures f yur circuit trace at 5Hz, 1kHz, 5kHz (3 plts) 7. Analg Discvery pictures f yur integratr input and utput with sine wave, triangular wave and square wave inputs (3 plts) Questins 1-8 PART D: Using Op-Amps t Add and Subtract Signals 1. Transient simulatin f the utput f the added bth resistrs 1k 2. Transient simulatin frm PSpice with R2 mdified Questins 1-3 Member Respnsibilities Summary/Overview K.A. Cnnr, S. Bnner, P. Schch Rensselaer Plytechnic Institute Try, New Yrk, USA