LTC1854/LTC1855/LTC Channel, ±10V Input 12-/14-/16-Bit, 100ksps ADC Converters with Shutdown Description. Features.

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1 Features n Single 5V Supply n Sample Rate: ksps n 8-Channel Multiplexer with ±3V Protection n ±V Bipolar Input Range Single Ended or Differential n ±3LSB INL for the LTC856, ±.5LSB INL for the LTC855, ±LSB INL for the LTC854 n Power Dissipation: 4mW (Typ) n SPI/MICROWIRE Compatible Serial I/O n Power Shutdown: Nap and Sleep n SINAD: 87dB (LTC856) n Operates with Internal or External Reference n Internal Synchronized Clock n 28-Pin SSOP Package Applications n Industrial Process Control n Multiplexed Data Acquisition Systems n High Speed Data Acquisition for PCs n Digital Signal Processing LTC854/LTC855/LTC856 8-Channel, ±V Input 2-/4-/6-Bit, ksps ADC Converters with Shutdown Description The LTC 854/LTC855/LTC856 are 8-channel, low power, 2-/4-/6-bit, ksps, analog-to-digital converters (ADCs). These ADCs operate from a single 5V supply and the 8 channel multiplexer can be programmed for single-ended inputs, pairs of differential inputs, or combinations of both. In addition, all channels are fault protected to ±3V. A fault condition on any channel will not affect the conversion result of the selected channel. An onboard precision reference minimizes external components. Power dissipation is 4mW at ksps and lower in two power shutdown modes (27.5mW in Nap mode and 4µW in Sleep mode.) DC specifications include ±3LSB INL for the LTC856, ±.5LSB INL for the LTC855 and ±LSB for the LTC854. The internal clock is trimmed for 5µs maximum conversion time and the sampling rate is guaranteed at ksps. A separate convert start input and data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application khz, 2-Bit/4-/6-Bit Sampling ADC LTC856 Typical INL Curve SOFTWARE-PROGRAMMABLE SINGLE-ENDED OR ERENTIAL INPUTS ±V BIPOLAR INPUT RANGE COM CH CH CH2 CH3 CH4 CH5 CH6 CH7 MUXOUT + MUXOUT ADC + ADC AGND CONVST RD SDI DGND BUSY OV DD DV DD AV DD AGND3 AGND2 REFCOMP V REF LTC854/ LTC855/ LTC856 µf µp CONTROL LINES.µF µf µf µf.µf.µf µf 3V TO 5V 5V 5V.µF 2.5V INL (LSB) CODE G af

2 LTC854/LTC855/LTC856 Absolute Maximum Ratings (Notes, 2) Supply Voltage (OV DD = DV DD = AV DD = V DD )... 6V Ground Voltage Difference DGND, AGND, AGND2, AGND3... ±.3V Analog Input Voltage ADC +, ADC (Note 3)...(AGND.3V) to (AV DD +.3V) CH-CH7, COM... ±3V Digital Input Voltage (Note 4)...(DGND.3V) to V Digital Output Voltage...(DGND.3V) to (DV DD +.3V) Power Dissipation... 5mW Operating Temperature Range LTC854C/LTC855C/LTC856C... C to 7 C LTC854I/LTC855I/LTC856I... 4 C to 85 C Storage Temperature Range C to 5 C Lead Temperature (Soldering, sec)... 3 C Package/order information LTC854CG LTC854IG COM CH 2 CH 3 CH2 4 CH3 5 CH4 6 CH5 7 CH6 8 CH7 9 MUXOUT + MUXOUT ADC + 2 ADC 3 AGND 4 TOP VIEW 28 CONVST 27 RD SDI 24 DGND BUSY 2 OV DD 2 DV DD 9 AV DD 8 AGND3 7 AGND2 6 REFCOMP 5 V REF G PACKAGE 28-LEAD PLASTIC SSOP T JMAX = 25 C, θ JA = 6 C/W EXPOSED PAD (PIN #) IS GND, MUST BE SOLDERED TO PCB ORDER PART NUMBER LTC855CG LTC855IG LTC856CG LTC856IG Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: Consult LTC Marketing for parts specified with wider operating temperature ranges. converter and multiplexer characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. MUXOUT connected to ADC inputs. (Notes 5, 6) LTC854 LTC855 LTC856 PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Resolution l Bits No Missing Codes l Bits Transition Noise.6.25 LSB RMS Integral Linearity Error (Note 7) l ± ±.5 ±3 LSB Differential Linearity Error l LSB Bipolar Zero Error (Note 8) l ±5 ±8 ±23 LSB Bipolar Zero Error Drift ±. ±. ±. ppm/ C Bipolar Zero Error Match 3 4 LSB Bipolar Full-Scale Error External Reference (Note ) Internal Reference (Note ) Bipolar Full-Scale Error Drift External Reference Internal Reference 2 l ±.34 ±.45 ±2.5 ±7 ±2.5 ±7 ±.4 ±.4 ±2.5 ±7 ±. ±.4 % % ppm/ C ppm/ C Bipolar Full-Scale Error Match 5 5 LSB Input Common Mode Range l ± ±+ ± V Input Common Mode Rejection Ratio db 85456fa

3 LTC854/LTC855/LTC856 analog input The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS Analog Input Range CH to CH7, COM ± V ADC +, ADC (Note 3) ADC ±2.48 V Impedance CH to CH7, COM 3 kω MUXOUT +, MUXOUT 5 kω Capacitance CH to CH7, COM 5 pf Sample Mode ADC +, ADC 2 pf Hold Mode ADC +, ADC 4 pf Input Leakage Current ADC +, ADC, CONVST = Low l ± µa dynamic accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. MUXOUT connected to ADC inputs. (Note 5) SYMBOL PARAMETER CONDITIONS LTC854 LTC855 LTC856 MIN TYP MAX MIN TYP MAX MIN TYP MAX S/(N + D) Signal-to-(Noise + Distortion) Ratio khz Input Signal db THD Total Harmonic Distortion khz Input Signal First Five Harmonics UNITS 2 95 db Peak Harmonic or Spurious Noise khz Input Signal db Channel-to-Channel Isolation khz Input Signal db 3dB Input Bandwidth MHz Aperture Delay ns Aperture Jitter ps Transient Response Full-Scale Step (Note 9) µs Overvoltage Recovery (Note 2) ns af 3

4 LTC854/LTC855/LTC856 internal reference Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS V REF Output Voltage I OUT = l V V REF Output Temperature Coefficient I OUT = ± ppm/ C V REF Output Impedance.mA I OUT.mA 8 kω V REFCOMP Output Voltage I OUT = 4.96 V digital inputs and digital outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IH High Level Input Voltage V DD = 5.25V l 2.4 V V IL Low Level Input Voltage V DD = 4.75V l.8 V I IN Digital Input Current V IN = V to V DD l ± µa C IN Digital Input Capacitance 5 pf V OH High Level Output Voltage V DD = 4.75V, I O = µa, OV DD = V DD V DD = 4.75V, I O = 2µA, OV DD = V DD l 4 V OL Low Level Output Voltage V DD = 4.75V, I O = 6µA, OV DD = V DD V DD = 4.75V, I O =.6mA, OV DD = V DD l 4.74 V V.5..4 I OZ Hi-Z Output Leakage V OUT = V to V DD, RD = High l ± µa C OZ Hi-Z Output Capacitance RD = High 5 pf I SOURCE Output Source Current V OUT = V ma I SINK Output Sink Current V OUT = V DD ma V V power requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS Positive Supply Voltage (Notes 9 and ) V Positive Supply Current Nap Mode Sleep Mode Power Dissipation Nap Mode Sleep Mode CONVST = V or 5V l ma ma µa CONVST = V or 5V mw mw µw fa

5 timing Characteristics LTC854/LTC855/LTC856 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25 C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f SAMPLE(MAX) Maximum Sampling Frequency Through CH to CH7 Inputs l khz Through ADC +, ADC Only 66 khz t CONV Conversion Time l 4 5 µs t ACQ Acquisition Time Through CH to CH7 Inputs l 4 µs Through ADC +, ADC Only µs f Frequency (Note 3) l 2 MHz t r Rise Time See Test Circuits 6 ns t f Fall Time See Test Circuits 6 ns t CONVST High Time l 4 ns t 2 CONVST to BUSY Delay C L = 25pF, See Test Circuits l 5 3 ns t 3 Period l 5 ns t 4 High l ns t 5 Low l ns t 6 Delay Time, to Valid C L = 25pF, See Test Circuits l ns t 7 Time from Previous Data Remains C L = 25pF, See Test Circuits l 5 2 ns Valid After t 8 Valid After RD C L = 25pF, See Test Circuits l 3 ns t 9 RD to Setup Time l 2 ns t SDI Setup Time Before l ns t SDI Hold Time After l 7 ns t 2 Valid Before BUSY RD = Low, C L = 25pF, See Test Circuits l 5 2 ns t 3 Bus Relinquish Time See Test Circuits l 3 ns Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with DGND, AGND, AGND2 and AGND3 wired together unless otherwise noted. Note 3: When these pin voltages are taken below ground or above AV DD = DV DD = OV DD = V DD, they will be clamped by internal diodes. This product can handle currents of greater than ma below ground or above V DD without latchup. Note 4: When these pin voltages are taken below ground they will be clamped by internal diodes. This product can handle currents of greater than ma below ground without latchup. These pins are not clamped to V DD. Note 5: V DD = 5V, f SAMPLE = khz, t r = t f = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended analog MUX input with respect to ground or ADC + with respect to ADC tied to ground. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual end points of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar zero error is the offset voltage measured from.5lsb when the output code flickers between and for the LTC856, between and for the LTC855 and between and for the LTC854. Note 9: Guaranteed by design, not subject to test. Note : Recommended operating conditions. Note : Full-scale bipolar error is the worst case of FS or +FS untrimmed deviation from ideal first and last code transitions, divided by the full-scale range, and includes the effect of offset error. Note 2: Recovers to specified performance after (2 FS) input overvoltage. Note 3: t 6 of 45ns maximum allows f up to MHz for rising capture with 5% duty cycle and f up to 2MHz for falling capture (with 5ns setup time for the receiving logic) af 5

6 LTC854/LTC855/LTC856 Typical Performance Characteristics INL (LSB) LTC856 Typical INL Curve CODE DNL (LSB) LTC856 Typical DNL Curve CODE MAGNITUDE (db) LTC856 Nonaveraged 496-Point FFT Plot f SAMPLE = khz f IN = khz 2 SINAD = 87dB 3 THD = db FREQUENCY (khz) G G G3 INL (LSB) LTC855 Typical INL Curve CODE 89 DNL (LSB) LTC855 Typical DNL Curve CODE 89 MAGNITUDE (db) LTC855 Nonaveraged 496-Point FFT Plot f SAMPLE = khz f IN = khz 2 SINAD = 83dB 3 THD = 95dB FREQUENCY (khz) G G G6 INL (LSB) LTC854 Typical INL Curve 24 CODE G7 DNL (LSB) LTC854 Typical DNL Curve 24 CODE G8 MAGNITUDE (db) LTC854 Nonaveraged 496-Point FFT Plot FREQUENCY (khz) f SAMPLE = khz f IN = khz SINAD = 73.6dB THD = 2dB G fa

7 Typical Performance Characteristics 9 LTC856 SINAD vs Input Frequency 7 LTC856 Total Harmonic Distortion vs Input Frequency LTC854/LTC855/LTC856. LTC856 Channel-to-Channel Offset Error Matching vs Temperature SINAD (db) TOTAL HARMONIC DISTORTION (db) 8 9 CHANNEL-TO-CHANNEL OFFSET ERROR MATCHING (LSBs) INPUT FREQUENCY (khz) INPUT FREQUENCY (khz) TEMPERATURE ( C) LTC855 SINAD vs Input Frequency G 6 LTC855 Total Harmonic Distortion vs Input Frequency G.5 LTC855 Channel-to-Channel Offset Error Matching vs Temperature G2 SINAD (db) TOTAL HARMONIC DISTORTION (db) CHANNEL-TO-CHANNEL OFFSET ERROR MATCHING (LSBs) INPUT FREQUENCY (khz) INPUT FREQUENCY (khz) TEMPERATURE ( C) 75 SINAD (db) LTC854 SINAD vs Input Frequency G3 INPUT FREQUENCY (khz) G6 TOTAL HARMONIC DISTORTION (db) LTC854 Total Harmonic Distortion vs Input Frequency INPUT FREQUENCY (khz) G G7 CHANNEL-TO-CHANNEL OFFSET ERROR MATCHING (LSB) LTC854 Channel-to-Channel Offset Error Matching vs Temperature TEMPERATURE ( C) G G af 7

8 LTC854/LTC855/LTC856 Typical Performance Characteristics CHANNEL-TO-CHANNEL GAIN ERROR MATCHING (LSBs) LTC856 Channel-to-Channel Gain Error Matching vs Temperature TEMPERATURE ( C) 75 CHANNEL-TO-CHANNEL GAIN ERROR MATCHING (LSBs) LTC855 Channel-to-Channel Gain Error Matching vs Temperature TEMPERATURE ( C) 75 CHANNEL-TO-CHANNEL GAIN ERROR MATCHING (LSB) LTC854 Channel-to-Channel Gain Error Matching vs Temperature TEMPERATURE ( C) G G G2 INTERNAL REFERENCE VOLTAGE (V) Internal Reference Voltage vs Temperature CHANGE IN REFCOMP VOLTAGE (V) Change in REFCOMP Voltage vs Load Current POWER SUPPLY FEEDTHROUGH (db) LTC856 Power Supply Feedthrough vs Ripple Frequency f SAMPLE = khz V RIPPLE = 6mV TEMPERATURE ( C) LOAD CURRENT (ma) 8 k k k M RIPPLE FREQUENCY (Hz) G G G24 Supply Current vs Supply Voltage 9. fsample = khz Supply Current vs Temperature 9. f SAMPLE = khz SUPPLY CURRENT (ma) POSITIVE SUPPLY CURRENT (ma) SUPPLY VOLTAGE (V) TEMPERATURE ( C) G G fa

9 LTC854/LTC855/LTC856 Pin Functions COM (Pin ): Common Input. This is the negative reference point for all single-ended inputs. It must be free of noise and is usually connected to the analog ground plane. CH (Pin 2): Analog MUX Input. CH (Pin 3): Analog MUX Input. CH2 (Pin 4): Analog MUX Input. CH3 (Pin 5): Analog MUX Input. CH4 (Pin 6): Analog MUX Input. CH5 (Pin 7): Analog MUX Input. CH6 (Pin 8): Analog MUX Input. CH7 (Pin 9): Analog MUX Input. MUXOUT + (Pin ): Positive MUX Output. Output of the analog multiplexer. Connect to ADC + for normal operation. MUXOUT (Pin ): Negative MUX Output. Output of the analog multiplexer. Connect to ADC for normal operation. ADC + (Pin 2): Positive Analog Input to the Analog-to- Digital Converter. ADC (Pin 3): Negative Analog Input to the Analog-to- Digital Converter. AGND (Pin 4): Analog Ground. V REF (Pin 5): 2.5V Reference Output. Bypass to analog ground with a µf tantalum capacitor. REFCOMP (Pin 6): Reference Buffer Output. Bypass to analog ground with a µf tantalum and a.µf ceramic capacitor. Nominal output voltage is 4.96V. AGND2 (Pin 7): Analog Ground. AGND3 (Pin 8): Analog Ground. This is the substrate connection. AV DD (Pin 9): 5V Analog Supply. Bypass to analog ground with a.µf ceramic and a µf tantalum capacitor. DV DD (Pin 2): 5V Digital Supply. Bypass to digital ground with a.µf ceramic and a µf tantalum capacitor. OV DD (Pin 2): Positive Supply for the Digital Output Buffers (3V to 5V). Bypass to digital ground with a.µf ceramic and a µf tantalum capacitor. BUSY (Pin 22): Output shows converter status. It is low when a conversion is in progress. (Pin 23): Serial Data Output af 9

10 LTC854/LTC855/LTC856 pin functions DGND (Pin 24): Digital Ground. SDI (Pin 25): Serial Data Input. (Pin 26): Serial Data Clock. RD (Pin 27): Read Input. This active low signal enables the digital output pin and enables the serial interface, SDI and are ignored when RD is high. CONVST (Pin 28): Conversion Start. The ADC starts a conversion on CONVST s rising edge. functional block diagram AV DD DV DD 9 2 CH CH 2 3 INPUT MUX MUX ADDRESS INTERNAL CLOCK CONTROL LOGIC CONVST SDI BUSY CH7 COM V REFERENCE 2-/4-/6-BIT SAMPLING ADC 4.96V DATA OUT SERIAL I/O RD OV DD 8k.6384X MUXOUT MUXOUT + ADC + ADC AGND V REF REFCOMP AGND2 AGND3 DGND 8545 BD 85456fa

11 test circuits Load Circuits for Access Timing 5V k LTC854/LTC855/LTC856 Load Circuits for Output Float Delay 5V k DN DN DN DN k 25pF 25pF k 25pF 25pF (A) Hi-Z TO V OH AND V OL TO V OH (B) Hi-Z TO V OL AND V OH TO V OL (A) V OH TO Hi-Z (B) V OL TO Hi-Z 8545 TC 8545 TC2 TIMING Diagrams t 2 (CONVST to BUSY Delay) t 2 t (For Short Pulse Mode) CONVST 2.4V t CONVST 5% 5% BUSY.4V 8545 TD 8545 TD2 t 6 (Delay Time, to Valid) t 7 (Time from Previous Data Remains Valid After ) t3, t 4, t 5 ( Timing) t 6 t 7 t 4 t 5.4V t TD3 2.4V.4V 8545 TD4 t 8 ( Valid After RD ) t 9 (RD to Setup Time) t 8 t 9 RD.4V RD.4V Hi-Z 2.4V.4V 2.4V 8545 TD TD af

12 LTC854/LTC855/LTC856 timing diagrams t (SDI Setup Time Before ) t t (SDI Hold Time After ) t 2.4V 2.4V SDI 2.4V.4V SDI 2.4V.4V 8545 TD TD8 t 2 ( Valid Before BUSY, RD = ) t 3 (BUS Relinquish Time) t 2 t 3 BUSY 2.4V RD 2.4V 2.4V B5 9% Hi-Z % 8545 TD 8545 TD fa

13 Applications Information Overview The LTC854/LTC855/LTC856 are innovative, multichannel ADCs. The on-chip resistors provide attenuation and offset for each channel. The precisely trimmed attenuators ensure an accurate input range. Because they precede the multiplexer, errors due to multiplexer on-resistance are eliminated. The input word selects the single ended or differential inputs for each channel or pair of channels. Overrange protection is provided for unselected channels. An overrange condition on an unused channel will not affect the conversion result on the selected channel. Conversion Details The LTC854/LTC855/LTC856 use a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 2-/4-/6-bit serial output respectively. The ADCs are complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) The analog signals applied at the MUX input channels are rescaled by the resistor divider network formed by R, R2 and R3 as shown below. The rescaled signals appear on the MUXOUT (Pins, ) which are also connected to the ADC inputs (Pins 2, 3) under normal operation. MUX INPUT R 25k REFCOMP R3 k R2 7k CH SEL MUXOUT AI LTC854/LTC855/LTC856 Before starting a conversion, an 8-bit data word is clocked into the SDI input on the first eight rising edges to select the MUX address and power down mode. The ADC enters acquisition mode on the falling edge of the sixth clock in the 8-bit data word and ends on the rising edge of the CONVST signal which also starts a conversion (see Figure 7). A minimum time of 4µs will provide enough time for the sample-and-hold capacitors to acquire the analog signal. Once a conversion cycle has begun, it cannot be restarted. During the conversion, the internal differential 2-/4-/6- bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). The input is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by a high speed comparator. At the end of a conversion, the DAC output balances the analog input (ADC + ADC ). The SAR contents (a 2-/4-/6-bit data word) which represents the difference of ADC + and ADC are loaded into the 2-/4-/6-bit shift register. Driving the Analog Inputs The input range for the LTC854/LTC855/LTC856 is ±V and the MUX inputs are overvoltage protected to ±3V. The input impedance is typically 3kΩ; therefore, it should be driven with a low impedance source. Wideband noise coupling into the input can be minimized by placing a 3pF capacitor at the input as shown in Figure 2. An NPO-type capacitor gives the lowest distortion. Place the capacitor as close to the device input pin as possible. If an amplifier is to be used to drive the input, care should be taken to select an amplifier with adequate accuracy, linearity and noise for the application. The following list is a summary of the op amps that are suitable for driving the LTC854/LTC855/LTC856. More detailed information is available in the Linear Technology data books and online at LT 7: Low noise precision amplifier. 2.7mA supply current ±5V to ±5V supplies. Gain bandwidth product 8MHz. DC applications af 3

14 LTC854/LTC855/LTC856 applications information AV DD DV DD CH MUX ADDRESS CONVST CH INPUT MUX INTERNAL CLOCK CONTROL LOGIC SDI BUSY CH7 COM + 2-/4-/6-BIT SAMPLING ADC DATA OUT SERIAL I/O RD OV DD 2.5V REFERENCE 4.96V 8k.6384X MUXOUT MUXOUT + ADC + ADC AGND V REF REFCOMP AGND2 AGND3 DGND 8545 F Figure. LTC854/LTC855/LTC856 Simplified Equivalent Circuit LT227: 4MHz video current feedback amplifier. ma supply current. ±5V to ±5V supplies. Low noise and low distortion. LT468/LT469: Single and dual 9MHz, 6-bit accurate op amp. Good AC/DC specs. ±5V to ±5V supplies. LT677: Single, low noise op amp. Rail-to-rail input and output. Up to ±5V supplies. 4 A IN + A IN 3pF CH CH MUXOUT + MUXOUT ADC + ADC 8545 F2 Figure 2. Analog Input Filtering LT792: Single, low noise JFET input op amp, ±5V supplies. LT793: Single, low noise JFET input op amp, pa bias current, ±5V supplies. LT88/LT882: Dual and quad, 2pA bias current, railto-rail output op amps. Up to ±5V supplies. LT844/LT885: Dual and quad, 4pA bias current, rail-to-rail output op amps. Up to ±5V supplies. Faster response and settling time. Internal Voltage Reference The LTC854/LTC855/LTC856 have an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.5V. The full-scale range of the LTC854/LTC855/LTC856 is equal to ±V. The output of the reference is connected to the input of a gain of.6384x buffer through an 8k resistor (see Figure 3). The input to the buffer or the output of the reference 85456fa

15 LTC854/LTC855/LTC856 Applications Information is available at V REF (Pin 5). The internal reference can be overdriven with an external reference if more accuracy is needed. The buffer output drives the internal DAC and is available at REFCOMP (Pin 6). The REFCOMP pin can be used to drive a steady DC load of less than 2mA. Driving an AC load is not recommended because it can cause the performance of the converter to degrade. 4.96V Figure 3. Internal or External Reference Source For minimum code transition noise the V REF pin and the REFCOMP pin should each be decoupled with a capacitor to filter wideband noise from the reference and the buffer. OUTPUT CODE 2.5V.µF µf V REF 8k.6384X BUFFER 6 REFCOMP µf 2.5V REFERENCE 2-/4-/6-BIT CAPACITIVE DAC 8545 F3 FULL SCALE AND OFFSET Figure 4 shows the ideal input/output characteristics for the LTC856. The code transitions occur midway between successive integer LSB values (i.e., FS+.5LSB, FS+.5LSB, FS+2.5LSB, FS.5LSB, FS.5LSB). The output is two s complement binary with: LSB FS ( FS) = = 2V = 35.2µV In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero during a calibration sequence. Offset error must be adjusted before full-scale error. Zero offset is achieved by adjusting the offset applied to the input. For single-ended inputs, this offset should be applied to the COM pin. For differential inputs, the input is dictated by the MUX address. For zero offset error, apply.5lsb to the + input and adjust the offset at the input until the output code flickers between and for the LTC856, between and for the LTC855 and between and for the LTC854. For full-scale adjustment, an input voltage of FS.5LSBs should be applied to the + input and the appropriate reference adjusted until the output code flickers between and for the LTC856, between and for the LTC855 and between and for the LTC854. These adjustments as well as the factory trims affect all channels. The channel-to-channel offset and gain error matching are guaranteed by design to meet the specifications in the Converter Characteristics table (FS LSB) INPUT VOLTAGE (V) FS LSB F4 Figure 4. Bipolar Transfer Characteristics af 5

16 LTC854/LTC855/LTC856 applications information DC Performance One way of measuring the transition noise associated with a high resolution ADC is to use a technique where a DC signal is applied to the input of the MUX and the resulting output codes are collected over a large number of conversions. For example in Figure 5 the distribution of output code is shown for a DC input that has been digitized 496 times. The distribution is Gaussian and the RMS code transition is about LSB for the LTC856. Digital Interface Internal Clock The ADC has an internal clock that is trimmed to achieve a typical conversion time of 4µs. No external adjustments are required and, with the maximum acquisition time of 4µs, throughput performance of ksps is assured. 3V Input/Output Compatible The LTC854/LTC855/LTC856 operate on a 5V supply, which makes the devices easy to interface to 5V digital systems. These devices can also interface to 3V digital systems: the digital input pins (, SDI, CONVST and RD) of the LTC854/LTC855/LTC856 recognize 3V or 5V inputs. The LTC854/LTC855/LTC856 have a dedicated output supply pin (OV DD ) that controls the output swings of the digital output pins (, BUSY) and allows the part to interface to either 3V or 5V digital systems. The output is two s complement. Timing and Control Conversion start and data read are controlled by two digital inputs: CONVST and RD. To start a conversion and put the sample-and-hold into the hold mode bring CONVST high for at least 4ns. Once initiated it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output, which goes low while the conversion is in progress. Figures 6a and 6b show two different modes of operation for the LTC856. For the 2-bit LTC854 and 4-bit LTC855, the last four and two bits of the will output zeros, respectively. In mode (Figure 6a), RD is tied low. The rising edge of CONVST starts the conversion. The data outputs are always enabled. The MSB of the data output is available after the conversion. In mode 2 (Figure 6b), CONVST and RD are tied together. The rising edge of the CONVST signal starts the conversion. Data outputs are in three-state at this time. When the conversion is complete (BUSY goes high), CONVST and RD go low to enable the data output for the previous conversion COUNT CODE F5 Figure 5. LTC856 Histogram for 496 Conversions fa

17 Applications Information LTC854/LTC855/LTC856 RD = t 3 t5 t SDI DON T CARE t t ODD/ SHIFT CONFIGURATION WORD IN tacq X X NAP SLEEP DON T CARE t7 t 6 ODD/ X X NAP SLEEP DON T CARE SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN B5 (MSB) B4 B3 B2 B B B9 B8 B B B5 (MSB) B4 B3 B2 B B B9 B8 B B t2 t t2 CONVST t2 BUSY t CONV Figure 6a. Mode for the LTC856*. CONVST Starts a Conversion, Data Output is Always Enabled (RD = ) t9 t3 t3 CONVST = RD t5 t SDI DON T CARE t t ODD/ SHIFT CONFIGURATION WORD IN t ACQ X X NAP SLEEP DON T CARE t7 t6 ODD/ X X NAP SLEEP DON T CARE SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN Hi-Z B5 (MSB) B4 B3 B2 B B B9 B8 Hi-Z B B B5 (MSB) B4 B3 B2 B B B9 B8 B B t 8 t 2 BUSY tconv Figure 6b. Mode 2 for the LTC856*. CONVST and RD Tied Together. CONVST Starts a Conversion, Data is Read by RD t9 t3 t 3 RD t 5 t SDI DON T CARE t t ODD/ SHIFT CONFIGURATION WORD IN tacq X X NAP SLEEP DON T CARE t7 t 6 ODD/ X X NAP SLEEP DON T CARE SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN Hi-Z B5 (MSB) B4 B3 B2 B B B9 B8 Hi-Z B B B5 (MSB) B4 B3 B2 B B B9 B8 B B CONVST t8 t t2 BUSY t CONV *For the 2-bit LTC854 and the LTC855 the last four and two bits of the will output zeros, respectively. Figure 7. Operating Sequence for the LTC856* 8545 F6a Hi-Z F6b Hi-Z F af 7

18 LTC854/LTC855/LTC856 applications information Serial DATA INPUT (sdi) Interface The LTC854/LTC855/LTC856 communicate with microprocessors and other external circuitry via a synchronous, full duplex, 3 wire serial interface (see Figure 7). The shift clock () synchronizes the data transfer with each bit being transmitted on the falling edge and captured on the rising edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). An 8-bit input word is shifted into the SDI input which configures the LTC854/LTC855/LTC856 for the next conversion. Simultaneously, the result of the previous conversion is output on the line. At the end of the data exchange the requested conversion begins by applying a rising edge on CONVST. After t CONV, the conversion is complete and the results will be available on the next data transfer cycle. As shown below, the result of a conversion is delayed by one conversion from the input word requesting it. SDI SDI WORD WORD DATA TRANSFER t CONV A/D CONVERSION SDI WORD 2 WORD DATA TRANSFER t CONV A/D CONVERSION SDI WORD 3 WORD AI2 Input Data Word The LTC854/LTC855/LTC856 8-bit data word is clocked into the SDI input on the first eight rising edges. Further inputs on the SDI pin are then ignored until the next conversion. The eight bits of the input word are defined as follows: ODD DON'T CARE DON'T CARE NAP SLEEP MUX ADDRESS POWER DOWN ION Table. Multiplexer Channel Selection MUX ADDRESS ERENTIAL CHANNEL ION MUX ADDRESS SINGLE-ENDED CHANNEL ION ODD ODD AI COM Differential 8 Single-Ended Combinations of Differential and Single-Ended Changing the MUX Assignment On the Fly CHANNEL, 2,3 4,5 6,7 { { { { CHANNEL ( ) + (+) + ( ) (+) + ( ) (+) + ( ) (+) COM ( ) CHANNEL, { ,3 { 4,5{ COM ( ) 6,7 { + 4,5 { COM (UNUSED) ST CONVERSION COM ( ) 2ND CONVERSION 8545 F8 8 Figure 8. Examples of Multiplexer Options on the LTC854/LTC855/LTC fa

19 LTC854/LTC855/LTC856 Applications Information MUX Address The first four bits of the input word assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the + and signs in the selected row of Table. Note that in differential mode ( = ) measurements are limited to four adjacent input pairs with either polarity. In single-ended mode, all input channels are measured with respect to COM. Both the + and inputs are sampled simultaneously so common mode noise is rejected. Bits 5 and 6 of the input words are Don t Care bits. Power Down Selection (NAP, SLEEP) The last two bits of the input word (Nap and Sleep) determine the power shutdown mode of the LTC854/LTC855/ LTC856. See Table 2. Nap mode is selected when Nap = and Sleep =. The previous conversion result will be clocked out and a conversion will occur before entering the Nap mode. The Nap mode starts at the end of the conversion which is indicated by the rising edge of the BUSY signal. Nap mode lasts until the falling edge of the 2nd (see Figure 9). Automatic nap will be achieved if Nap = is selected each time an input word is written to the ADC. Table 2. Power Down Selection NAP SLEEP POWER DOWN MODE Power On Nap X Sleep Sleep mode will occur when Sleep = is selected, regardless of the selection of the Nap input. The previous conversion result can be clocked out and the Sleep mode will start on the falling edge of the last (6th). Notice that the CONVST should stay either high or low in sleep mode (see Figure ). To wake up from the sleep mode, apply a rising edge on the CONVST signal and then apply Sleep = on the next SDI word and the part will wake up on the falling edge of the last (6th) (see Figure ). In Sleep mode, all bias currents are shut down and only the power on reset circuit and leakage currents (about µa) remain. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 6). The wake-up time is typically 4ms with the recommended µf capacitor connected on the REFCOMP pin. Dynamic Performance FFT (Fast Fourier Transform) test techniques are used to test the ADC s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC s spectral content can be examined for frequencies outside the fundamental. Figure 2 shows a typical LTC856 FFT plot which yields a SINAD of 87dB and THD of db af 9

20 LTC854/LTC855/LTC856 applications information RD SDI DON T CARE ODD/ X X NAP = SLEEP = DON T CARE ODD/ X X NAP SLEEP DON T CARE Hi-Z SHIFT CONFIGURATION WORD IN B5 (MSB) B4 B3 B2 B B B9 B8 B B Hi-Z SHIFT A/D RESULT OUT FROM PREVIOUS CONVERSION AND NEW CONFIGURATION WORD IN B5 MSB B4 B3 B2 B B B9 B8 B B Hi-Z CONVST BUSY t ACQ t CONV NAP tacq 8545 F9 Figure 9. Nap Mode Operation for the LTC856* RD SDI DON T CARE ODD/ X X NAP SLEEP = DON T CARE SHIFT SLEEP CONFIGURATION WORD IN B5 (MSB) B4 B3 B2 B B B9 B8 B B A/D RESULT FROM PREVIOUS CONVERSION CONVST CONVST SHOULD STAY EITHER HIGH OR LOW IN SLEEP MODE t CONV BUSY SLEEP 8545 F Figure. Sleep Mode Operation for the LTC856* RD SDI DON T CARE ODD/ X X NAP SLEEP = DON T CARE ODD/ X X NAP SLEEP DON T CARE SHIFT WAKE-UP CONFIGURATION WORD IN SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN B5 (MSB) B4 B3 B2 B B B9 B8 B B B5 (MSB) B4 B3 B2 B B B9 B8 B B A/D RESULT NOT VALID CONVST t CONV t CONV BUSY *For the 2-bit LTC854 and the LTC855 the last four and two bits of the will output zeros, respectively. SLEEP WAKE-UP TIME READY Figure. Wake Up from Sleep Mode for the LTC856* 8545 F fa

21 Applications Information Signal-to-Noise AND DISTORTION Ratio The Signal-to-Noise and Distortion Ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 2 shows a typical SINAD of 87dB with a khz sampling rate and a khz input. Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 2log V V V V N 2 where V is the RMS amplitude of the fundamental frequency and V 2 through V N are the amplitudes of the second through Nth harmonics. V LTC854/LTC855/LTC856 Board Layout, Power Supplies and Decoupling Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC854/LTC855/LTC856, a printed circuit board is required. Layout for the printed circuit board should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by AGND. In applications where the MUX is connected to the ADC, it is possible to get noise coupling into the ADC from the trace connecting the MUXOUT to the ADC. Therefore, reducing the length of the traces connecting the MUXOUT pins (Pins, ) to the ADC pins (Pins 2, 3) can minimize the problem. The unused MUX inputs should be grounded to prevent noise coupling into the inputs. Figure 3 shows the power supply grounding that will help obtain the best performance from the 2-bit/4-bit/6-bit ADCs. Pay particular attention to the design of the analog and digital ground planes. The DGND pin of the LTC854/ MAGNITUDE (db) f SAMPLE = khz f IN = khz 2 SINAD = 87dB 3 THD = db FREQUENCY (khz) F2 Figure 2. LTC856 Nonaveraged 496 Point FFT Plot af 2

22 LTC854/LTC855/LTC856 applications information LTC855/LTC856 can be tied to the analog ground plane. Placing the bypass capacitor as close as possible to the power supply pins, the reference and reference buffer output is very important. Low impedance common returns for these bypass capacitors are essential to low noise operation of the ADC, and the foil width for these tracks should be as wide as possible. Also, since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedance as much as possible. The digital output latches and the onboard sampling clock have been placed on the digital ground plane. The two ground planes are tied together at the ADC through a wide, low inductance path. + LTC854/ LTC855/ CH LTC856 CH MUXOUT CH2 + CH3 CH4 MUXOUT CH5 CH6 CH7 COM 2 3 ADC + LTC854/LTC855/LTC856 DIGITAL SYSTEM ADC V REF REFCOMP AGND AV DD DV DD DGND OV DD 5 6 4, 7, µf µf µf µf µf ANALOG GROUND PLANE DIGITAL GROUND PLANE 8545 F3 Figure 3. Power Supply Grounding Practice fa

23 Package Description G Package 28-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # ) LTC854/LTC855/LTC ± * (.39.43) ( ).42 ±.3.65 BSC RECOMMENDED SOLDER PAD LAYOUT ** (.97.22) (.79) MAX (.35.) (.22.37) NOTE:. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE * DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.52mm (.6") PER SIDE ** DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED.254mm (.") PER SIDE.65 (.256) BSC (.9.5) TYP.5 (.2) MIN G28 SSOP 24 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights af 23

24 LTC854/LTC855/LTC856 Typical Application 5V µf.µf 5V µf.µf 9 2 AV DD DV DD COM MUX ADDRESS CONVST 28 SINGLE-ENDED OR ERENTIAL CHANNEL ION (SEE TABLE ) INPUT RANGE: ±V 2 CH 3 CH 9 CH7 INPUT MUX + 2-/4-/6-BIT SAMPLING ADC INTERNAL CLOCK DATA OUT CONTROL LOGIC SERIAL I/O SDI 25 BUSY RD 27 OV DD 2 µf 8-BIT SERIAL DATA INPUT 6 SHIFT CLOCK CYCLES.µF 3V TO 5V 2.5V REFERENCE 4.96V 23 6-BIT SERIAL DATA OUT 8k.6384X AGND MUXOUT MUXOUT + ADC + ADC V REF REFCOMP AGND2 AGND3 DGND µf µf.µf 8545 TA3 Related Parts PART NUMBER DESCRIPTION COMMENTS Sampling ADCs LTC48 4-Bit, 2ksps, Single 5V or ±5V ADC 5mW, Serial/Parallel I/O LTC64 6-Bit, 333ksps, ±5V ADC 9dB SINAD, 22mW Power Dissipation, Pin Compatible with LTC68 LTC65 6-Bit, ksps, Single 5V ADC ±V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC66 LTC66 6-Bit, 25ksps, Single 5V ADC ±V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC65 LTC68 6-Bit, 5ksps, ±5V ADC 9dB SINAD, 27mW Power Dissipation, Pin Compatible with LTC64 LTC69 6-Bit, 2ksps Serial ADC Configurable Unipolar/Bipolar Input, Up to V Single 5V Supply LTC85/LTC85 -Bit/2-Bit, 8-Channel,.25Msps ADC Programmable MUX and Sequencer, Parallel I/O LTC859/LTC858/ LTC857 6-Bit, 4-Bit, 2-Bit, ksps, SoftSpan ADCs Software-Selectable Spans, Pin Compatible with LTC864/LTC865 6-Bit, -/2-Channel, 25ksps ADC in MSOP Single 5V Supply, 85µA with Autoshutdown LTC864L/LTC865L 3V, 6-Bit, -/2-Channel, 5ksps ADC in MSOP DACs Single 3V Supply, 45µA with Autoshutdown LTC856/LTC855/LTC854 LTC588/LTC589 LTC592 2-/4-/6-Bit, Serial, SoftSpan I OUT DACs Software-Selectable Spans, ±LSB INL/DNL LTC595 6-Bit Serial Multiplying I OUT DAC in SO-8 ±LSB Max INL/DNL, Low Glitch, DAC843 6-Bit Upgrade LTC596 6-Bit Serial Multiplying I OUT DAC ±LSB Max INL/DNL, Low Glitch, AD7543/DAC843 6-Bit Upgrade LTC597 6-Bit Parallel, Multiplying DAC ±LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors LTC65 6-Bit Serial V OUT ±5V DAC Low Power, Low Glitch, 4-Quadrant Multiplication LTC274-6/ LTC274-4/ LTC Bit, 4-Bit, 2-Bit, Serial, Quad SoftSpan V OUT DACs Software-Selectable Spans, ±2LSB INL, ±LSB INL, Force/Sense Output fa LT 47 REV A PRINTED IN USA Linear Technology Corporation 63 McCarthy Blvd., Milpitas, CA (48) FAX: (48) LINEAR TECHNOLOGY CORPORATION 26