Atmel AT97SC3204. Trusted Platform Module LPC Interface SUMMARY DATASHEET. Features. Description

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1 tmel T97S04 Trusted Platform Module LP Interface SUMMRY TSHEET Features Fully compliant to the Trusted omputing Group (TG) Trusted Platform Module (TPM) version. specification ompliant with TG P clientspecific TPM Interface Specification (TIS) version. Singlechip, turnkey solution Hardware asymmetric crypto engine tmel VR RIS microprocessor Internal EEPROM storage for RS keys MHz Low Pin ount (LP) bus for easy P interface Secure hardware and firmware design and chip layout Internal, highquality Random Number Generator (RNG) FIPS 40 compliant NV storage space for 756 bytes of user defined data.v supply voltage 8lead thin TSSOP, 8lead wide TSSOP, or 40pad QFN packages Offered in both commercial (0 to 70 ) and industrial (40 to +85 ) temperature ranges escription The tmel T97S04 is a fully integrated security module designed to be integrated into personal computers and other embedded systems. It implements version. of the Trusted omputing Group (TG) specification for Trusted Platform Modules (TPM). The TPM includes a cryptographic accelerator capable of computing a 048bit RS signature in 00ms and a 04bit RS signature in 40ms. Performance of the SH accelerator is 0μs per 64byte block. The chip communicates with the P through the LP interface. The TPM supports SIRQ (for interrupts) and LKRUN to permit clock stopping for power savings in mobile computers. This is a summary document. The complete document is available under N. For more information, please contact your local tmel sales office.

2 . Pin onfigurations and Pinouts Table. Pin onfigurations Pin name SBV LRESET# L0 L L L LLK LFRME# LKRUN# LPP# SERIRQ GPIOExpress00 TestI TestBI N Function.V Supply Voltage Standby.V Supply Voltage Ground PI Reset Input ctive Low LP ommand, ddress, ata Line Input/Output LP ommand, ddress, ata Line Input/Output LP ommand, ddress, ata Line Input/Output LP ommand, ddress, ata Line Input/Output MHz PI lock Input LP FRME Input PI lock Run Input/Output LP Powerown Input Serialized Interrupt Request Input/Output GPIO assigned to TPM_NV_INEX_GPIO_00 Test Input (isabled) Test Input (isabled) tmel Test Pin No onnect Not Bounded Out Table. Pinouts 8pin TSSOP 4.4mm x 9.7mm Body 0.65mm Pitch 40pin QFN 6.0mm x 6.0mm Body 0.50mm Pitch 8pin TSSOP 6.mm x 9.7mm Body 0.65mm Pitch LPP# SERIRQ SBV GPIOExpress00 N TestI TestBI LPP# SERIRQ L0 V L LFRME# LLK L L LRESET# LKRUN# SBV GPIOExpress00 N TestI TestBI LKRUN# LRESET# L0 V L LFRME# LLK L L tmel T97S04 LP Interface [SUMMRY TSHEET]

3 . Block iagram ROM Program EEPROM Program MHz LP Interface VR 8bit RIS PU SRM GPIOExpress00 GPIO EEPROM ata RNG RYPTO Engine Timer Physical Security ircuitry The TPM includes a hardware random number generator, including a FIPSapproved Pseudo Random Number Generator that is used for key generation and TG protocol functions. The RNG is also available to the system to generate random numbers that may be needed during normal operation. The chip uses a dynamic internal memory management scheme to store multiple RS keys. Other than the standard TG commands (TPM_FlushSpecific, TPM_Loadkey), no system intervention is required to manage this internal key cache. The TPM is offered to OEM and OM manufacturers as a turnkey solution, including the firmware integrated on the chip. In addition, tmel provides the necessary device driver software for integration into certain operating systems, along with BIOS drivers. tmel will also provide manufacturing support software for use by OEMs and OMs during initialization and verification of the TPM during board assembly. Full documentation for TG primitives can be found in the TG TPM Main Specification, Parts to, on the TG Web site located at TPM features specific to P lient platforms are specified in the TG P lient Specific TPM Interface Specification, Version., also available on the TG web site. Implementation guidance for bit P platforms is outlined in the TG P lient Specific Implementation Specification for onventional BIOS for TG Version., also available on the TG website. tmel T97S04 LP Interface [SUMMRY TSHEET]

4 . Ordering Information tmel Ordering ode Package Operating Range T97S04 () T97S04 () 8X (8pin thin TSSOP) 40ML (40pin QFN) Leadfree, RoHS ommercial (0 to 70 ) Industrial (40 to 85 ) Note:. Please see the T97S04 datasheet addendum for the complete catalog number ordering code. Package Type 8X 40ML 8lead, 4.4mm body width, Plastic Thin Shrink Small Outline (thin TSSOP) 40pad 6.0 x 6.0x0.9mm body, 0.50mm pitch, Verythin Quad Flat No Lead (VQFN) tmel T97S04 LP Interface [SUMMRY TSHEET] 4

5 4. Package rawings 4. 8X 8lead Thin TSSOP TOP VIEW EN VIEW ETIL '' B 4 ( REF) S E E L R R H (0 ~8 ) d 0.0 B X N/ TIPS 5 e 8 SEE ETIL "" L (.00 REF) 0.5 ( REF) 8X b SIE VIEW j n 0.0 m B d 0.0 SETING PLNE OMMON IMENSIONS (UNIT OF MESURE=MM) SYMBOL MIN NOM MX NOTE Note:. Refer to JEE drawing MO5,variation E. imension does not include mold flash, protrusions or gate burrs. Mold flash,protrusions or gate burrs shall not exceed 0.5mm per end. imension E does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.5mm per side.. imension "b" does not include dambar protrusion. llowable dambar protrusion shall be 0.08mm total in excess of the "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm b c E E e L BS BS R 0.09 R 0.09 S 0.0 7/8/0 Package rawing ontact: [email protected] TITLE 8X, 8lead, 4.4mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) GP TFL RWING NO. 8X REV. tmel T97S04 LP Interface [SUMMRY TSHEET] 5

6 4. 40ML 40pad VQFN N X 0.0 X 0.0 B Pin Indicator E Top View L B 0 Side View OMMON IMENSIONS (Unit of Measure = mm) E SYMBOL MIN NOM MX NOTE 6.00 BS b E 6.00 BS E N e REF PIN I Bottom View L e 0.50 BS b Notes: Package rawing ontact: [email protected]. This drawing is for general information only. Refer to JEE rawing MO0, Variation WJJ, for proper dimensions, tolerances, datums, etc.. imension b applies to metallized terminal and is measured between 0.5 mm and 0.0 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 09// TITLE 40ML, 40pad 6.0 x 6.0x0.9 mm Body, 0.50 mm pitch, VeryThin Quad Flat No Lead Package (VQFN) Punched GP ZJI RWING NO. 40ML REV. tmel T97S04 LP Interface [SUMMRY TSHEET] 6

7 5. Revision History oc. Rev. ate omments 595ES 0/0 595S /0 Removed bullet from features: 048bit RS sign in 00ms. Updated footers and disclaimer page. hanged GPIO6 to GPIOExpress00. Updated package drawings 8 and 40ML. Updated package drawing 8 to 8X. Updated template and tmel logos. 595S 0/0 orrected header and footers. 595BS 0/00 dded Industrial Grade support detail. 595S 0/008 Initial document release. tmel T97S04 LP Interface [SUMMRY TSHEET] 7

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