The K computer: Project overview

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1 The Next-Generation Supercomputer The K computer: Project overview SHOJI, Fumiyoshi Next-Generation Supercomputer R&D Center, RIKEN

2 The K computer Outline Project Overview System Configuration of the K computer Facilities for the system

3 The K computer Outline Project Overview System Configuration of the K computer Facilities for the system

4 The K computer What is K computer? 京 (Kei) is a nickname of the Next-Generation Supercomputer system. The name was chosen from public applications this July. 京 is a Japanese prefix number like mega, tera, peta, etc., which means 10 16, or 10 peta. 万 (man)=10 4, 億 (oku)=10 8, 兆 (cho)=10 12, 垓 (gai)=10 20, K computer is assigned for English documents. A logo was also determined. It was written by a famous Japanese calligrapher Souun TAKEDA. Another meaning of the 京 is a big gate. A new era of computational science is coming though the gate 京. by hoping promised future success.

5 The K computer Goals of the Next-Generation Supercomputer project Development and installation of the most advanced high performance supercomputer system with LINPACK performance of 10 petaflops. Development and deployment of application software, which should be made to attain the system maximum capability, in various science and engineering fields. Establishment of an Advanced Institute for Computational Science:AICS as one of the Center of Excellence around supercomputing facilities. The AICS has been established in Kobe at October 2010.

Development and deployment of application software, which should be made to attain the system maximum capability, in various science and

6 The K computer Schedule of the project We are here. FY2006 FY2007 FY2008 FY2009 FY2010 FY2011 FY2012 System Conceptual design Detailed design Prototype, evaluation Production, installation, and adjustment Tuning and and improvement Buildings Applications Next-Generation Integrated Nanoscience Simulation Next-Generation Integrated Life Simulation Computer building Research building Development, production, and evaluation Development, production, and evaluation Design Design Construction Construction Verification Verification

installation, and adjustment Tuning and and improvement Buildings Applications Next-Generation Integrated Nanoscience Simulation

7 First installation of the K computer The eight racks has been housed at October 1, First Linpack result by a part of the system Rmax:48.03TFLOPS(Rpeak:52.22TFLOPS) Power:57.96kW

2010. First Linpack result by a part of the

8 The K computer Outline Project Overview System Configuration of the K computer Facilities for the system

9 Networks for Control and Management The K computer System configuration Users Control Servers Compute Nodes Number of CPUs > 80K Number of cores > 640K Total memory capacity > 1PB Internet System Configuration Interconnect Network Multi-dimensional Mesh/Torus Management Servers Job & User Management Local File System Global Global I/O I/O Networks Networks Global File System Frontend Servers

System Configuration Interconnect Network Multi-dimensional Mesh/Torus Management Servers Job &

10 The K computer CPU features (Fujitsu SPARC64 TM VIIIfx) 8 cores 2 SIMD operation units/core 2 Multiply & add floating-point operations (SP or DP) are executed in one SIMD instruction 256 FP registers/core (double precision) Performance 16GFLOPS/core, 128GFLOPS/CPU 2.2GFLOPS/W (58W at 30 by water cooling) Hardware barrier among cores Pre-fetch instruction Shared 6MB L2 Cache (12-way) Software controllable cache (sectored cache) Reference: SPARC64 TM VIIIfx Extensions 45nm CMOS process, 2GHz 22.7mm x 22.6mm 760 M transistors

2GFLOPS/W (58W at 30 by water cooling) Hardware barrier among cores Pre-fetch instruction Shared 6MB L2 Cache (12-way) Software controllable cache

11 5GB/s (peak) x 2 5GB/s (peak) x 2 Compute nodes and Network Compute nodes (CPUs): > 80,000 Number of cores: > 640,000 Peak performance: > 10PFLOPS Memory: > 1PB (16GB/node) 6-dimensional mesh/torus network: Tofu 10 connections to each adjacent node Peak bandwidth: 5GB/s x 2 for each connection Logically 3-dimensional torus network SPARC64 TM VIIIfx 5GB/s(peak) x 2 Compute ノード node CPU: 128GFLOPS (8 Core) Core Core SIMD(4FMA) Core SIMD(4FMA) Core SIMD(4FMA) Core SIMD(4FMA) Core SIMD(4FMA) Core16GFlops SIMD(4FMA) Core16GFlops 16GFlops SIMD(4FMA) 16GFlops SIMD(4FMA) 16GFlops 16GFlops 16GFlops 16GFLOPS 5GB/s (peak) x 2 z 5GB/s(peak) x 2 L2$:6MB 5MB 64GB/s MEM: 16GB y x Courtesy of FUJITSU Ltd.

VIIIfx 5GB/s(peak) x 2 Compute ノード node CPU: 128GFLOPS (8 Core) Core Core SIMD(4FMA) Core SIMD(4FMA) Core SIMD(4FMA) Core SIMD(4FMA) Core SIMD(4FMA) Core16GFlops SIMD(4FMA)

12 The Packaging K computer of the system A rack consists of 24 system boards, 6 IO boards, power supply units, system storages, and diagnostic processors. A hose pipe is connected to the water loop under the floor. 796mm システムボード System Board CPU 2060mm ~560mm ICC LSI for interconnect ~460mm

processors. A hose pipe is connected to the water loop under the floor.

13 The K computer Outline Project Overview System Configuration of the K computer Facilities for the system

14 AICS: location of the K computer in Kobe Kyoto AICS (Advanced Institute for Computational Science) was established at RIKEN last July. Kobe Tokyo 450km (280miles) west from Tokyo

15 Layout of the buildings Research Building Computer building Chillers Substation Supply

16 Image of the K computer More than 800 racks will be housed. The full system will be in operational in 2012.

17 The K computer Summary The Next-Generation Supercomputer 京 (kei), K computer The facilities for the K computer is complete. The installation of the K computer has started. The first measurement of LINPACK on a part of the system has been done. The full system of the K computer will be in operational at 2012.

The installation of the K computer has started.

18 Thank you for your attention! A photo in the early evening

SPARC64 VIIIfx: CPU for the K computer

SPARC64 VIIIfx: CPU for the K computer Toshio Yoshida Mikio Hondo Ryuji Kan Go Sugizaki SPARC64 VIIIfx, which was developed as a processor for the K computer, uses Fujitsu Semiconductor Ltd. s 45-nm CMOS