A COMPARATIVE STUDY OF THREE-PHASE AND SINGLE-PHASE PLL ALGORITHMS FOR GRID-CONNECTED SYSTEMS

Transcription

1 A COMPARATIE STUDY OF THREEPHASE AND SINGLEPHASE PLL ALGORITHMS FOR GRIDCONNECTED SYSTEMS Ruben Marco do Santo Filho Centro Federal de Educação Tecnológica CEFETMG Coord. Eletrônica Av. Amazona 553 Belo Horizonte MG CEP BRASIL Fax: Paulo F. Seixa, Porfírio C. Cortizo Univeridade Federal de Mina Gerai UFMG EE.UFMGDELT Av. Antônio Carlo 667 Belo Horizonte MG CEP BRASIL Fax: Abtract Thi worreent a comparative tudy of two threephae and five inglephae PLL tructure. It i hown through analytical and imulation reult that the threephae SRF PLL and the intantaneou power baed threephae PLL behave exactly equal, what i corroborated by tet of voltage and frequency diturbance, harmonic injection and line unbalance. However, the power PLL algorithm i more efficient ince it require fewer computation in it phae detector. The five different type of inglephae PLL tructure are briefly reviewed and their performance are evaluated under everal line diturbance. Index term Phaelocked loop (PLL), ynchronou reference frame (SRF), adaptive linear combiner (ALC). I. INTRODUCTION The correct phae angle i a very important information in gridconnected ytem uch a UPS, controlled rectifier, active filter, dynamic voltage retorer and alo in the emerging ditributed generation ytem uch a eolic and photovoltaic. To etimate the phae angle open loop and cloed loop method are available [7]. The cloed loop method are commonly known a PhaeLocked Loop or PLL. The figure of merit of a PLL are the teady tate phae angle error, peed of repone to phae, frequency and voltage amplitude diturbance, harmonic rejection and line unbalance in the cae of threephae ytem. Generally, the line frequency varie within a limited range even in iolated ytem, and it rate of change i limited by generator mechanical inertia. But when (unbalanced) grid fault occur, equipment are ubjected to phae angle jump and voltage ag [3]. The unbalanced ituation may lat for everal cycle before the fault i cleared. Thu, the development of robut ynchronizing algorithm i needed for the growing performance requirement of modern gridconnected equipment. In recent year, everal PLL algorithm have been developed and preented in the literature [][5]. The main objective of thi wor to briefly review and evaluate ome PLL algorithm for gridconnected ytem under divere line diturbance. In Section II, analytical reult of the threephae ynchronou reference frame PLL tructure (PLL) [] and threephae intantaneou power baed PLL (ppll) [][4], will be preented. Section III will preent five different inglephae tructure. The firt two are baed on the SRF method, the third i baed on the intantaneou power PLL, and the two later are baed on adaptive filter theory. II. THREEPHASE PLLS In the following ubection the block diagram and equation of the phae detector of the two threephae PLL tructure will be hown. A. ThreePhae SRF PLL (PLL) The block diagram of the PLL i hown in Fig. []. The grid voltage ample are va, vb and vc. Comparing thi diagram to the conventional PLL ued in telecommunication, it can be een that the PI controller i analogou to the low pa filter, the integrator i analogou to the voltage controlled ocillator, and the SRF tranformation block cheme i analogou to the phae detector. It working principle relie on regulating to zero the direct component of the rotating frame. Thi component i calculated uing the etimated phae angle, cloing the loop. * d v a v b v c abc q α β Fig.. ThreePhae SRF PLL Auming balanced and harmonic free input voltage, the expreion of the daxi component which i feed to the PI controller i: α in ˆ θ ˆ d = β coθ () or = coθ in ˆ θ inθ co ˆ θ () leading to: = in( θ ˆ θ ) (3) where: i the phae detector output ignal; i the amplitude of the input voltage; θ i the angle of phae A; i the etimated angle.

2 Uing the ame procedure for the qaxi component q, we find it amplitude: q = co( θ ˆ θ ) (4) When approximateθ, in (3) will approximate zero and the PLL will be locked. In thi ituation, according to (4), q will be equal to the input voltage amplitude. B. Intantaneou Power ThreePhae PLL (ppll) The block diagram of the threephae ppll i hown in Fig. [][4]. The working principle of it phae detector i baed on regulating to zero the fictitiou intantaneou threephae power. Thi power i calculated uing the voltage ample and the fictitiou current i a and i c depicted in Fig. and generated through the etimated angle. The and gain determine the peed of repone and diturbance rejection of the PLL in a direct relation. However, there i a trade off between noie, harmonic and voltage unbalance rejection and peed of repone. The higher the gain, the wore the noie, harmonic and line unbalance rejection. The adequate bandwidth will depend on the application purpoe. The following imulation reult have been obtained for the dicretized threephae PLL and ppll. There have been ued 64 ample per line period or 3840Hz. The input voltage amplitude and frequency were normalized at p.u./60hz. The ame PI gain were et for both PLL: =00, =0,000. The PI gain were adjuted uch that a uitable ettling time and damping and an acceptable harmonic rejection were obtained. The 3/ factor ha been included in the PLL. p*=0 p i c co ( ˆ θ 0) ) Phae Angle Jump Repone The PLL repone to a 30 degree phae angle tep at t= i hown in Fig. 3. Both PLL behave exactly equal a pointed out by (3) and (7) with a ettling time of about 40m and zero teadytate error. v a v b v c i a Fig.. Threephae ppll ˆ ) co(θ Auming balanced and harmonic free input voltage, the expreion of the phae detector output ignal p which i fed to the PI controller can be found by writing the intantaneou threephae power expreion: p = v i v i v i (5) a a b b c c Since i i i 0, (5) can be rewritten a: a b c = p = (v v )i (v v ) i (6) a b a Subtituting v a = in( θ ), v b = in( θ π / 3) and v c = in( θ π / 3) in (6) and making the implification we obtain: 3 p = in( θ ˆ θ ) (7) C. Simulation Reult and Performance Comparion The phae detector expreion of both threephae PLL depend on input voltage amplitude and phae. Equation (3) and (7) are imilar, except for the factor 3/ in (7). A they were obtained for balanced and harmonic free grid voltage, the following tet will evaluate the PLL behavior under non ideal and tranient ituation. c b c Fig. 3. Repone of the threephae ppll and PLL to a 30 degree phaeangle jump in the input voltage. ) Frequency Step Repone Fig. 4 how the repone of the threephae PLL to a 5Hz frequency tep at t=. Although the line utility frequency commonly change in a narrow range even in iolated ytem and it rate of change Fig. 4. Repone of the threephae PLL to a 5Hz frequency tep.

3 i limited due to the generator inertia, the frequency tep tet intend to give an idea of ytem peed and adaptivity. The overlap of both repone can be een again. The PLL achieve zero error in teadytate after the frequency change. 3) Harmonic Rejection The preence of harmonic in the line voltage lead to ocillating phae angle error at PLL output with near to zero average value. The tet wa performed applying one harmonic at a time. The peahae angle error obtained for both PLL a a function of harmonic order and amplitude i hown in Fig. 5. A tated before, both PLL behave equally. It can be een that higher harmonic frequencie lead to lower error. The inability of the PLL to accurately track unbalanced line voltage i well known in the literature. Several cheme have been propoed in order to improve the unbalance rejection of the PLL [7],[],[4]. Thoe cheme uually compute the intantaneou poitive equence component of the input voltage and feed them to the PLL. The imulation and analytical reult obtained ugget that uch cheme are alo applicable to the threephae ppll and would produce the ame reult. 5) Computational Load Table I diplay the number of computation needed in the phae detector tage of the threephae PLL and ppll. The PI and the integrator were not included becaue they are equal in both PLL. A can be een, the phae detector of the threephae ppll i more efficient ince it require fewer computation. Actually, effective computational load of the PLL algorithm will depend on ued proceor architecture. Table I Computational Load of ThreePhae Algorithm Number of Operation in the Phae Detector Algorithm Mult. Addition Trigon. Total PLL % ppll % III. SINGLEPHASE PLLS Fig. 5. Peahae angle error of the threephae PLL in the preence of harmonic ditortion in input voltage. 4) Phae Unbalance Repone Thi tet ha been performed uing the ANSI/IEEE tandard 4986 which quantifie the threephae unbalance a the relative maximum individual line rm voltage deviation in relation to the average rm value of the three phae: a,b,c ( ) max RMS RMS Unbalance% = 00% (8) RMS where i the average rm value of the three phae. RMS Fig. 6 how the peak and average phae angle error of both PLL a a conequence of line unbalance, which ha been calculated through (8). Five different inglephae PLL tructure have been tudied: two inglephae verion of the threephae PLL (PLLFIFO and PLLPark) [5],[6]; one inglephae verion of the threephae ppll (ppll) [5]; the enhanced PLL (EPLL) [7],[8]; and finally one PLL which employ an adaptive filter to etimate line phae angle (PLLALC) []. A. Singlephae Tranport Delay PLL (PLLFIFO) Fig. 7 how the block diagram of the PLLFIFO [5],[6]. It working principle i the ame of it threephae verion. It ue a firtinfirtout regiter to build the quadrature component to the tranformation. Due to the fixed length delay, it i not able to adjut to input voltage frequency deviation, leading to phae angle error a will be hown in the imulation reult. Other alternative to generate the quadrature component i the Hilbert tranformer, but it i very difficult to implement in low frequency (50/60Hz). * d q Fig. 6. Peak and average phae angle error of the threephae PLL a a function of input voltage unbalance. β Delay /4 Cycle (FIFO) α Fig. 7. Singlephae tranport delay PLL

4 B. Singlephae Invere Park PLL (PLLPark) Fig. 8 diplay the block diagram of the inglephae invere Park baed PLL [5],[6]. It i alo baed on frame orientation. The quadrature component α i build through the invere Park tranformation. * d q p p α Fig. 8. Singlephae invere Park PLL C. Singlephae Power PLL (ppll) β Fig. 9 diplay the block diagram of the inglephae ppll [5]. A it threephae verion, it i alo baed on annulling the fictitiou intantaneou power. Auming purely inuoidal input voltage in the form inθ, the expreion of the phae detector output ignal i: or p = inθ co ˆ θ (9) p = in( θ ˆ θ ) in( θ ˆ θ ) (0) A pointed out by (0), there i a trong drawback to thi tructure: the product of input voltage and virtual current ha a econd harmonic component which ha to be filtered out. Thu, a low pa filter with low cutoff frequency i needed, lowing down ytem peed. The adopted approach in the performed imulation wa to ue the tate feedback technique to allocate cloed loop pole and hence ytem dynamic, a preented in [5]. u e ^ A K x x Fig. 0. Singlephae Enhanced PLL Thi PLL i baed on adaptive filter theory. Baically, it recontruct in real time the fundamental component of the input ignal by etimating it amplitude, phae and frequency through the teepet decent algorithm. In other word, thi PLL ha a nonlinear phae detector. The gain K control the convergence peed of the etimated amplitude Â. Roughly peaking, the adaptive filter theory i baed on the idea that an output ignal y(t) of a ytem can be recontructed (or etimated) modifying the gain of a linear combiner a a function of an error e(t), which in turn i the difference between the etimated ignal ŷ (t) and the ytem output (the deired ignal), a depicted in Fig.. In the PLL context, the deired ignal y(t) i the grid voltage. The etimated ignal ŷ (t) i built with the etimated phaeangle, a well a the input x(t) to the filter. x(t) Adaptive Filter Sytem ŷ(t) e(t) y(t) θ &ˆ in co (deired ignal) Fig.. Adaptive filter tructure (etimated ignal) E. Singlephae Adaptive Linear Combiner PLL (PLLALC) Fig. diplay the block diagram of the PLLALC, which i alo baed on adaptive filter theory []. p*=0 x x e State Fbk. nd order ωˆ Controller filter x 3 W * W W W &ˆ θ u(t) i (t) co( ) Fig. 9. Singlephae power PLL W W x x in co D. Singlephae Enhanced PLL (EPLL) Fig. 0 diplay the block diagram of the EPLL [7],[8]. Adaptation Algorithm e u Fig.. Singlephae Adaptive Linear Combiner PLL

5 The filter input x and x are built with the etimated phae angle, what i analogou to the EPLL cheme in Fig. 0. The linear combiner gain W and W are updated online uing the delta rule. The PI controller regulate the gain W to zero. Thu the W gain become equal to the input voltage amplitude when equal θ. The normalizing block which compute W W improve tranient repone to voltage diturbance but it i not eential. F. Simulation Reult and Performance Comparion All inglephae PLL were dicretized with a ample rate of 64 ample per 60Hz cycle or 3840Hz. The ame PI gain were et to the PLLFIFO, PLL_Park, and EPLL: =00, =0,000. Half thi value had to be et to the PLLALC PI controller due to tability iue. The EPLL gain K wa et to 00. The ppll filter wa implemented by two cacaded firt order filter with cutoff frequency of 4Hz, reulting in 8dB of attenuation at 0Hz. The tate feedback gain were et o that the cloed loop pole were at 5Hz and 0Hz with optimum damping factor. In the PLLPark the cutoff frequencie of the two firt order filter were et to 0Hz. In the PLLALC the convergence gain α of the adaptation algorithm wa et to 0.5. ) oltage Sag Repone Fig. 3 how the imulation reult for thi tet. It can be een that the PLLFIFO ha the bet repone to voltage diturbance. The cloed loop pole choen to the ppll led to a noticeable ocillation in the phae angle error in teady tate, though maller than 0.5 degree peaktopeak. The PLLParreented the highet overhoot with the hortet ettling time. Table II how a more objective comparion criterion of all five repone through the ISE integral of quare error index. ) PhaeAngle Jump Repone Fig. 4 how the reult for thi tet, and Table III how the ISE of all five repone. The ppll ha the lowet repone due to it filter with mall cutoff frequency. PLLFIFO ha the mallet underhoot, and PLLPark ha the mallet ettling time. Fig. 4. Singlephae PLL repone to a phaeangle jump of 30 degree Table III PhaeAngle Jump Tet ISE SinglePhae Algorithm ISE Integral of Square PhaeAngle Error Algorithm PLLFIFO PLLParPLL EPLL PLLALC ISE % 8.7% 00% 30.6% 4.8% 3) Frequency Step Repone Fig. 5 how the imulation reult for thi tet. A can be een, PLLFIFO can not deal with frequency deviation due to it fixed delay, which have been adjuted to the line nominal frequency. Again, the ppll preented the lowet repone but zero teady tate error. The bet repone wa achieved by the PLLPark, a indicated in Table I. Fig. 3. Singlephae PLL repone to a voltage ag of 30% Table II oltage Sag Tet ISE SinglePhae Algorithm ISE Integral of Square PhaeAngle Error Algorithm PLLFIFO PLLParPLL EPLL PLLALC ISE % 00% 3.5% 5% 56.% Fig. 5. Singlephae PLL repone to a frequency tep of 5Hz

6 Table I Frequency Step Tet ISE SinglePhae Algorithm ISE Integral of Square PhaeAngle Error Algorithm PLLFIFO PLLParPLL EPLL PLLALC ISE %.% 00% 3.5% 4.% 4) Harmonic Repone Fig. 6 how the time repone to 5% 3 rd harmonic injection in the line input voltage. In ome repone there i a dc error uperimpoed to the ocillating phaeangle error. Table Computational Load of the SinglePhae Algorithm Total Number of Operation Algorithm Mult Add. Trig. Div Shift Total % PLLFIFO % PLLPark % ppll % EPLL % PLLALC * 7% * Diviion ha been weighted by a factor of 0. I. CONCLUSIONS Fig. 6. Singlephae PLL repone to 5% 3 rd harmonic injection in the input voltage Fig. 7 how how each PLL behave in preence of the 3 rd, 5 th and 7 th harmonic. The PLLALC ha the lowet enitivity (degree of deviation per harmonic %). In thi work, it wa hown that the phae detector tage of the two main threephae PLL tructure for gridconnected ytem found in the literature have practically the ame equation, leading to identical behavior under line diturbance, harmonic and line unbalance. Furthermore, the threephae power PLL algorithm i more efficient from the computational point of view, demanding about half the number of calculation on it phae detector tage. Although not teted in thi work, the imulation and analytical reult ugget that the poitive equence detection cheme ued in the traditional threephae SRF PLL are alo applicable to the threephae power PLL and would produce the ame reult. Five different type of inglephae PLL found in the literature have been briefly reviewed and it imulation reult have been preented. The inglephae power PLL algorithm preented the lowet repone to frequency and phae diturbance but it i the tiffet to voltage ag and harmonic due to the low cutoff frequency of it filter. The tranport delay PLL require the lowet computational effort, followed by the EPLL. The PLLALC i the heaviet algorithm from proceing time viewpoint, but i le enitive to harmonic and o fat a the EPLL and PLL Park.. REFERENCES Fig. 7. Singlephae PLL enibilitie to harmonic 5) Computational Load The total number of calculation for each inglephae PLL algorithm i hown in Table. The normalizing block wa not conidered in the PLLALC computational load, and the diviion operation ha been weighted by a factor of 0 due to it inherent implementation complexity. [] Kaura,. and Blako,., Operation of a Phae Locked Loop Sytem Under Ditorted Utility Condition, IEEE Tran. on Ind. Application, vol. 33. no., pp.5863, Jan Silva, S.A.O. and Coelho, E.A.A., Analyi an [] Deign of a ThreePhae PLL Structure for Utility Connected Sytem under Ditorted Utility Condition, in Proc. Conf. Rec. IEEECIEP, 004, pp.83. [3] Arede M. et al, Control Strategie for Serie and Shunt Active Filter, in Proc. Conf. Rec. IEEE Powertech, 6 pp [4] Arede, M. and Monteiro, L.F.C., A Control Strategy for hunt Active Filter, in Proc. Conf. Rec. IEEE ICHQP, 00, pp

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