FT232R USB UART I.C.

Transcription

1 Future echnology evices International Ltd. FR USB UAR I.C. Incorporating Clock enerator Output and FIChip-I Security ongle he FR is the latest device to be added to FI s range of USB UAR interface Integrated Circuit evices. he FR is a USB to serial UAR interface with optional clock generator output, and the new FIChip-I security dongle feature. In addition, asynchronous and synchronous bit bang interface modes are available. USB to serial designs using the FR have been further simplified by fully integrating the external EEPROM, clock circuit and USB resistors onto the device. he FR adds two new functions compared with its predecessors, effectively making it a -in- chip for some application areas. he internally generated clock (6MHz, MHz, 4MHz, and 48MHz) can be brought out of the device and used to drive a microcontroller or external logic. A unique number (the FIChip-I ) is burnt into the device during manufacture and is readable over USB, thus forming the basis of a security dongle which can be used to protect customer application software from being copied. he FR is available in Pb-free (RoHS compliant) compact 8-Lead SSOP and QF- packages. Copyright Future echnology evices International Ltd. 00

2 . Features Page. Hardware Features Single chip USB to asynchronous serial data transfer interface. Entire USB protocol handled on the chip - o USB-specific firmware programming required. UAR interface support for 7 or 8 data bits, or stop bits and odd / even / mark / space / no parity. Fully assisted hardware or X-On / X-Off software handshaking. ata transfer rates from 00 baud to Megabaud (RS4 / RS48 and at L levels) and 00 baud to Megabaud (RS). In-built support for event characters and line break condition. ew USB FIChip-I feature. ew configurable CBUS I/O pins. Auto transmit buffer control for RS48 applications. ransmit and receive LE drive signals. ew 48MHz, 4MHz,MHz, and 6MHz clock output signal Options for driving external MCU or FPA. FIFO receive and transmit buffers for high data throughput. Adjustable receive buffer timeout. Synchronous and asynchronous bit bang mode interface options with R# and WR# strobes. ew CBUS bit bang mode option. Integrated 04 Byte internal EEPROM for I/O configuration and storing USB VI, PI, serial number and product description strings. evice supplied preprogrammed with unique USB serial number. Support for USB suspend / resume. Support for bus powered, self powered, and highpower bus powered USB configurations. Integrated.V level converter for USB I/O. Integrated level converter on UAR and CBUS for interfacing to V -.8V Logic. rue V /.V /.8V /.8V CMOS drive output and L input. High I/O pin output drive option. Integrated USB resistors. Integrated power-on-reset circuit. Fully integrated clock - no external crystal, oscillator, or resonator required. Fully integrated AVCC supply filtering - o separate AVCC pin and no external R-C filter required. UAR signal inversion option. USB bulk transfer mode..v to.v Single Supply Operation. Low operating and USB suspend current. Low USB bandwidth consumption. UHCI / OHCI / EHCI host controller compatible USB.0 Full Speed compatible. Available in compact Pb-free 8 Pin SSOP and QF- packages (both RoHS compliant).. river Support Royalty-Free VIRUAL COM POR (VCP) RIVERS for... Windows 98, 98SE, ME, 000, Server 00, XP. Windows Vista / Longhorn* Windows XP 64-bit.* Windows XP Embedded. Windows CE.E 4. &.0 MAC OS 8 / 9, OS-X Linux.4 and greater Royalty-Free XX irect rivers (USB rivers + LL S/W Interface) Windows 98, 98SE, ME, 000, Server 00, XP. Windows Vista / Longhorn* Windows XP 64-bit.* Windows XP Embedded. Windows CE.E 4. &.0 Linux.4 and greater he drivers listed above are all available to download for free from the FI website. Various rd Party rivers are also available for various other operating systems - see the FI website for details. * Currently Under evelopment. Contact FI for availability.. ypical Applications USB to RS / RS4 / RS48 Converters Upgrading Legacy Peripherals to USB Cellular and Cordless Phone USB data transfer cables and interfaces Interfacing MCU / PL / FPA based designs to USB USB Audio and Low Bandwidth Video data transfer PA to USB data transfer USB Smart Card Readers USB Instrumentation USB Industrial Control USB MP Player Interface USB FLASH Card Reader / Writers Set op Box PC - USB interface USB igital Camera Interface USB Hardware Modems USB Wireless Modems USB Bar Code Readers USB Software / Hardware Encryption ongles FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

3 . Enhancements Page. evice Enhancements and Key Features his section summarises the enhancements and the key features of the FR device. For further details, consult the device pin-out description and functional description sections. Integrated Clock Circuit - Previous generations of FI s USB UAR devices required an external crystal or ceramic resonator. he clock circuit has now been integrated onto the device meaning that no crystal or ceramic resonator is required. However, if required, an external MHz crystal can be used as the clock source. Integrated EEPROM - Previous generations of FI s USB UAR devices required an external EEPROM if the device were to use USB Vendor I (VI), Product I (PI), serial number and product description strings other than the default values in the device itself. his external EEPROM has now been integrated onto the FR chip meaning that all designs have the option to change the product description strings. A user area of the internal EEPROM is available for storing additional data. he internal EEPROM is programmable in circuit, over USB without any additional voltage requirement. Preprogrammed EEPROM - he FR is supplied with its internal EEPROM preprogrammed with a serial number which is unique to each individual device. his, in most cases, will remove the need to program the device EEPROM. Integrated USB Resistors - Previous generations of FI s USB UAR devices required two external series resistors on the USBP and USBM lines, and a. KΩ pull up resistor on USBP. hese three resistors have now been integrated onto the device. Integrated AVCC Filtering - Previous generations of FI s USB UAR devices had a separate AVCC pin - the supply to the internal PLL. his pin required an external R-C filter. he separate AVCC pin is now connected internally to VCC, and the filter has now been integrated onto the chip. Less External Components - Integration of the crystal, EEPROM, USB resistors, and AVCC filter will substantially reduce the bill of materials cost for USB interface designs using the FR compared to its FBM predecessor. Configurable CBUS I/O Pin Options - here are now configurable Control Bus (CBUS) lines. Options are XE - transmit enable for RS48 designs, PWRE# - Power control for high power, bus powered designs, XLE# - for pulsing an LE upon transmission of data, RXLE# - for pulsing an LE upon receiving data, X&RXLE# - which will pulse an LE upon transmission OR reception of data, SLEEP# - indicates the device going into USB suspend mode, CLK48 / CLK4 / CLK / CLK6-48MHz, 4MHz,MHz, and 6MHz clock output signal options. here are also bit bang mode options (see below). he CBUS lines can be configured with any one of these output options by setting bits in the internal EEPROM. he device is supplied with the most commonly used pin definitions preprogrammed - see Section 0 for details. Enhanced Asynchronous Bit Bang Mode with R# and WR# Strobes - he FR supports FI s BM chip bit bang mode. In bit bang mode, the eight UAR lines can be switched from the regular interface mode to an 8-bit Parallel I/O port. ata packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the baud rate prescaler). With the FR device this mode has been enhanced so that the internal R# and WR# strobes are now brought out of the device which can be used to allow external logic to be clocked by accesses to the bit bang I/O bus. his option will be described more fully in a separate application note Synchronous Bit Bang Mode - Synchronous bit bang mode differs from asynchronous bit bang mode in that the interface pins are only read when the device is written to. hus making it easier for the controlling program to measure the response to an output stimulus as the data returned is synchronous to the output data. he feature was previously seen in FI s FC device. his option will be described more fully in a separate application note. CBUS Bit Bang Mode - his mode allows four of the CBUS pins to be individually configured as PIO pins, similar to Asynchronous bit bang mode. his mode is available while the UAR interface is being used, thus providing up to four general purpose I/O pins which are available during normal operation. An application note describing this feature is available separately from the FI website. FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

4 Page 4 Lower Supply Voltage - Previous generations of the chip required V supply on the VCC pin. he FR will work with a supply in the range.v - V. Bus powered designs would still take their supply from the V on the USB bus, but for self powered designs where only.v is available and there is no V supply there is no longer any need for an additional external regulator. Integrated Level Converter on UAR Interface and Control Signals - VCCIO pin supply can be from.8v to V. Connecting the VCCIO pin to.8v,.8v, or.v allows the device to directly interface to.8v,.8v or.v and other logic families without the need for external level converter I.C.s V /.V /.8V /.8V Logic Interface - he FR provides true CMOS rive Outputs and L level Inputs. Integrated Power-On-Reset (POR) Circuit- he device incorporates an internal POR function. A RESE# pin is available in order to allow external logic to reset the FR where required. However, for many applications the RESE# pin can be left unconnected, or pulled up to VCC. Lower Operating and Suspend Current - he device operating supply current has been further reduced to ma, and the suspend current has been reduced to around 70μA. Low USB Bandwidth Consumption - he operation of the USB interface to the FR has been designed to use as little as possible of the total USB bandwidth available from the USB host controller. High Output rive Option - he UAR interface and CBUS I/O pins can be made to drive out at three times the standard signal drive level thus allowing multiple devices to be driven, or devices that require a greater signal drive strength to be interfaced to the FR. his option is configured in the internal EEPROM. Power Management Control for USB Bus Powered, High Current esigns- he PWRE# signal can be used to directly drive a transistor or P-Channel MOSFE in applications where power switching of external circuitry is required. An option in the internal EEPROM makes the device gently pull down on its UAR interface lines when the power is shut off (PWRE# is high). In this mode any residual voltage on external circuitry is bled to when power is removed, thus ensuring that external circuitry controlled by PWRE# resets reliably when power is restored. UAR Pin Signal Inversion - Each of the UAR signals can be individually inverted by setting an option in the internal EEPROM. FIChip-I - Each FR is assigned a unique number which is burnt into the device at manufacture. his I number cannot be reprogrammed by product manufacturers or end-users. his allows the possibility of using FR based dongles for software licensing. Further to this, a renewable license scheme can be implemented based on the FIChip-I number when encrypted with other information. his encrypted number can be stored in the user area of the FR internal EEPROM, and can be decrypted, then compared with the protected FIChip-I to verify that a license is valid. Web based applications can be used to maintain product licensing this way. An application note describing this feature is available separately from the FI website. Improved EMI Performance - he reduced operating current and improved on-chip VCC decoupling significantly improves the ease of PCB design requirements in order to meet FCC, CE and other EMI related specifications. Programmable Receive Buffer imeout - he receive buffer timeout is used to flush remaining data from the receive buffer. his time defaults to 6ms, but is programmable over USB in ms increments from ms to ms, thus allowing the device to be optimised for protocols that require fast response times from short data packets. ew Package Options - he FR is available in two packages - a compact 8 pin SSOP ( FRL) and an ultra-compact mm x mm pinless QF- package ( FRQ). Both packages are lead ( Pb ) free, and use a green compound. Both packages are fully compliant with European Union directive 00/9/EC. FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

5 . Block iagram Page. Block iagram (Simplified) VCC 48MHz Baud Rate enerator VOU USBP USBM. Volt LO Regulator USB ransceiver with Integrated Series Resistors and.k Pull-up Serial Interface Engine ( SIE ) o USB ransceiver Cell FIFO X Buffer USB Protocol Engine Internal EEPROM UAR FIFO Controller VCCIO UAR Controller with Programmable Signal Inversion and High rive X RX RS# CS# R# SR# C# RI# CBUS0 CBUS CBUS CBUS CBUS4 USB PLL VOU OSCO (optional) OCSI (optional) Internal MHz Oscillator Clock Multiplier / ivider 48MHz 4 MHz MHz 6 MHz FIFO RX Buffer RESE# o USB ransceiver Cell RESE EERAOR ES Figure - FR Block iagram. Functional Block escriptions.v LO Regulator - he.v LO Regulator generates the.v reference voltage for driving the USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the VOU regulator output pin. It also provides.v power to the.kω internal pull up resistor on USBP. he main function of this block is to power the USB ransceiver and the Reset enerator Cells rather than to power external logic. However, external circuitry requiring.v nominal at a current of not greater than 0mA could also draw its power from the VOU pin if required. USB ransceiver - he USB ransceiver Cell provides the USB. / USB.0 full-speed physical interface to the USB cable. he output drivers provide. volt level slew rate control signalling, whilst a differential receiver and two single ended receivers provide USB data in, SEO and USB Reset condition detection. his Cell also incorporates internal USB series resistors on the USB data lines, and a.kω pull up resistor on USBP. USB PLL - he USB PLL cell locks on to the incoming RZI USB data and provides separate recovered clock and data signals to the SIE block. Internal MHz Oscillator - he Internal MHz Oscillator cell generates a MHz reference clock input to the x4 Clock multiplier. he MHz Oscillator is also used as the reference clock for the SIE, USB Protocol Engine and UAR FIFO controller blocks Clock Multiplier / ivider - he Clock Multiplier / ivider takes the MHz input from the Oscillator Cell and generates the 48MHz, 4MHz, MHz, and 6MHz reference clock signals. he 48Mz clock reference is used for the USB PLL and the Baud Rate enerator blocks. FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

6 Page 6 Serial Interface Engine (SIE) - he Serial Interface Engine (SIE) block performs the Parallel to Serial and Serial to Parallel conversion of the USB data. In accordance to the USB.0 specification, it performs bit stuffing / un-stuffing and CRC / CRC6 generation / checking on the USB data stream. USB Protocol Engine - he USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the low level USB protocol (Chapter 9) requests generated by the USB host controller and the commands for controlling the functional parameters of the UAR. FIFO X Buffer - ata from the USB data out endpoint is stored in the ual Port X buffer and removed from the buffer to the UAR transmit register under control of the UAR FIFO controller. FIFO RX Buffer - ata from the UAR receive register is stored in the ual Port RX buffer prior to being removed by the SIE on a USB request for data from the device data in endpoint. UAR FIFO Controller - he UAR FIFO controller handles the transfer of data between the ual Port RX and X buffers and the UAR transmit and receive registers. UAR Controller with Programmable Signal Inversion and High rive - he UAR controllers handle the transfer of data between the ual Port RX and X buffers and the UAR transmit and receive registers. It performs asynchronous 7 / 8 bit Parallel to Serial and Serial to Parallel conversion of the data on the RS (RS4 and RS48) interface. Control signals supported by UAR mode include RS, CS, SR, R, C and RI. here is also a transmitter enable control signal pin option (XE) provided to assist with interfacing to RS48 transceivers. RS/CS, SR/R and X-On / X-Off handshaking options are also supported. Handshaking, where required, is handled in hardware to ensure fast response times. he UAR also supports the RS BREAK setting and detection conditions. A new feature, programmable in the internal EEPROM allows the UAR signals to each be individually inverted. Another new EEPROM programmable feature allows the high signal signal drive strength on the UAR and CBUS. Baud Rate enerator - he Baud Rate enerator provides a x6 clock input to the UARs from the 48MHz reference clock and consists of a 4 bit prescaler and register bits which provide fine tuning of the baud rate (used to divide by a number plus a fraction). his determines the Baud Rate of the UAR which is programmable from 8 baud to million baud. he FR supports all standard baud rates and non-standard baud rates from 00 Baud up to Megabaud. Achievable non-standard baud rates are calculated as follows - Baud Rate = / (n + x) where n can be any integer between and 6,84 ( = 4 ) and x can be a sub-integer of the value 0, 0., 0., 0.7, 0., 0.6, 0.7, or When n =, x = 0, i.e. baud rate divisors with values between and are not possible. his gives achievable baud rates in the range 8. baud to,000,000 baud. When a non-standard baud rate is required simply pass the required baud rate value to the driver as normal, and the FI driver will calculate the required divisor, and set the baud rate. See FI application note AB-0 for more details. RESE enerator - he Reset enerator Cell provides a reliable power-on reset to the device internal circuitry on power up. An additional RESE# input is provided to allow other devices to reset the FR. RESE# can be tied to VCC or left unconnected unless it is a requirement to reset the device from external logic or an external reset generator I.C. Internal EEPROM - he internal EEPROM in the FR can be used to store USB Vendor I (VI), Product I (PI), device serial number, product description string, and various other USB configuration descriptors. he device is supplied with the internal EEPROM settings preprogrammed as described in Section 0. FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

7 4. evice Pin Out and Signal escriptions 4. 8-L SSOP Package Page 7 X 8 OSCO R# OSCI RS# ES VCCIO RX RI# C SR# C# CS# CBUS4 CBUS YYXX-A FRL FI A C CBUS0 CBUS VCC RESE# VOU USBM CBUS 4 USBP Figure - 8 Pin SSOP Package Pin Out VCCIO VCC USBM USBP X RX RS# CS# C RESE# C OSCI OSCO FRL R# SR# C# RI# CBUS0 7 VOU A E S CBUS CBUS CBUS CBUS Figure - 8 Pin SSOP Package Pin Out (Schematic Symbol) FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

8 4. SSOP-8 Package Signal escriptions Page 8 able - SSOP Package Pin Out escription Pin o. ame ype escription USB Interface roup USBP I/O USB ata Signal Plus, incorporating internal series resistor and.k pull up resistor to.v 6 USBM I/O USB ata Signal Minus, incorporating internal series resistor. Power and round roup 4 VCCIO PWR +.8V to +.V supply to I/O Interface group pins (...,, 6, 9...4,, ). In USB bus powered designs connect to VOU to drive out at.v levels, or connect to VCC to drive out at V CMOS level. his pin can also be supplied with an external.8v -.8V supply in order to drive out at lower levels. It should be noted that in this case this supply should originate from the same source as the supply to. his means that in bus powered designs a regulator which is supplied by the V on the USB bus should be used. 7, 8, PWR evice ground supply pins 7 VOU Output. Volt output from integrated L..O. regulator. his pin should be decoupled to ground using a 00nF capacitor. he prime purpose of this pin is to provide the internal.v supply to the USB transceiver cell and the internal.kω pull up resistor on USBP. Up to 0mA can be drawn from this pin to power external logic if required. his pin can also be used to supply the FR s VCCIO pin. 0 VCC PWR.V to.v supply to the device core. A PWR evice analog ground supply for internal clock multiplier Miscellaneous Signal roup 8, 4 C C o internal connection. 9 RESE# Input Can be used by an external device to reset the FR. If not required can be left unconnected or pulled up to. 6 ES Input Puts the device into I.C. test mode. Must be grounded for normal operation. 7 OSCI Input Input to MHz Oscillator Cell. Optional - Can be left unconnected for normal operation. 8 OSCO Output Output from MHz Oscillator Cell. Optional - Can be left unconnected for normal operation if internal oscillator is used. I/O Interface roup Pin efinitions* Pin o. ame ype escription X Output ransmit Asynchronous ata Output R# Output ata erminal Ready Control Output / Handshake signal RS# Output Request o Send Control Output / Handshake signal RX Input Receive Asynchronous ata Input 6 RI# Input Ring Indicator Control Input. When remote wake up is enabled in the internal EEPROM taking RI# low can be used to resume the PC USB host controller from suspend. 9 SR# Input ata Set Ready Control Input / Handshake signal. 0 C# Input ata Carrier etect Control input CS# Input Clear to Send Control input / Handshake signal CBUS4 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory efault function is SLEEP#. See CBUS Signal Options, able. CBUS I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory efault function is XE. See CBUS Signal Options, able. 4 CBUS I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory efault function is PWRE#. See CBUS Signal Options, able. CBUS I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory efault function is RXLE#. See CBUS Signal Options, able. CBUS0 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory efault function is XLE#. See CBUS Signal Options, able. * When used in Input Mode, these pins are pulled to VCCIO via internal 00K resistors. hese can be programmed to gently pull low during USB suspend ( PWRE# = ) by setting this option in the internal EEPROM. FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

9 4. QF- Package OP Page 9 8 FI YYXX-A FRQ BOOM C OSCO OSCI ES C RS# R# X A 4 C CBUS0 CBUS 0 VCC 9 RESE# 8 7 VCCIO RX RI# 4 C 6 SR# 7 C# 8 CS# Figure 4 - QF- Package Pin Out VOU USBM USBP C C CBUS CBUS CBUS VCCIO VCC USBM USBP C C C C C FRQ X RX RS# CS# R# SR# C# RESE# C OSCI OSCO VOU A E S RI# CBUS0 CBUS CBUS CBUS CBUS4 0 9 Figure - QF- Package Pin Out (Schematic Symbol) FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

10 4.4 QF- Package Signal escriptions Page 0 able - QF Package Pin Out escription Pin o. ame ype escription USB Interface roup 4 USBP I/O USB ata Signal Plus, incorporating internal series resistorand.k pull up resistor to.v USBM I/O USB ata Signal Minus, incorporating internal series resistor. Power and round roup VCCIO PWR +.8V to +.V supply to I/O Interface group pins (,, 6,...,,,, 0,..). In USB bus powered designs connect to VOU to drive out at.v levels, or connect to VCC to drive out at V CMOS level. his pin can also be supplied with an external.8v -.8V supply in order to drive out at lower levels. It should be noted that in this case this supply should originate from the same source as the supply to. his means that in bus powered designs a regulator which is supplied by the V on the USB bus should be used. 4, 7, 0 PWR evice ground supply pins 6 VOU Output. Volt output from integrated L..O. regulator. his pin should be decoupled to ground using a 00nF capacitor. he prime purpose of this pin is to provide the internal.v supply to the USB transceiver cell and the internal.k pull up resistor on USBP. Up to 0mA can be drawn from this pin to power external logic if required. his pin can also be used to supply the FR s VCCIO pin. 9 VCC PWR.V to.v supply to the device core. 4 A PWR evice analog ground supply for internal clock multiplier Miscellaneous Signal roup,,,,, 9 C C o internal connection. 8 RESE# Input Can be used by an external device to reset the FR. If not required can be left unconnected or pulled up to. 6 ES Input Puts the device into I.C. test mode. Must be grounded for normal operation. 7 OSCI Input Input to MHz Oscillator Cell. Optional - Can be left unconnected for normal operation. 8 OSCO Output Output from MHz Oscillator Cell. Optional - Can be left unconnected for normal operation if internal oscillator is used. I/O Interface roup Pin efinitions* Pin o. ame ype escription 0 X Output ransmit Asynchronous ata Output R# Output ata erminal Ready Control Output / Handshake signal RS# Output Request o Send Control Output / Handshake signal RX Input Receive Asynchronous ata Input RI# Input Ring Indicator Control Input. When remote wake up is enabled in the internal EEPROM taking RI# low can be used to resume the PC USB host controller from suspend. 6 SR# Input ata Set Ready Control Input / Handshake signal. 7 C# Input ata Carrier etect Control input 8 CS# Input Clear to Send Control input / Handshake signal 9 CBUS4 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory efault function is SLEEP#. See CBUS Signal Options, able. 0 CBUS I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory efault function is XE. See CBUS Signal Options, able. CBUS I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory efault function is PWRE#. See CBUS Signal Options, able. CBUS I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory efault function is RXLE#. See CBUS Signal Options, able. CBUS0 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory efault function is XLE#. See CBUS Signal Options, able. * When used in Input Mode, these pins are pulled to VCCIO via internal 00K resistors. hese can be programmed to gently pull low during USB suspend ( PWRE# = ) by setting this option in the internal EEPROM. FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

11 4. CBUS Signal Options Page he following options can be configured on the CBUS I/O pins. CBUS signal options are common to both package versions of the FR. hese options are all configured in the internal EEPROM using the utility software MPRO, which can be downloaded from the FI website. he default configuration is described in Section 0. able - CBUS Signal Options CBUS Signal Option Available On CBUS Pin... escription XE CBUS0, CBUS, CBUS, CBUS, CBUS4 Enable transmit data for RS48 PWRE# CBUS0, CBUS, CBUS, CBUS, CBUS4 oes low after the device is configured by USB, then high during USB suspend. Can be used to control power to external logic P- Channel logic level MOSFE switch. Enable the interface pull-down option when using the PWRE# pin in this way. XLE# CBUS0, CBUS, CBUS, CBUS, CBUS4 ransmit data LE drive - pulses low when transmitting data via USB. See Section 9 for more details. RXLE# CBUS0, CBUS, CBUS, CBUS, CBUS4 Receive data LE drive - pulses low when receiving data via USB. See Section 9 for more details. X&RXLE# CBUS0, CBUS, CBUS, CBUS, CBUS4 LE drive - pulses low when transmitting or receiving data via USB. See Section 9 for more details. SLEEP# CBUS0, CBUS, CBUS, CBUS, CBUS4 oes low during USB suspend mode. ypically used to power down an external L to RS level converter I.C. in USB to RS converter designs. CLK48 CBUS0, CBUS, CBUS, CBUS, CBUS4 48MHz Clock output. CLK4 CBUS0, CBUS, CBUS, CBUS, CBUS4 4MHz Clock output. CLK CBUS0, CBUS, CBUS, CBUS, CBUS4 MHz Clock output. CLK6 CBUS0, CBUS, CBUS, CBUS, CBUS4 6MHz Clock output. CBitBangI/O CBUS0, CBUS, CBUS, CBUS CBUS bit bang mode option. Allows up to 4 of the CBUS pins to be used as general purpose I/O. Configured individually for CBUS0 to CBUS in the internal EEPROM. A separate application note will describe in more detail how to use CBUS bit bang mode. BitBangWRn CBUS0, CBUS, CBUS, CBUS Bit bang mode WR# Strobe Output BitBangRn CBUS0, CBUS, CBUS, CBUS Bit bang mode R# Strobe Output FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

12 . Package Parameters Page he FR is supplied in two different packages. he FRL is the SSOP-8 option and the FRQ is the QF- package option.. SSOP-8 Package imensions / / / yp Min.7 +/ Max 0.6 +/-0.06 YYXX-A FRL FI 0.0 +/ /-0.0 yp. +/ Figure 6 - SSOP-8 Package imensions he FRL is supplied in a RoHS compliant 8 pin SSOP package. he package is lead ( Pb ) free and uses a green compound. he package is fully compliant with European Union directive 00/9/EC. his package has a.0mm x 0.0mm body ( 7.80mm x 0.0mm including pins ). he pins are on a 0.6 mm pitch. he above mechanical drawing shows the SSOP-8 package all dimensions are in millimetres. he date code format is YYXX where XX = digit week number, YY = digit year number. FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

13 Page. QF- Package imensions OP Indicates Pin # (Laser Marked) 8 FI YYXX-A FRQ BOOM Max Pin # I 0.0 +/ / Min / /-0.00 SIE / Figure 7 - QF- Package imensions /-0.00 he FRQ is supplied in a RoHS compliant leadless QF- package. he package is lead ( Pb ) free, and uses a green compound. he package is fully compliant with European Union directive 00/9/EC. his package has a compact.00mm x.00mm body. he solder pads are on a 0.0mm pitch. he above mechanical drawing shows the QF- package all dimensions are in millimetres. he centre pad on the base of the FRQ is not internally connected, and can be left unconnected, or connected to ground (recommended). he date code format is YYXX where XX = digit week number, YY = digit year number. FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

14 Page 4. Reflow Profile he FR is supplied in Pb free 8 L SSOP and QF- packages. he recommended solder reflow profile for both package options is shown in Figure 8. t p emperature, (egrees C) p L Max S Min S ts Preheat Ramp Up t L Critical Zone: when is in the range to p Ramp own L Figure 8 - FR Solder Reflow Profile = º C to P ime, t (seconds) he recommended values for the solder reflow profile are detailed in able 4. Values are shown for both a completely Pb free solder process (i.e. the FR is used with Pb free solder), and for a non-pb free solder process (i.e. the FR is used with non-pb free solder). able 4 - Reflow Profile Parameter Values Profile Feature Pb Free Solder Process on-pb Free Solder Process Average Ramp Up Rate ( s to p ) C / second Max. C / Second Max. Preheat - emperature Min ( S Min.) - emperature Max ( S Max.) - ime (t S Min to t S Max) ime Maintained Above Critical emperature L : - emperature ( L ) - ime (t L ) 0 C 00 C 60 to 0 seconds 7 C 60 to 0 seconds 00 C 0 C 60 to 0 seconds 8 C 60 to 0 seconds Peak emperature ( P ) 60 C 40 C ime within C of actual Peak emperature (t P ) 0 to 40 seconds 0 to 40 seconds Ramp own Rate 6 C / second Max. 6 C / second Max. ime for = C to Peak emperature, p 8 minutes Max. 6 minutes Max. FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

15 6. evice Characteristics and Ratings Page 6. Absolute Maximum Ratings he absolute maximum ratings for the FR devices are as follows. hese are in accordance with the Absolute Maximum Rating System (IEC 604). Exceeding these may cause permanent damage to the device. able - Absolute Maximum Ratings Parameter Value Unit Storage emperature -6 C to 0 C egrees C Floor Life (Out of Bag) At Factory Ambient ( 0 C / 60% Relative Humidity) 68 Hours (IPC/JEEC J-S-0A MSL Level Compliant)* Ambient emperature (Power Applied) 0 C to 70 C egrees C. Supply Voltage -0. to V.C. Input Voltage - Inputs -0. to +( +0.) V.C. Input Voltage - High Impedance Bidirectionals -0. to +( +0.) V.C. Output Current - Outputs 4 ma C Output Current - Low Impedance Bidirectionals 4 ma Power issipation ( =.V) 00 mw * If devices are stored out of the packaging beyond this time limit the devices should be baked before use. he devices should be ramped up to a temperature of C and baked for up to 7 hours. 6. C Characteristics C Characteristics ( Ambient emperature = 0 to 70 o C ) able 6 - Operating Voltage and Current Parameter escription Min yp Max Units Conditions VCC Operating Supply Voltage. -. V VCCIO Operating Supply Voltage.8 -. V Icc Operating Supply Current - - ma ormal Operation Icc Operating Supply Current μa USB Suspend* Hours *Supply current excludes the 00μA nominal drawn by the external pull-up resistor on USBP. able 7 - UAR and CBUS I/O Pin Characteristics (VCCIO =.0V, Standard rive Level) Parameter escription Min yp Max Units Conditions Voh Output Voltage High V I source = ma Vol Output Voltage Low V I sink = ma Vin Input Switching hreshold..6.9 V ** VHys Input Switching Hysteresis 0 60 mv ** able 8 - UAR and CBUS I/O Pin Characteristics (VCCIO =.V, Standard rive Level) Parameter escription Min yp Max Units Conditions Voh Output Voltage High..7. V I source = ma Vol Output Voltage Low V I sink = ma Vin Input Switching hreshold.0.. V ** VHys Input Switching Hysteresis 0 0 mv ** FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

16 able 9 - UAR and CBUS I/O Pin Characteristics (VCCIO =.8V, Standard rive Level) Parameter escription Min yp Max Units Conditions Voh Output Voltage High..6. V I source = ma Page 6 Vol Output Voltage Low V I sink = ma Vin Input Switching hreshold.0.. V ** VHys Input Switching Hysteresis 0 0 mv ** able 0 - UAR and CBUS I/O Pin Characteristics (VCCIO =.0V, High rive Level) Parameter escription Min yp Max Units Conditions Voh Output Voltage High V I source = 6 ma Vol Output Voltage Low V I sink = 6 ma Vin Input Switching hreshold..6.9 V ** VHys Input Switching Hysteresis 0 60 mv ** able - UAR and CBUS I/O Pin Characteristics (VCCIO =.V, High rive Level) Parameter escription Min yp Max Units Conditions Voh Output Voltage High..8. V I source = ma Vol Output Voltage Low V I sink = 8 ma Vin Input Switching hreshold.0.. V ** VHys Input Switching Hysteresis 0 0 mv ** able - UAR and CBUS I/O Pin Characteristics (VCCIO =.8V, High rive Level) Parameter escription Min yp Max Units Conditions Voh Output Voltage High..8. V I source = ma Vol Output Voltage Low V I sink = 8 ma Vin Input Switching hreshold.0.. V ** VHys Input Switching Hysteresis 0 0 mv ** **Inputs have an internal 00K pull-up resistor to VCCIO. able - RESE#, ES Pin Characteristics Parameter escription Min yp Max Units Conditions Vin Input Switching hreshold..6.9 V VHys Input Switching Hysteresis 0 60 mv able 4 - USB I/O Pin (USBP, USBM) Characteristics Parameter escription Min yp Max Units Conditions UVoh I/O Pins Static Output ( High).8.6 V RI =.K to VOut ( + ) RI = K to ( - ) UVol I/O Pins Static Output ( Low ) 0 0. V RI =.K to VOut ( + ) RI = K to ( - ) UVse Single Ended Rx hreshold V UCom ifferential Common Mode 0.8. V UVif ifferential Input Sensitivity 0. V UrvZ river Output Impedance Ohms *** ***river Output Impedance includes the internal USB series resistors on USBP and USBM pins. FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

17 6. EEPROM Reliability Characteristics Page 7 he internal 04 Byte EEPROM has the following reliability characteristics- able - EEPROM Characteristics Parameter escription Value Unit ata Retention Years Read / Write Cycles 00,000 Cycles 6.4 Internal Clock Characteristics he internal Clock Oscillator has the following characteristics. able 6 - Internal Clock Characteristics Parameter Value Unit Min ypical Max Frequency of Operation MHz Clock Period ns uty Cycle 4 0 % able 7 - OSCI, OSCO Pin Characteristics (Optional - Only applies if external Oscillator is used***) Parameter escription Min yp Max Units Conditions Voh Output Voltage High V Fosc = MHz Vol Output Voltage Low V Fosc = MHz Vin Input Switching hreshold.8.. V ***When supplied the device is configured to use its internal clock oscillator. Users who wish to use an external oscillator or crystal should contact FI technical support. FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

18 7. evice Configurations Page 8 Please note that pin numbers on the FR chip in this section have deliberately been left out as they vary between the FRL and FRQ versions of the device. All of these configurations apply to both package options for the FR device. Please refer to Section 4 for the package option pin-out and signal descriptions. 7. Bus Powered Configuration SHIEL 4 0nF + Ferrite Bead VCC USBM USBP VCCIO C RESE# C OSCI OSCO FR X RX RS# CS# R# SR# C# RI# CBUS0 CBUS 00nF 4.7uF + 00nF VOU A E S CBUS CBUS CBUS4 Figure 9 - Bus Powered Configuration Figure 9 illustrates the FR in a typical USB bus powered design configuration. A USB Bus Powered device gets its power from the USB bus. Basic rules for USB Bus power devices are as follows i) On plug-in to USB, the device must draw no more than 00mA. ii) On USB Suspend the device must draw no more than 00μA. iii) A Bus Powered High Power USB evice (one that draws more than 00mA) should use one of the CBUS pins configured as PWRE# and use it to keep the current below 00mA on plug-in and 00μA on USB suspend. iv) A device that consumes more than 00mA can not be plugged into a USB Bus Powered Hub v) o device can draw more that 00mA from the USB Bus. he power descriptor in the internal EEPROM should be programmed to match the current draw of the device. A Ferrite Bead is connected in series with USB power to prevent noise from the device and associated circuitry (EMI) being radiated down the USB cable to the Host. he value of the Ferrite Bead depends on the total current required by the circuit a suitable range of Ferrite Beads is available from Steward ( for example Steward Part # MI080K400R-00. FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

19 7. Self Powered Configuration Page 9 SHIEL 4 VCC =.V - V 4k7 0k VCC USBM USBP VCCIO C RESE# C OSCI OSCO FR X RX RS# CS# R# SR# C# RI# CBUS0 VCC CBUS 00nF 00nF 4.7uF + 00nF VOU A E S CBUS CBUS CBUS4 Figure 0 Self Powered Configuration Figure 0 illustrates the FR in a typical USB self powered configuration. A USB Self Powered device gets its power from its own POWER SUPPLY and does not draw current from the USB bus. he basic rules for USB Self power devices are as follows i) A Self Powered device should not force current down the USB bus when the USB Host or Hub Controller is powered down. ii) A Self Powered evice can use as much current as it likes during normal operation and USB suspend as it has its own power supply. iii) A Self Powered evice can be used with any USB Host and both Bus and Self Powered USB Hubs he power descriptor in the internal EEPROM should be programmed to a value of zero (self powered). In order to meet requirement (i) the USB Bus Power is used to control the RESE# Pin of the FR device. When the USB Host or Hub is powered up the internal.kω resistor on USBP is pulled up to.v, thus identifying the device as a full speed device to USB. When the USB Host or Hub power is off, RESE# will go low and the device will be held in reset. As RESE# is low, the internal.kω resistor will not be pulled up to.v, so no current will be forced down USBP via the.kω pull-up resistor when the host or hub is powered down. Failure to do this may cause some USB host or hub controllers to power up erratically. Figure 0 illustrates a self powered design which has a.v - V supply. A design which is interfacing to.8v -.8V logic would have a.8v -.8V supply to VCCIO, and a.v - V supply to VCC ote : When the FR is in reset, the UAR interface pins all go tri-state. hese pins have internal 00KΩ pull-up resistors to VCCIO, so they will gently pull high unless driven by some external logic. FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00

20 7. USB Bus Powered with Power Switching Configuration P-Channel Power MOSFE s d Switched V Power to External Logic Page 0 g 0.uF 0.uF Soft Start Circuit SHIEL 4 0nF + Ferrite Bead V VCC k VCC USBM USBP VCCIO C RESE# C OSCI OSCO FR X RX RS# CS# R# SR# C# RI# V VCC CBUS0 CBUS 00nF 4.7uF + 00nF VOU A E S CBUS CBUS CBUS4 PWRE# Figure - Bus Powered with Power Switching Configuration USB Bus powered circuits need to be able to power down in USB suspend mode in order to meet the <= 00μA total USB suspend current requirement (including external logic). Some external logic can power itself down into a low current state by monitoring the PWRE# signal. For external logic that cannot power itself down in this way, the FR provides a simple but effective way of turning off power to external circuitry during USB suspend. Figure shows how to use a discrete P-Channel Logic Level MOSFE to control the power to external logic circuits. A suitable device would be an International Rectifier ( IRLML640, or equivalent. It is recommended that a soft start circuit consisting of a KΩ series resistor and a 0.μF capacitor are used to limit the current surge when the MOSFE turns on. Without the soft start circuit there is a danger that the transient power surge of the MOSFE turning on will reset the FR, or the USB host / hub controller. he values used here allow attached circuitry to power up with a slew rate of ~.V per millisecond, in other words the output voltage will transition from to V in approximately 400 microseconds. Alternatively, a dedicated power switch I.C. with inbuilt soft-start can be used instead of a MOSFE. A suitable power switch I.C. for such an application would be a Micrel ( MIC0-BM or equivalent. Please note the following points in connection with power controlled designs i) he logic to be controlled must have its own reset circuitry so that it will automatically reset itself when power is reapplied on coming out of suspend. ii) Set the Pull-down on Suspend option in the internal EEPROM. iii) One of the CBUS Pins should be configured as PWRE# in the internal EEPROM. iv) For USB high-power bus powered device (one that consumes greater than 00mA, and up to 00mA of current from the USB bus), the power consumption of the device should be set in the max power field in the internal EEPROM. A high-power bus powered device must use this descriptor in the internal EEPROM to inform the system of its power requirements. v) For.V power controlled circuits the VCCIO pin must not be powered down with the external circuitry (the PWRE# signal gets its VCC supply from VCCIO). Either connect the power switch between the output of the.v regulator and the external.v logic or power VCCIO from the VOU pin of the FR. FR USB UAR I.C. atasheet Version 0.94 Future echnology evices International Ltd. 00