- Windows 98 and Windows 98 SE. - Windows 2000 / ME / XP. - Linux 2.40 and greater. - USB RS422 / RS485 Converters

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1 USB UART ( USB - Serial) I.. The is the nd generation of FTI s popular USB UART I.. This device not only adds extra functionality to its FT8U3AM predecessor and reduces external component count, but also maintains a high degree of pin compatibility with the original, making it easy to upgrade or cost reduce existing designs as well as increasing the potential for using the device in new application areas..0 Features HARWARE FEATURES Single hip USB Asynchronous Serial ata IRTUAL OM PORT (P) RIERS for Transfer - Windows 98 and Windows 98 SE Full Handshaking & Modem Interface Signals - Windows 000 / ME / XP UART I/F Supports / 8 Bit ata, / Stop Bits - Windows E and Odd/Even/Mark/Space/o Parity - MA OS-8 and OS-9 ata rate 300 => 3M Baud (TTL) - MA OS-X ata rate 300 => M Baud (RS3) - Linux.0 and greater ata rate 300 => 3M Baud (RS/RS85) XX (USB irect rivers + LL S/W Interface) 38 Byte Receive Buffer / 8 Byte Transmit Buffer - Windows 98 and Windows 98 SE for high data throughput - Windows 000 / ME / XP Adjustable RX buffer timeout APPLIATIO AREAS Fully Assisted Hardware or X-On / X-Off - USB RS3 onverters Handshaking - USB RS / RS85 onverters In-built support for event characters and line break - Upgrading RS3 Legacy Peripherals to USB condition - ellular and ordless Phone USB data transfer Auto Transmit Buffer control for RS85 cables and interfaces Support for USB Suspend / Resume through - Interfacing MU based designs to USB SLEEP# and RI# pins - USB Audio and Low Bandwidth ideo data transfer Support for high power USB Bus powered devices - PA USB data transfer through PWRE# pin - USB Smart ard Readers Integrated level converter on UART and control - Set Top Box (S.T.B.) P - USB interface signals for interfacing to 5 and 3.3 logic - USB Hardware Modems Integrated 3.3 regulator for USB IO - USB Wireless Modems Integrated Power-On-Reset circuit - USB Instrumentation Integrated 6MHz 8Mhz clock multiplier PLL - USB Bar ode Readers USB Bulk or Isochronous data transfer modes.35 to 5.5 single supply operation UHI / OHI / EHI host controller compatible USB. and USB.0 compatible USB I, PI, Serial umber and Product escription strings in external EEPROM EEPROM programmable on-board via USB ompact 3-L LQFP package S3B ersion.6 Future Technology evices Intl. Ltd. 00 Page of 5

2 .0 Enhancements USB UART ( USB - Serial) I.. This section summarises the enhancements of the nd generation device compared to its FT8U3AM predecessor. For further details, consult the device pin-out description and functional descriptions. Integrated Power-On-Reset (POR) ircuit The device now incorporates an internal POR function. The existing RESET# pin is maintained in order to allow external logic to reset the device where required, however for many applications this pin can now simply be hard wired to. In addition, a new reset output pin (RSTOUT#) is provided in order to allow the new POR circuit to provide a stable reset to external MU and other devices. RSTOUT# was the TEST pin on the previous generation of devices. Integrated RLK ircuit In the previous devices, an external R circuit was required to ensure that the oscillator and clock multiplier PLL frequency was stable prior to enabling the clock internal to the device. This circuit is now embedded on-chip the pin assigned to this function is now designated as the TEST pin and should be tied to for normal operation. This gating is now done on-chip - USBE has now been replaced with the new PWRE# signal which can be used to directly drive a transistor or P-hannel MOSFET in applications where power switching of external circuitry is required. A new EEPROM based option makes the device pull gently down its UART interface lines when the power is shut off (PWRE# is High). In this mode, any residual voltage on external circuitry is bled to when power is removed thus ensuring that external circuitry controlled by PWRE# resets reliably when power is restored. Lower Suspend urrent Integration of RLK within the device and internal design improvements reduce the suspend current of the to under 00uA (excluding the.5k pull-up on USBP) in USB suspend mode. This allows greater margin for peripherals to meet the USB Suspend current limit of 500uA. Integrated Level onverter on UART interface and control signals The previous devices would drive the UART and control signals at 5 MOS logic levels. The new device has a separate -IO pin allowing the device to directly interface to 3.3 and other logic families without the need for external level converter I.. s Improved Power Management control for USB Bus Powered, high current devices The previous devices had a USBE pin, which became active when the device was enumerated by USB. To provide power control, this signal had to be externally gated with SLEEP# and RESET#. Support for USB Isochronous Transfers Whilst USB Bulk transfer is usually the best choice for data transfer, the scheduling time of the data is not guaranteed. For applications where scheduling latency takes priority over data integrity such as transferring audio and low bandwidth video data, the new device now offers an option of USB Isochronous transfer via an option bit in the EEPROM. S3B ersion.6 Future Technology evices Intl. Ltd. 00 Page of 5

3 USB UART ( USB - Serial) I.. Programmable Receive Buffer Timeout In the previous device, the receive buffer timeout used to flush remaining data from the receive buffer was fixed at 6ms timeout. This timeout is now programmable over USB in ms increments from ms to 55ms, thus allowing the device to be better optimised for protocols requiring faster response times from short data packets. TXE Timing fix TXE timing has now been fixed to remove the external delay that was previously required for RS85 applications at high baud rates. TXE now works correctly during a transmit send-break condition. Relaxed ecoupling The nd generation devices now incorporate a level of on-chip decoupling. Though this does not eliminate the need for external decoupling capacitors, it significantly improves the ease of PB design requirements to meet F, E and other EMI related specifications. Improved PreScaler ranularity The previous version of the Prescaler supported division by (n + 0), (n + 0.5), (n + 0.5) and (n + 0.5) where n is an integer between and 6,38 ( ). To this we have added (n ), (n ), (n + 0.5) and (n+ 0.85) which can be used to improve the accuracy of some baud rates and generate new baud rates which were previously impossible (especially with higher baud rates). Bit Bang Mode The nd generation device has a new option referred to as Bit Bang mode. In Bit Bang mode, the eight UART interface control lines can be switched between UART interface mode and an 8-bit Parallel IO port. ata packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by the prescaler setting. As well as allowing the device to be used stand-alone as a general purpose IO controller for example controlling lights, relays and switches, some other interesting possibilities exist. For instance, it may be possible to connect the device to an SRAM configurable FPA as supplied by vendors such as Altera and Xilinx. The FPA device would normally be un-configured (i.e. have no defined function) at power-up. Application software on the P could use Bit Bang Mode to download configuration data to the FPA which would define its hardware function, then after the FPA device is configured the can switch back into UART interface mode to allow the programmed FPA device to communicate with the P over USB. This approach allows a customer to create a generic USB peripheral who s hardware function can be defined under control of the application software. The FPA based hardware can be easily upgraded or totally changed simply by changing the FPA configuration data file. Application notes, software and development modules for this application area will be available from FTI and other 3 rd parties. PreScaler ivide By Fix The previous device had a problem when the integer part of the divisor was set to. In the nd generation device setting the prescaler value to gives a baud rate of million baud and setting it to zero gives a baud rate of 3 million baud. oninteger division is not supported with divisor values of 0 and. S3B ersion.6 Future Technology evices Intl. Ltd. 00 Page 3 of 5

4 USB UART ( USB - Serial) I.. Less External Support omponents As well as eliminating the RLK R network, and for most applications the need for an external reset circuit, we have also eliminated the requirement for a 00K pull-up on EES to select 6MHz operation. When the is being used without the configuration EEPROM, EES, EESK and EEATA can now be left n/c. For circuits requiring a long reset time (where the device is reset externally using a reset generator I.., or reset is controlled by the IO port of a MU, FPA or ASI device) an external transistor circuit is no longer required as the.5k pull-up resistor on USBP can be wired to the RSTOUT# pin instead of to 3.3. ote : RSTOUT# drives out at 3.3 level, not at 5 level. This is the preferred configuration for new designs. Multiple evice Support without EEPROM When no EEPROM (or a blank or invalid EEPROM) is attached to the device, the no longer gives a serial number as part of its USB descriptor. This allows multiple devices to be simultaneously connected to the same P. However, we still highly recommend that EEPROM is used, as without serial numbers a device can only be identified by which hub port in the USB tree it is connected to which can change if the end user re-plugs the device into a different port. Extended EEPROM Support The previous generation of devices only supported EEPROM of type 936 (6 x 6 bit). The new devices will also work with EEPROM type 9356 (8 x 6 bit) and 9366 (56 x 6 bit). The extra space is not used by the device, however it is available for use by other external MU / logic whilst the is being held in reset. USB.0 (full speed option) A new EEPROM based option allows the to return a USB.0 device descriptor as opposed to USB.. ote : The device would be a USB.0 Full Speed device (Mb/s) as opposed to a USB.0 High Speed device (80Mb/s). S3B ersion.6 Future Technology evices Intl. Ltd. 00 Page of 5

5 USB UART ( USB - Serial) I Block iagram (Simplified) PWRTL SLEEP# PWRE# 8MHz Baud Rate enerator 33OUT USBP USBM 3.3 olt LO Regulator USB Transceiver Serial Interface Engine ( SIE ) ual Port TX Buffer 8 bytes USB Protocol Engine UART FIFO ontroller UART TX RX RTS# TS# TR# SR# # RI# TXE TXLE# RXLE# USB PLL ual Port RX Buffer 38 Bytes XTOUT XTI 6MHZ Oscillator x8 lock Multiplier 8MHz MHz RESET# 33OUT RESET EERATOR EEPROM Interface EES EESK EEATA RSTOUT# TEST 3. Functional Block escriptions 3.3 LO Regulator The 3.3 LO Regulator generates the 3.3 volt reference voltage for driving the USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the 33OUT regulator output pin. It also provides 3.3 power to the RSTOUT# pin. The main function of this block is to power the USB Transceiver and the Reset enerator ells rather than to power external logic. However, external circuitry requiring 3.3 nominal at a current of not greater than 5mA could also draw its power from the 33OUT pin if required. and two single ended receivers provide USB data in, SEO and USB Reset condition detection. USB PLL The USB PLL cell locks on to the incoming RZI USB data and provides separate recovered clock and data signals to the SIE block. 6MHz Oscillator The 6MHz Oscillator cell generates a 6MHz reference clock input to the x8 lock multiplier from an external 6MHz crystal or ceramic resonator. USB Transceiver The USB Transceiver ell provides the USB. / USB.0 full-speed physical interface to the USB cable. The output drivers provide 3.3 volt level slew rate control signalling, whilst a differential receiver S3B ersion.6 Future Technology evices Intl. Ltd. 00 Page 5 of 5

6 USB UART ( USB - Serial) I.. x8 lock Multiplier The x8 lock Multiplier takes the 6MHz input from the Oscillator cell and generates a MHz reference clock for the SIE, USB Protocol Engine and UART FIFO controller blocks. It also generates a 8MHz reference clock for the USB PPL and the Baud Rate enerator blocks. Serial Interface Engine (SIE) The Serial Interface Engine (SIE) block performs the Parallel to Serial and Serial to Parallel conversion of the USB data. In accordance to the USB.0 specification, it performs bit stuffing / unstuffing and R5 / R6 generation / checking on the USB data stream. USB Protocol Engine The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the low level USB protocol (hapter 9) requests generated by the USB host controller and the commands for controlling the functional parameters of the UART. ual Port TX Buffer (8 bytes) ata from the USB data out endpoint is stored in the ual Port TX buffer and removed from the buffer to the UART transmit register under control of the UART FIFO controller. ual Port RX Buffer (38 bytes) ata from the UART receive register is stored in the ual Port RX buffer prior to being removed by the SIE on a USB request for data from the device data in endpoint. UART FIFO ontroller The UART FIFO controller handles the transfer of data between the ual Port RX and TX buffers and the UART transmit and receive registers. of the data on the RS3 (RS and RS85) interface. ontrol signals supported by the UART include RTS, TS, SR, TR, and RI. The UART provides a transmitter enable control signal (TXE) to assist with interfacing to RS85 transceivers. The UART supports RTS/ TS, SR/TR and X-On/X-Off handshaking options. Handshaking, where required, is handled in hardware to ensure fast response times. The UART also supports the RS3 BREAK setting and detection conditions. Baud Rate enerator The Baud Rate enerator provides a x6 clock input to the UART from the 8MHz reference clock and consists of a bit prescaler and 3 register bits which provide fine tuning of the baud rate (used to divide by a number plus a fraction). This determines the Baud Rate of the UART which is programmable from 83 baud to 3 million baud. RESET enerator The Reset enerator ell provides a reliable power-on reset to the device internal circuitry on power up. An additional RESET# input and RSTOUT# output are provided to allow other devices to reset the or the to reset other devices respectively. uring reset, RSTOUT# is driven low, otherwise it drives out at the 3.3 provided by the onboard regulator. RSTOUT# can be used to control the.5k pull-up on USBP directly where delayed USB enumeration is required. It can also be used to reset other devices. RSTOUT# will stay highimpedance for approximately 5ms after has risen above 3.5 A the device oscillator is running A RESET# is high. RESET# should be tied to unless it is a requirement to reset the device from external logic or an external reset generator i.c. UART The UART performs asynchronous / 8 bit Parallel to Serial and Serial to Parallel conversion S3B ersion.6 Future Technology evices Intl. Ltd. 00 Page 6 of 5

7 USB UART ( USB - Serial) I.. EEPROM Interface Though the will work without the optional EEPROM, an external 936 (9356 or 9366) EEPROM can be used to customise the USB I, PI, Serial umber, Product escription Strings and Power escriptor value of the for OEM applications. Other parameters controlled by the EEPROM include Remote Wake Up, Isochronous Transfer Mode, Soft Pull own on Power-Off and USB.0 descriptor modes. The EEPROM should be a 6 bit wide configuration such as a Microhip 93L6B or equivalent capable of a Mb/s clock rate at =.35 to 5.5. The EEPROM is programmableon board over USB using a utility available from FTI s web site ( This allows a blank part to be soldered onto the PB and programmed as part of the manufacturing and test process. If no EEPROM is connected (or the EEPROM is blank), the will use its built-in default I, PI Product escription and Power escriptor alue. In this case, the device will not have a serial number as part of the USB descriptor..0 evice Pin-Out EESK EEATA RESET# RSTOUT# 33OUT USBP USBM 8 EES 3 TEST SLEEP# A RXLE# A TXLE# XTOUT IO XTI PWRTL PWRE# TX 5 FTI XXYY 9 6 TXE RX RTS# TS# TR# SR# # RI# OUT USBM USBP RSTOUT# RESET# XTI XTOUT EES EESK EEATA TEST A A 9 9 I O TX RX RTS# TS# TR# SR# # RI# TXE TXLE# RXLE# PWRTL PWRE# SLEEP# Figure Pin-Out (LQFP-3 Package ) Figure Pin-Out (Schematic Symbol ) S3B ersion.6 Future Technology evices Intl. Ltd. 00 Page of 5

8 USB UART ( USB - Serial) I... Signal escriptions Table - - PIOUT ESRIPTIO UART ITERFAE ROUP Pin# Signal Type escription 5 TX OUT Transmit Asynchronous ata Output RX I Receive Asynchronous ata Input 3 RTS# OUT Request To Send ontrol Output / Handshake signal TS# I lear To Send ontrol Input / Handshake signal TR# OUT ata Terminal Ready ontrol Output / Handshake signal 0 SR# I ata Set Ready ontrol Input / Handshake signal 9 # I ata arrier etect ontrol Input 8 RI# I Ring Indicator ontrol Input. When the Remote Wakeup option is enabled in the EEPROM, taking RI# low can be used to resume the P USB Host controller from suspend. 6 TXE OUT Enable Transmit ata for RS85 USB ITERFAE ROUP Pin# Signal Type escription USBP I/O USB ata Signal Plus ( Requires.5k pull-up to 33OUT or RSTOUT# ) 8 USBM I/O USB ata Signal Minus EEPROM ITERFAE ROUP Pin# Signal Type escription 3 EES I/O EEPROM hip Select. For 8MHz operation pull EES to using a 0K resistor. For 6MHz operation no resistor is required. Tri-State during device reset. **ote EESK OUT lock signal to EEPROM. Tri-State during device reset, else drives out. Adding a 0K pull down resistor onto EESK will cause the to use USB Product I 600 (hex) instead of 600 (hex). All of the other USB device descriptors are unchanged.**ote EEATA I/O EEPROM ata I/O onnect directly to ata-in of the EEPROM and to ata- Out of the EEPROM via a.k resistor. Also, pull ata-out of the EEPROM to via a 0K resistor for correct operation. Tri-State during device reset. **ote S3B ersion.6 Future Technology evices Intl. Ltd. 00 Page 8 of 5

9 POWER OTROL ROUP Pin# Signal Type escription USB UART ( USB - Serial) I.. 0 SLEEP# OUT oes Low during USB Suspend Mode. Typically used to power-down an external TTL to RS3 level converter i.c. in USB <=> RS3 converter designs. 5 PWRE# OUT oes Low after the device is configured via USB, then high during USB suspend. an be used to control power to external logic using a P-hannel Logic Level MOSFET switch. Enable the Interface Pull-own Option in EEPROM when using the PWRE# pin in this way. PWRTL I Bus Powered Tie Low / Self Powered Tie High (to IO) MISELLAEOUS SIAL ROUP Pin# Signal Type escription RESET# I an be used by an external device to reset the. If not required, tie to. 5 RSTOUT# OUT Output of the internal Reset enerator. Stays high impedance for ~ 5ms after > 3.5 and the internal clock starts up, then clamps its output to the 3.3v output of the internal regulator. Taking RESET# low will also force RSTOUT# to drive low. RSTOUT# is OT affected by a USB Bus Reset. TXLE# O.. LE rive - Pulses Low when Transmitting ata via USB RXLE# O.. LE rive - Pulses Low when Receiving ata via USB XTI I Input to 6MHz rystal Oscillator ell. This pin can also be driven by an external 6MHz clock if required. ote : Switching threshold of this pin is /, so if driving from an external source, the source must be driving at 5 MOS level or a.c. coupled to centre around /. 8 XTOUT OUT Output from 6MHz rystal Oscillator ell. XTOUT stops oscillating during USB suspend, so take care if using this signal to clock external logic. 3 TEST I Puts device in I.. test mode must be tied to for normal operation. POWER A ROUP Pin# Signal Type escription 6 33OUT OUT 3.3 volt Output from the integrated L..O. regulator This pin should be decoupled to using a 33nF ceramic capacitor in close proximity to the device pin. Its prime purpose is to provide the internal 3.3 supply to the USB transceiver cell and the RSTOUT# pin. A small amount of current (<= 5mA) can be drawn from this pin to power external 3.3v logic if required. 3,6 PWR +.35 volt to +5.5 volt to the device core, LO and non-uart interface pins. 3 IO PWR +3.0 volt to +5.5 volt to the UART interface pins 0..,..6 and When interfacing with 3.3 external logic in a bus powered design connect IO to a 3.3 supply generated from the USB bus. When interfacing with 3.3 external logic in a self powered design connect IO to the 3.3 supply of the external logic. Otherwise connect to to drive out at 5 MOS level. 9, PWR evice - round Supply Pins 30 A PWR evice - Analog Power Supply for the internal x8 clock multiplier 9 A PWR evice - Analog round Supply for the internal x8 clock multiplier **ote - uring device reset, these pins are tri-state but pulled up to via internal 00K resistors. S3B ersion.6 Future Technology evices Intl. Ltd. 00 Page 9 of 5

10 USB UART ( USB - Serial) I Package Outline Figure 3 3 L LQFP Package imensions 3 9 Pin # FTI XXYY o +/- o 0.3 +/ MAX. +/ Min 0. Max / Min 0.6 Max 0.05 Min 0.5 Max 0. Min 0.6 +/- 0.5 The is supplied in a 3 L LQFP package as standard. This package has a mm x mm body ( 9mm x 9mm including leads ) with leads on a 0.8mm pitch. A lead free version is available on special request. An alternative 5mm x 5mm leadless chip scale package (.S.P.) is also available on special request for projects where package area is critical. ontact support@ftdichip.com for package details and availability. The above drawing shows the LQFP-3 package all dimensions are in millimetres. XXYY = ate ode where XX = digit year number, YY = digit week number; or XYY- where X = digit year number, YY = digit week number. S3B ersion.6 Future Technology evices Intl. Ltd. 00 Page 0 of 5

11 6.0 Absolute Maximum Ratings USB UART ( USB - Serial) I.. These are the absolute maximum ratings for the device in accordance with the Absolute Maximum Rating System (IE 603). Exceeding these may cause permanent damage to the device. Storage Temperature o to + 50 o Floor Life (Out of Bag) at Factory Ambient (30 o /60% Relative Humidity)...9 Hours **ote (Level 3 ompliant) Ambient Temperature (Power Applied)... 0 o to + 0 o M.T.B.F. (at 35 o ).. Years Supply oltage to Input oltage - Inputs to Input oltage - High Impedance Bidirectionals to Output urrent Outputs... ma Output urrent Low Impedance Bidirectionals... ma Power issipation ( = 5.5) mW Electrostatic ischarge oltage (Human Body Model) (I < ua)... +/ Latch Up urrent (i = +/- 0 maximum, for 0 ms)... +/-00mA **ote If devices are stored out of the packaging beyond this time limit the devices should be baked before use. The devices should be ramped up to a temperature of 0 o and baked for 8 to 0 hours haracteristics haracteristics ( Ambient Temperature = 0 to 0 o ) Operating oltage and urrent Parameter escription Min Typ Max Units onditions cc Operating Supply oltage cc IO Operating Supply oltage Icc Operating Supply urrent ma ormal Operation Icc Operating Supply urrent ua USB Suspend **ote 3 **ote 3 Supply current excludes the 00uA nominal drawn by the external pull-up resistor on USBP. UART IO Pin haracteristics ( IO = 5.0 ) Parameter escription Min Typ Max Units onditions oh Output oltage High I source = ma ol Output oltage Low I sink = ma in Input Switching Threshold **ote Hys Input Switching Hysteresis m S3B ersion.6 Future Technology evices Intl. Ltd. 00 Page of 5

12 USB UART ( USB - Serial) I.. UART IO Pin haracteristics ( IO = ) Parameter escription Min Typ Max Units onditions oh Output oltage High.. 3. I source = ma ol Output oltage Low I sink = ma in Input Switching Threshold.0..5 **ote Hys Input Switching Hysteresis m **ote Inputs have an internal 00K pull-up resistor to IO. XTI / XTOUT Pin haracteristics Parameter escription Min Typ Max Units onditions oh Output oltage High Fosc = 6MHz ol Output oltage Low Fosc = 6MHz in Input Switching Threshold RESET#, TEST, EES, EESK, EEATA Pin haracteristics Parameter escription Min Typ Max Units onditions oh Output oltage High I source = ma ol Output oltage Low I sink = ma in Input Switching Threshold **ote 5 Hys Input Switching Hysteresis m **ote 5 EES, EESK and EEATA pins have an internal 00K pull-up resistor to RSTOUT Pin haracteristics Parameter escription Min Typ Max Units onditions oh Output oltage High I source = ma ol Output oltage Low I sink = ma USB IO Pin haracteristics Parameter escription Min Typ Max Units onditions Uoh IO Pins Static Output ( High) RI =.5K to 33Out ( + ) RI = 5K to ( - ) Uol IO Pins Static Output ( Low ) RI =.5K to 33Out ( + ) RI = 5K to ( - ) Use Single Ended Rx Threshold Uom ifferential ommon Mode Uif ifferential Input Sensitivity 0. UrvZ river Output Impedance 9 Ohm **ote 5 **ote 5 river Output Impedance includes the external R series resistors on USBP and USBM pins. S3B ersion.6 Future Technology evices Intl. Ltd. 00 Page of 5

13 USB UART ( USB - Serial) I...0 evice onfiguration Examples. Oscillator onfigurations Figure 3-Pin eramic Resonator onfiguration Figure 5 rystal or -Pin eramic Resonator onfiguration FT3BM pf XTI XTI 3-Pin Resonator 6MHz M - Pin Resonator or rystal 6MHz pf 8 XTOUT 8 XTOUT Figure illustrates how to use the with a 3-Pin eramic Resonator. A suitable part would be a ceramic resonator from Murata s ERALOK range. (Murata Part umber STR6M005), or equivalent. 3-Pin ceramic resonators have the load capacitors built into the resonator so no external loading capacitors are required. This makes for an economical configuration. The accuracy of this Murata ceramic resonator is +/- 0.% and it is specifically designed for USB full speed applications. A MegaOhm loading resistor across XTI and XTOUT is recommended in order to guarantee this level of accuracy. Other ceramic resonators with a lesser degree of accuracy (typically +/- 0.5%) are technically out-with the USB specification, but it has been calculated that using such a device will work satisfactorily in practice with a design. Figure 5 illustrates how to use the with a 6MHz rystal or -Pin eramic Resonator. In this case, these devices do not have in-built loading capacitors so these have to be added between XTI, XTOUT and as shown. A value of pf is shown as the capacitor in the example this will be good for many crystals and some resonators but do select the value based on the manufacturers recommendations wherever possible. If using a crystal, use a parallel cut type. If using a resonator, see the previous note on frequency accuracy. S3B ersion.6 Future Technology evices Intl. Ltd. 00 Page 3 of 5

14 USB UART ( USB - Serial) I... EEPROM onfiguration Figure 6 EEPROM onfiguration k 0k 3 EES EESK EEATA EEPROM / 56 / 66 8 S SK 3 6 I 5 OUT Figure 6 illustrates how to connect the to the 936 (9356 or 9366) EEPROM. EES (pin 3) is directly connected to the chip select (S) pin of the EEPROM. EESK (pin ) is directly connected to the clock (SK) pin of the EEPROM. EEATA (pin ) is directly connected to the ata In (in) pin of the EEPROM. There is a potential condition whereby both the ata Output (out) of the EEPROM can drive out at the same time as the EEATA pin of the. To prevent potential data clash in this situation, the out of the EEPROM is connected to EEATA of the via a.k resistor. Following a power-on reset or a USB reset, the will scan the EEPROM to find out (a) if an EEPROM is attached to the evice and (b) if the data in the device is valid. If both of these are the case, then the will use the data in the EEPROM, otherwise it will use its built-in default values. When a valid command is issued to the EEPROM from the, the EEPROM will acknowledge the command by pulling its out pin low. In order to check for this condition, it is necessary to pull out high using a 0K resistor. If the command acknowledge doesn t happen then EEATA will be pulled high by the 0K resistor during this part of the cycle and the device will detect an invalid command or no EEPROM present. There are two varieties of these EEPROM s on the market one is configured as being 6 bits wide, the other is configured as being 8 bits wide. These are available from many sources such as Microchip, STMicro, ISSI etc. The requires EEPROM s with a 6-bit wide configuration such as the Microchip 93L6B device. The EEPROM must be capable of reading data at a Mb clock rate at a supply voltage of.35 to 5.5. Most available parts are capable of this. heck the manufacturers data sheet to find out how to connect pins 6 and of the EEPROM. Some devices specify these as no-connect, others use them for selecting 8 / 6 bit mode or for test functions. Some other parts have their pinout rotated by 90 o so please select the required part and its options carefully. It is possible to share the EEPROM between the and another external device such as an MU. However, this can only be done when the is in its reset condition as it tri-states its EEPROM interface at that time. A typical configuration would use four bit s of an MU IO Port. One bit would be used to hold the reset (using RESET#) on power-up, the other three would connect to the EES, EESK and EEATA pins of the in order to read / write data to the EEPROM at this time. Once the MU has read / written the EEPROM, it would take RESET# high to allow the to configure itself and enumerate over USB. S3B ersion.6 Future Technology evices Intl. Ltd. 00 Page of 5

15 .3 USB Bus Powered and Self Powered onfiguration Figure USB Bus Powered onfiguration USB UART ( USB - Serial) I.. USB "B" onnector 3 Ferrite Bead R R 0nF 6 33nF v3OUT I O 0R 30 A 8 USB M USB P k5 + 5 RSTOUT# RESET# POWERTL A 0uF 9 9 ecoupling apacitors Figure illustrates a typical USB bus powered configuration. A USB Bus Powered device gets its power from the USB bus. Basic rules for USB Bus power devices are as follows a) On plug-in, the device must draw no more than 00mA b) On USB Suspend the device must draw no more than 500uA. c) A Bus Powered High Power evice (one that draws more than 00mA) should use the PWRE# pin to keep the current below 00mA on plug-in and 500uA on USB suspend. d) A device that consumes more than 00mA can not be plugged into a USB Bus Powered Hub e) o device can draw more that 500mA from the USB Bus. PWRTL (pin ) is pulled low to tell the device to use a USB Bus Power descriptor. The power descriptor in the EEPROM should be programmed to match the current draw of the device. A Ferrite Bead is connected in series with USB power to prevent noise from the device and associated circuitry (EMI) being radiated down the USB cable to the Host. The value of the Ferrite Bead depends on the total current required by the circuit a suitable range of Ferrite Beads is available from Steward ( for example Steward Part # MI0805K00R-00 also available as igikey Part # S3B ersion.6 Future Technology evices Intl. Ltd. 00 Page 5 of 5