Building Blocks for Rapid Communication System Development

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1 White Paper Introduction The explosive growth of the Internet has placed huge demands on the communications industry to rapidly develop and deploy new products that support a wide array of protocols with a highly flexible architecture. The aggregate amount of Internet data traffic continues to climb as new subscribers go online at a rapid rate, and individual subscribers consume more data through graphic rich web sites, large file transfers, and streaming video content. The need for increased bandwidth over the last mile from the home to the central office has been well documented, and the gradual deployment of DSL and cable modem infrastructure has started to satisfy some of the consumer demand. Aggregate backbone capacity continues to increase as fiber optic cable is deployed at a rapid rate, while the data rate of individual channels accelerates from Optical Carrier Level 12 (OC-12) to OC-48 and OC-192, and the number of data streams carried on each fiber expands through advancements in Dense Wavelength Division Multiplexing (DWDM) technologies. Although the demand for more bandwidth by subscribers has accelerated the rate of growth of network backbone capacity, the impact at the edge of the network has been more profound. To remain competitive, communication system manufacturers developing products at the edge of the network need to rapidly develop systems that support the growing list of access services being deployed, including the newer services such as DSL and cable modem, existing 56 Kbps dial-up, and the traditional T/E-carrier services used by business subscribers. A variety of different protocols need to be supported on top of these transmission media, including Frame Relay, Asynchronous Transfer Mode (ATM) and Point-to-Point Protocol (PPP). With continuous change on both sides of the edge of the network, there is an absolute requirement for flexible architectures in Metropolitan Area Network (MAN) equipment, including terminal/access multiplexers, edge routers, edge switches, and Synchronous Optical Network (SONET) / Synchronous Digital Hierarchy (SDH) add-drop multiplexers. Implementation Options Vendors of Application Specific Standard Products (ASSPs) have attempted to satisfy these needs with chipset families and multi-mode products. These products can be low-cost, high-performance, advantageous solutions for some applications, but disadvantageous in many other instances. First, ASSPs usually require multi-chip solutions, increasing board space and power consumption. This is because individual ASSPs typically provide one or two primary functions such as SONET/SDH framing and ATM cell delineation. However, neighboring functions such as traffic management and switching require additional chips, for an overall two- or three-chip solution. Second, individual ASSPs are often targeted to a broad audience with several similar functions included in a single chip. For example, ASSPs are available for SONET/SDH Virtual Tributary (VT) mapping, but these chips typically provide VT-1.5, VT-2, VT-3 and VT-6 mapping, though users typically require only one of these functions for a given product implementation. As such, users pay for gates that they do not require, and are burdened with complicated software programming for these multi-mode chips. These problems can be addressed through the use of high-density Programmable Logic Devices (PLDs). PLDs can integrate several functions, such as the SONET/SDH framer, ATM cell delineator, traffic manager and switch, into a single device. Also, users of PLDs can select only the functions they require, and consume only the gates needed for their application. Reducing gate consumption lowers device costs, facilitates a higher level of integration in a single PLD, and yields a more efficient system design. To ease the integration of distinct IP cores, each function should be designed as part of a larger family with a strong architectural approach to partitioning and interfaces. A broad portfolio of configurable functions with standardized A-WP-RapidCom-01 March 2001, ver

2 interfaces is required. System designers could then select the functions they require, configure them to their specific requirements, and simply connect the customized cores and proprietary user-logic (through standardized interfaces) for a highly efficient unique design. For example, many companies design line cards that support the transport of either ATM cells or PPP packets over SONET/SDH at a variety of different data rates (155 Mbps, 622 Mbps, and 2.5 Gbps). The transmission convergence layer of these line cards can be partitioned into two distinct functions, SONET/ SDH framing, and ATM cell or PPP packet delineation. ASSP solutions are available that support either the transport of cells or packets over SONET/SDH as a software configuration option. This approach is not ideal because only one mode (cell or packet) is used for a given line card though the board is populated with the larger device capable of both modes and entirely different chips are required for different data rates. Communications IP for Programmable Logic Altera has invested heavily in the development of intellectual property (IP) cores that are optimized for PLDs, and provide the highest degree of flexibility possible. Altera MegaCore functions can be configured prior to synthesis through a MegaWizard Plug-In, an easy-to-use graphical user interface which allows designers to quickly and easily eliminate features that are not required, thus reducing device consumption and simplifying software integration. Configurable MegaCore functions for SONET/SDH framing, ATM cell processing, and PPP packet processing are available as programmable logic. Each core can be configured before synthesis to eliminate unused features. The SONET/SDH framers can be configured with or without serial insertion and extraction of transport overhead (TOH) and path overhead (POH) bytes through hardware, section trace (J0 byte) monitoring, path trace (J1 byte) monitoring, and bit error rate (one second window) monitoring. The ATM cell processors provide cell delineation, and optional gates for cell insertion and extraction, performance monitoring, and up to four generic cell filters, which can be used to monitor a specific subscriber s traffic (for trouble shooting), or to manage Operations, Administration and Maintenance (OAM) flows. The PPP packet processors provide the byte-oriented HDLC-like framing used in the transport convergence layer of Packet over SONET/SDH (PoS). System developers have been forced to use either a chipset from a single ASSP vendor, or to use ASSPs from a variety of vendors, often requiring additional chips to bridge the incompatible interfaces. To avoid similar problems while integrating IP cores, developers should follow a plug and play model by using standard interfaces between the IP cores. Altera has developed and published three such interfaces: the Middle (Midbus) interface, the Access to Internal Registers (AIRbus) interface, and the Atlantic. Figure 1 below illustrates the usage of these interfaces in four typical applications ATM or Packet over SONET/SDH at STS-3c/STM-1 or STS-12c/STM-4. Figure 1. Typical Applications ATM or Packet over SONET/SDH, and STS-12c/STM-4 or STS-3c/STM-1. Fiber Optic Module Clock Data Recovery rxclk SER/DES Midbus Atlantic ATM Cell SONET/SDH or Framer PPP Packet Processor User Logic Atlantic UTOPIA or POSPHY External CPU txclk CPU Bus Processor AIRbus PLD Boundary Inventory costs can be minimized, while retaining flexibility, by storing multiple device programming files in flash memory (four in this example). The PLD can be programmed at boot-up of the line card with the appropriate configuration (ATM over SONET/SDH STS-12c/STM-4, Packet over SONET/SDH STS-12c/STM-4, ATM over SONET/ SDH STS-3c/STM-1, or Packet over SONET/SDH STS-3c/STM-1). User logic in these examples could be traffic management, routing and switching functions. Standard bus interface IP cores are also available for the data path, 2

3 including POSPHY and UTOPIA, as well as PCI interfaces that are often used as the processor interface across the backplane. By loading the PLD with only the required gates (one of four programming files in this example), the PLD size is minimized, while the same PLD supports each operating mode. T3 framing, T3 mapping, and E3 mapping functions that compliment the Altera SONET/SDH, ATM, and PPP cores are also available. Because these cores are designed with standard interfaces, they can be easily connected in a variety of configurations for different applications. For example, T3 channels can be mapped asynchronously into SONET/ SDH using the T3 mapper and the SONET/SDH framer, and if required for the application, frame alignment information can be made available by adding the T3 framer to the design. Alternatively, a T3 line can be used to transport cells or packets, by combining the T3 framer with either the ATM cell processor, or the PPP packet processor. Full duplex T1 and E1 framer cores and VT-1.5 and VT-2 mapper cores are planned for later this year (2001). In addition to single channel designs, configuration options for multi-channel support will be provided, including up to 84 channels for T1 framing and VT-1.5 mapping, and 63 channels for E1 framing and VT-2 mapping. Time slicing design techniques will be used to optimize the cores for programmable logic. Figure 2 illustrates how these MegaCore functions could be used to develop a line card for a SONET/SDH add-drop multiplexer with an unprecedented level of integration. Figure 2. Typical Applications Line Card for SONET/SDH Add-Drop Mux, and 84 T1 lines Add/Dropped to/from an STS-1. T1 Line #1 T1 Line #84 Line Unit Line Unit T1 Framer Midbus VT-1.5 Mapper SONET STS-3 Framer SERDES Serial Data to/from Backplane PLD Boundary The line card referenced in Figure 2 could be connected to the backplane for STS-3 switching. Similar line cards could be used to add/drop T3 lines, replacing the T1 framer and VT-1.5 mapper with T3 framers and T3 mappers, to add/drop E3 lines using E3 framers and E3 mappers, to add/drop E1 lines using an E1 framer and VT-2 mapper, or to add/drop access lines such as DSL with user designed logic for the framing and mapping. The corresponding network card could receive the switched STS-3 signals from the backplane and multiplex them into an STS-12 for transmission over an OC-12 ring, or into an STS-48 for transmission over an OC-48 ring. In the opposite direction, the egress traffic from the OC-12 ring would be de-interleaved into twelve STS-1 signals and switched on the backplane to the applicable line card. The underlying quality of an IP core is important. Many designers have had bad experiences with IP. As discussed earlier, it can be difficult to integrate cores from one or more suppliers with proprietary user logic. Design reuse requires advanced planning and standardized interfaces, so multiple IP cores and user logic can be easily integrated. In addition, IP cores must deliver the specified functionality and performance. Altera embraces these approaches, and to assure quality, complete hardware testing of complex and high-performance cores is performed in compliance with industry standards. 3

4 Cost of Implementation The combination of a SONET framer with a 28 channel VT-1.5 mapper and 28 channel T1 framer in a single PLD would require a mid-size PLD. This highly integrated system-on-programmable-chip (SOPC) would consume approximately 18,000 logic elements (LEs) of an APEX TM 20KE device, and more specifically, 75% of a 20K600E-3 part, a device that currently lists for $460 in low volume. External Line Units (LIUs) are commercially available for approximately $12 per T1 channel, increasing the cost of this solution to $800. Implementing these functions in a PLD provides the flexibility to manage the inevitable feature creep that arises during the development process. In comparison, a solution using multiple ASSPs would require several chips, including a SONET framer, a VT mapper, and four T1 framers with integrated LIUs (three octals and one quad). This six-chip solution lists for approximately $800 in aggregate, and offers considerably less flexibility than the PLD-based solution. In addition, the software integration of the ASSP-based solution would be considerably more complex. The PLD-based solution provides a cost-competitive solution, especially if existing migration paths to high volume, lower-cost silicon from PLD vendors are considered. Altera offers a turn-key migration path to lower-cost mask programmed logic devices (HardCopy devices) for high-volume, high-density PLD designs. The HardCopy implementation process offers guaranteed functionality and performance with minimal customer involvement, samples in 6-7 weeks, and production volumes in weeks from the start of the design conversion. Using HardCopy eliminates the risks associated with manual migration from a PLD to an Application Specific Integrated Circuit (ASIC), and the up-front costs are significantly less. Design costs to migrate the PLD design outlined above to an ASIC would be in the $ K range, layout would be approximately $50K, and non-recurring manufacturing costs would be $ K depending on the technology targeted, for a total design conversion cost of $ K. This process typically takes at least 12 weeks for design and verification, 4 to 8 weeks for layout, 8 weeks for samples, 8 to 12 weeks for testing, and then 8 weeks for volume production, for a total design conversion cycle of at least 40 elapsed weeks. In addition, the risks involved with this manual process are significant, and the possibility of a re-spin is very real. In contrast, converting this PLD design to a HardCopy would require only weeks of elapsed time to volume production, the design conversion cost would be only $125K, and the HardCopy unit costs would be reduced to less than $75 in high-volume. With external LIUs costing $335, this solution would cost less than $410, compared to the competitive multi-assp solution that costs $800. Role of Embedded Processors Flexibility is also required to interface line cards with host processors. One approach would be to utilize an embedded processor in the PLD. For example, an embedded processor could be implemented in the PLD designs for the line cards described above. In addition to the lower performance soft-core processors that have been available for many years, Altera has embedded high-performance hard-core processors in PLDs. This approach does not negate the requirement for a host processor, which remains in its traditional location on the processor card. The local management of specific line card functions provides a great deal of flexibility by abstracting the actual implementation, eases the provisioning of new lines and line cards, and reduces the burden on the host processor. For example, software for the T1 framer could be processed locally on the line card, with performance monitoring statistics stored in the PLD memory resources or an external memory. The local processor would send messages to the host processor when applicable error conditions have been detected and dealt with, and provide status reports to the host processor when requested. Standard software interfaces would be developed and used with each line card, making the development of new line cards for the system a simple task, with integration completely under the control of software. 4

5 Conclusion Programmable logic has applications throughout the network. Complex functions, such as those outlined in this discussion, are easily implemented in PLDs in the data path of Metropolitan Networks, where the flexibility provided by configurable IP cores is necessary. In the backbone, where performance is at a premium, complex functions will typically be implemented initially in ASIC/ASSPs. To connect incompatible devices, or to insert proprietary user logic between the ASIC/ASSPs, Altera will offer (by mid-2001) a selection of industry standard high-speed interfaces that are optimized for PLDs, including SPI-4 Phase I (FlexBus Level 4) and SPI-4 Phase II (POSPHY Level 4). A selection of lower speed interfaces are available within a compiler, including Level 2 and Level 3, Link-side and PHY-side interfaces, with the ability to join together applicable cores for interface bridges (e.g. a bridge from a single POSPHY Level 3 Link-side interface to four POSPHY Level 2 PHY-side interfaces). UTOPIA Level 2 and Level 3 cores are also available. Using configurable MegaCore functions with proprietary logic targeted to a programmable logic device leads to the rapid development and deployment of unique products. This highly flexible approach to system design produces architectures that can be supported while network infrastructure continues to evolve to sustain the explosive growth of the Internet. 101 Innovation Drive San Jose, CA (408) Copyright 2001 Altera Corporation. Altera, APEX, MegaCore, and MegaWizard are trademarks and/or service marks of Altera Corporation in the United States and other countries. Other brands or products are trademarks of their respective holders. The specifications contained herein are subject to change without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. All rights reserved. 5

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