KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem. User Guide

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1 KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide Literature Number: SPRUGV9D June 2013

2 Release History Release Date Description/Comments SPRUGV9D June 2013 Added KeyStone I and KeyStone II to register name description, figure, and table. (Page 3-38) Clarified Collision Based Receive Flow Control paragraph. (Page 2-7) Added Port 3 and Port 4 to ESS Memory Map Table Summary. (Page 3-30) Corrected Field Descriptions to say Port 4 instead of Port 3. (Page 3-71) Corrected Register to say Port 1 instead of Port 2. (Page 3-48) Added KeyStone II Ethernet Switch Subsystem Block Diagram (Page 1-4) Updated KeyStone I Ethernet Switch Subsystem Block Diagram (Page 1-3) Added "KeyStone I and KeyStone II" to table name to clarify register purpose (Page 3-38) Added KeyStone I to Ethernet Switch Register Table caption. (Page 3-31) Added KeyStone II Ethernet Switch Register Table. (Page 3-32) Added KeyStone II Flow Control Register (FLOW_CONTROL) Register figure. (Page 3-39) Added KeyStone II Port 2 Time Sync Control Register (P2_TS_CTL) Register figure. (Page 3-54) Added KeyStone II Port 1 Time Sync Control Register (P1_TS_CTL) Register figure. (Page 3-46) Added KeyStone II Priority Type Register (PTYPE) Register figure. (Page 3-37) Added KeyStone II Statistics Port Enable (STAT_PORT_EN) Register figure. (Page 3-36) Added KeyStone II Port 0 Source Identification Register (P0_CPPI_SRC_ID) Register figure. (Page 3-40) Added P2_TS_CTL_LTYPE2 and P2_TS_CTL2 Register entries to table. (Page 3-9) Added P1_TS_CTL2 and P1_TS_CTL_LTYPE2 Register entries to table. (Page 3-9) Removed Port 0 entry. (Page 3-38) Updated KeyStone II Port 1 Time Sync Control Register (P1_TS_CTL) Field Descriptions table. (Page 3-47) Added Flow Control Register Reset Values. (Page 3-39) Added Reset value to ALE Table Control Register. (Page 3-107) Updated STAT_PORT_EN field descriptions for KeyStone II. (Page 3-36) Added KeyStone II Gigabit Ethernet Switch Subsystem Module table. (Page 3-2) Added Port 3 and Port 4 SGMII registers to the Complete Register Listing table. (Page 3-8) Corrected KeyStone II Gigabit Ethernet Switch Subsystem Complete Register Listing table to show "Reserved" for reserved addresses. (Page 3-7) Corrected KeyStone II Gigabit Ethernet Switch Subsystem Complete Register Listing table to show Reserved for certain addresses. (Page 3-11) Corrected module name to register name correspondence in the KeyStone II Gigabit Ethernet Switch Subsystem Complete Register Listing table. Some were shifted down in the column. (Page 3-13) Added "KeyStone II" to table caption. (Page 3-34) Added bit fields for KeyStone II 5-Port CPSW Control Field Descriptions. (Page 3-34) Added Port 4 Time Sync Control Register 2 (P4 _TS_CTL2) Register. (Page 3-70) Added Port 4 Time Sync Control Register and LTYPE2 (P4_TS_CTL_LTYPE2) Register tables. (Page 3-69) Added Port 3 Time Sync Control Register 2 (P3 _TS_CTL2) Register tables. (Page 3-64) Added Port 3 Time Sync Control Register and LTYPE2 (P3 _TS_CTL_LTYPE2) Register tables. (Page 3-63) Added Port 2 Time Sync Control Register 2 (P2 _TS_CTL2) Register. (Page 3-56) Added Port 2 Time Sync Control Register and LTYPE2 (P2 _TS_CTL_LTYPE2) Register. (Page 3-56) Added Port 1 Time Sync Control Register 2 (P1 _TS_CTL2) Register. (Page 3-48) Added Port 1 Time Sync Control Register and LTYPE2 (P1 _TS_CTL_LTYPE2) Register. (Page 3-48) Added STATSA/STATC entry in the KeyStone II Gigabit Ethernet Switch Subsystem Complete Register Listing table to show addresses are shared. (Page 3-12) Added information about additional EMAC submodules in KeyStone II devices. (Page 2-4) Added note about viewing STATS. (Page 2-13) Added PS_FLAGS for GbE Switch Ingress Packets table for KeyStone II devices. (Page 2-6) Added SGMII2 and SGMII3 for KeyStone II devices. (Page 1-3) Added user guide reference for KeyStone I and II devices to the Streaming Packet Interface section. (Page 2-4) Removed the Ethernet Receive Event subsection and replaced it with new, more complete material. (Page 2-29) Updated discussion of RX_CEF_EN, RX_CSF_EN, RX_CMF_EN bits. (Page 2-42) Corrected the Event Middle Register and field descriptions. (Page 3-101) Corrected MAC1 Source Address Low Register bits 15-0 field descriptions. (Page 3-45) Corrected offset address for Port 3 and Port 4 SGMII module in KeyStone II Gigabit Ethernet Switch Subsystem Modules table. (Page 2-3) ø-ii KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide SPRUGV9D June 2013

3 SPRUGV9D June 2013 Release Date Description/Comments SPRUGV9C April 2013 Added additional port 3 and port 4 related register descriptions for KeyStone II. (Page 3-57) Added KS II P2_TS_CTL Field Descriptions. (Page 3-68) Added KS II P2_TS_CTL Field Descriptions. (Page 3-61) Added KS II P2_TS_CTL Field Descriptions. (Page 3-54) Added KS II P1_TS_CTL Field Descriptions. (Page 3-47) Add KeyStone II Overrun Type II in Architecture. (Page 2-17) Added extra ports for STATSB for KeyStone II devices. (Page 2-19) Added KeyStone II Overrun Type 2 in registers. (Page 2-18) Added KeyStone II port enable in registers. (Page 3-36) Added KeyStone II Reset Considerations in Arch. (Page 2-53) Added KeyStone II SerDes Architecture section in Architecture chapter. (Page 2-53) Added KeyStone II specifics in Introduction. (Page 1-4) Added KeyStone II statistics submodule in architecture. (Page 2-13) Added KeyStone II Time Sync Event Field. (Page 2-28) Added KeyStone II Time Synchronization Submodule Architecture section. (Page 2-25) Added KeyStone II Type 3 Overrun Registers. (Page 2-19) Added Port 3 and Port 4 Interfaces note in arch. (Page 2-27) Added port 3 and port 4 MAC in Initialization for KeyStone II. (Page 2-54) Added ports to Type 2 KeyStone I Register for Keystone II. (Page 2-18) Added STATSC and STATSD module details in Overrun Type 1. (Page 2-19) Additional KeyStone II detail added to Switch Architecture. (Page 2-4) Added EVENT_MID register description. (Page 3-101) Added KeyStone II CPTS Memory Map. (Page 3-96) Added KeyStone II FLOW_CONTROL Register Description. (Page 3-39) Added Keystone II Port 0 Source ID Register. (Page 3-40) Added Keystone II PTYPE Register. (Page 3-37) Added noted about Keystone II devices Register field descriptions. (Page 3-55) Corrected Address in Memory Map. (Page 3-4) Corrected Register Addresses in Memory Map. (Page 3-10) Corrected Register Addresses in Memory Map. (Page 3-10) Corrected Register Addresses in Memory Map. (Page 3-10) Added Keystone II Features in Features list. (Page 1-2) SPRUGV9B July 2012 Updated addresses for port 1 MAC registers in GbE switch complete register listing table. (Page 3-9) Updated addresses for port 1 MAC registers in GbE switch complete register listing table. (Page 3-4) Updated the description for the SGMII SerDes LOOP_BWIDTH field. (Page 3-116) Updated the field description for the NO_LEARN bit in the ALE Port Control Register 0. (Page 3-109) Updated the field description for the SGMII SerDes RATE field. (Page 3-118) Updated the recommended settings for the SGMII SerDes EQ field description. (Page 3-118) Modified procedure description for SGMII to SGMII with Forced Link step 1b. (Page 2-49) SPRUGV9D June 2013 KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide ø-siii

4 Release Date Description/Comments SPRUGV9A July 2011 Modified the field description tables so they include all field labels shown in the related register figure and their corresponding bit numbers. (Page 3-1) Added Gigabit Ethernet Switch Subsystem Descriptor Error Flags table. (Page 2-42) Added Ratescale values table. (Page 3-116) Added SGMII_SERDES_STS Register. (Page 3-114) Changed Start of Frame statistic to Overrun Type 3 statistic and updated the description. (Page 2-19) Changed Start of Frame statistic to Overrun Type 2 statistic and updated the description. (Page 2-18) Changed Start of Frame statistic to Overrun type 1 statistic and updated the description. (Page 2-17) Updated SerDes SGMII Boot Configuration Registers to add SGMII_SERDES_STS register. (Page 3-114) Updated VRANGE field description in the SGMII PLL Configuration Register. (Page 3-116) Updated procedure for setting up the SGMII in master mode with autonegotiation. (Page 2-48) Updated procedure for setting up the SGMII in slave mode with autonegotiation. (Page 2-48) Updated the SGMII to SGMII with forced link procedure from 0x21 to 0x21. (Page 2-49) Updated the Time Synchronization Submodule Architecture. (Page 2-25) Added Ethernet Switch Subsystem Complete Register Listing Table. (Page 3-2) Changed RFTCLK_SEL to CPTS_RTFCLK_SEL. (Page 2-33) Changed RTFCLK_SEL to CPTS_RTFCLK_SEL. (Page 2-2) Changed RTFCLK_SEL[4:0] to CPTS_RTFCLK_SEL[2:0]. (Page 2-2) SPRUGV9 November 2010 Initial Release ø-iv KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide SPRUGV9D June 2013

5 Contents Contents Release History ø-ii List of Tables ø-x List of Figures ø-xiv List of Procedures ø-xviii Preface ø-xix About This Manual ø-xix Notational Conventions ø-xix Related Documentation from Texas Instruments ø-xx Trademarks ø-xx Chapter 1 Chapter 2 Introduction Purpose of the Peripheral Features Gigabit Ethernet Switch Subsystem Functional Block Diagram Industry Standard(s) Compliance Statement Architecture Clock Control Gigabit Switch Subsystem Clock SGMII SerDes Reference Clock MDIO Clock IEEE 1588 Time Synchronization Clock GMII Clock Memory Map Gigabit Ethernet Switch Architecture Streaming Packet Interface Transmit Streaming Packet Interface Transmit VLAN Processing Receive Streaming Packet Interface Media Access Controller Submodule Architecture Data Receive Operations Data Transmission MAC Receive FIFO Architecture Statistics Submodule Architecture Accessing Statistics Registers Statistics Interrupts Receive Statistics Descriptions Transmit (Only) Statistics Descriptions Receive and Transmit (Shared) Statistics Descriptions Time Synchronization Submodule Architecture KeyStone II Time Synchronization Submodule Architecture Time Synchronization Submodule Components Time Synchronization Events Time Synchronization Initialization Detecting and Processing Time Synchronization Events Address Lookup Engine (ALE) Submodule Architecture ALE Table Reading Entries from the ALE Table SPRUGV9D June 2013 KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide ø-v

6 Contents Chapter Writing Entries to the ALE Table ALE Table Entry Types ALE Packet Forwarding Process ALE Learning Process Serial Gigabit Media Independent Interface (SGMII) Architecture SGMII Receive Interface SGMII Transmit Interface Modes of Operation Digital Loopback SGMII to PHY Configuration SGMII to SGMII with Autonegotiation Configuration SGMII to SGMII with Forced Link Configuration Management Data Input/Output (MDIO) Architecture Global PHY Detection and Link State Monitoring PHY Register User Access Writing Data to a PHY Register Reading Data from a PHY Register MDIO Interrupts MDIO Link Status Interrupts MDIO User Access Interrupts Initializing the MDIO Module KeyStone I Serializer/Deserializer (SerDes) Architecture KeyStone II Serializer/Deserializer (SerDes) Architecture Reset Considerations Initialization Interrupt Support Interrupt Events Power Management Registers Summary of Modules Gigabit Ethernet (GbE) Switch Subsystem Module Ethernet Switch Subsystem Identification and Version Register (ES_SS_IDVER) Serial Gigabit Media Independent Interface (SGMII) module SGMII Identification and Version Register (SGMII_IDVER) Software Reset Register (SOFT_RESET) SGMII Control Register (SGMII_CONTROL) Status Register (STATUS) Advertised Ability Register (MR_ADV_ABILITY) SGMII MODE Link Partner Advertised Ability Register (MR_LP_ADV_ABILITY) Management Data Input/Output (MDIO) module MDIO Version Register (MDIO_VERSION) MDIO Control Register (MDIO_CONTROL) PHY Alive Status Register (ALIVE) PHY Link Status Register (LINK) MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) MDIO User Access Register 0 (USERACCESS0) MDIO User PHY Select Register 0 (USERPHYSEL0) MDIO User Access Register 1 (USERACCESS1) ø-vi KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide SPRUGV9D June 2013

7 Contents MDIO User PHY Select Register 1 (USERPHYSEL1) Ethernet Switch Module Gigabit Ethernet (GbE) Switch Submodule GbE Switch Identification and Version Register (CPSW_IDVER) GbE Switch Control Register (CPSW_CONTROL) Emulation Control Register (EM_CONTROL) Statistics Port Enable (STAT_PORT_EN) Priority Type Register (PTYPE) KeyStone I and KeyStone II MAC Short Gap Threshold Register (GAP_THRESH) Transmit FIFO Start Words Register (TX_START_WDS) Flow Control Register (FLOW_CONTROL) Port 0 Source Identification Register (P0_CPPI_SRC_ID) Port 0 VLAN Register (P0_PORT_VLAN) Port 0 Receive Packet Priority to Header Priority Mapping Register (P0_RX_PRI_MAP) Port 0 Receive Maximum Length Register (P0_RX_MAXLEN) Port 1 Max Blocks Register (P1_MAX_BLKS) Port 1 Block Count Register (P1_BLK_CNT) Port 1 VLAN Register (P1_PORT_VLAN) Port 1 Transmit Header Priority to Switch Priority Mapping Register (P1_TX_PRI_MAP) MAC1 Source Address Low Register (MAC1_SA_LO) MAC1 Source Address High Register (MAC1_SA_HI) Port 1 Time Sync Control Register (P1_TS_CTL) Port 1 Time Sync Sequence ID and LTYPE Register (P1_TS_SEQ_LTYPE) Port 1 Time Sync Control Register 2 (P1 _TS_CTL2) Port 1 Time Sync Control Register and LTYPE2 (P1 _TS_CTL_LTYPE2) Port 1 Time Sync VLAN LTYPE Register (P1_TS_VLAN_LTYPE) Port 2 Max Blocks Register (P2_MAX_BLKS) Port 2 Block Count Register (P2_BLK_CNT) Port 2 VLAN Register (P2_PORT_VLAN) Port 2 Transmit Header Priority to Switch Priority Mapping Register (P2_TX_PRI_MAP) MAC2 Source Address Low Register (MAC2_SA_LO) MAC2 Source Address High Reserved Register (MAC2_SA_HI) Port 2 Time Sync Control Register (P2_TS_CTL) Port 2 Time Sync Sequence ID and LTYPE Register (P2_TS_SEQ_LTYPE) Port 2 Time Sync VLAN LTYPE Register (P2_TS_VLAN_LTYPE) Port 2 Time Sync Control Register 2 (P2 _TS_CTL2) Port 2 Time Sync Control Register and LTYPE2 (P2 _TS_CTL_LTYPE2) KeyStone II Port 3 & 4 Register Descriptions Port 3 Max Blocks Register (P3_MAX_BLKS) Port 3 Block Count Register (P3_BLK_CNT) Port 3 VLAN Register (P3_PORT_VLAN) Port 3 Transmit Header Priority to Switch Priority Mapping Register (P3_TX_PRI_MAP) MAC3 Source Address Low Register (MAC3_SA_LO) MAC3 Source Address High Register (MAC3_SA_HI) Port 3 Time Sync Control Register (P3 _TS_CTL) Port 3 Time Sync Sequence ID and LTYPE Register (P3_TS_SEQ_LTYPE) Port 3 Time Sync VLAN LTYPE Register (P3_TS_VLAN_LTYPE) Port 3 Time Sync Control and LTYPE2 Register (P3 _TS_CTL_LTYPE2) Port 3 Time Sync Control Register 2 (P3 _TS_CTL2) Port 4 Max Blocks Register (P4_MAX_BLKS) Port 4 Block Count Register (P4_BLK_CNT) Port 4 VLAN Register (P4_PORT_VLAN) Port 4 Transmit Header Priority to Switch Priority Mapping Register (P4_TX_PRI_MAP) MAC4 Source Address Low Register (MAC4_SA_LO) MAC4 Source Address High Register (MAC4_SA_HI) Port 4 Time Sync Control Register (P4 _TS_CTL) Port 4 Time Sync Sequence ID and LTYPE Register (P4_TS_SEQ_LTYPE) Port 4 Time Sync VLAN LTYPE Register (P4_TS_VLAN_LTYPE) Port 4 Time Sync Control Register and LTYPE2 (P4 _TS_CTL_LTYPE2) SPRUGV9D June 2013 KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide ø-vii

8 Contents Port 4 Time Sync Control Register 2 (P4 _TS_CTL2) Ethernet Media Access Controller (EMAC) Submodule MAC Identification and Version Register (MAC_IDVER) MAC Control Register (MAC_CONTROL) MAC Status Register (MACSTATUS) Software Reset Register (SOFT_RESET) Receive Maximum Length Register (RX_MAXLEN) Receive Pause Timer Register (RX_PAUSE) Transmit Pause Timer Register (TX_PAUSE) Emulation Control Register (EM_CONTROL) Receive Packet Priority to Header Priority Mapping Register (MAC_RX_PRI_MAP) Statistics (STATS) Submodule Good Receive Frames Register (RXGOODFRAMES) Broadcast Receive Frames Register (RXBROADCASTFRAMES) Multicast Receive Frames Register (RXMULTICASTFRAMES) Pause Receive Frames Register (RXPAUSEFRAMES) Receive CRC Errors Register (RXCRCERRORS) Receive Align/Code Errors Register (RXALIGNCODEERRORS) Oversize Receive Frames Register (RXOVERSIZEDFRAMES) Receive Jabber Frames Register (RXJABBERFRAMES) Undersize (Short) Receive Frames Register (RXUNDERSIZEDFRAMES) Receive Fragment Register (RXFRAGMENTS) Receive Octets Register (RXOCTETS) Good Transmit Frames Register (TXGOODFRAMES) Broadcast Transmit Frames Register (TXBROADCASTFRAMES) Multicast Transmit Frames (TXMULTICASTFRAMES) Pause Transmit Frames Register (TXPAUSEFRAMES) Deferred Transmit Frames Register (TXDEFERREDFRAMES) Transmit Frames Collision Register (TXCOLLISIONFRAMES) Transmit Frames Single Collision Register (TXSINGLECOLLFRAMES) Transmit Frames Multiple Collision Register (TXMULTCOLLFRAMES) Transmit Excessive Collision Register (TXEXCESSIVECOLLISIONS) Transmit Late Collisions Register (TXLATECOLLISIONS) Transmit Frames Underrun Register (TXUNDERRUN) Transmit Carrier Sense Errors Register (TXCARRIERSENSEERRORS) Transmit Octets Register (TXOCTETS) Receive and Transmit 64 Octet Frames Register (64OCTETFRAMES) Receive and Transmit Octet Frames Register (65T127OCTETFRAMES) Receive and Transmit Octet Frames Register (128T255OCTETFRAMES) Receive and Transmit Octet Frames Register (256T511OCTETFRAMES) Receive and Transmit Octet Frames Register (512T1023OCTETFRAMES) Receive and Transmit 1024 and Up Octet Frames Register (1024TUPOCTETFRAMES) Net Octets Register (NETOCTETS) Receive Start of Frame Overruns Register (RXSOFOVERRUNS) Receive Middle of Frame Overruns Register (RXMOFOVERRUNS) Receive DMA Overruns Register (RXDMAOVERRUNS) Time Synchronization (CPTS) submodule CPTS Identification and Version Register (CPTS_IDVER) Time Sync Control Register (TS_CTL) RFTCLK Select Register (CPTS_RFTCLK_SEL) Time Stamp Event Push Register (TS_PUSH) Interrupt Status Raw Register (INTSTAT_RAW) Interrupt Status Masked Register (INTSTAT_MASKED) Interrupt Enable Register (INT_ENABLE) Event Pop Register (EVENT_POP) Event Low Register (EVENT_LOW) Event Middle Register (EVENT_MID) Event High Register (EVENT_HIGH) Address Lookup Engine (ALE) submodule ø-viii KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide SPRUGV9D June 2013

9 Contents ALE Identification and Version Register (ALE_IDVER) ALE Control Register (ALE_CONTROL) ALE Prescale Register (ALE_PRESCALE) ALE Unknown VLAN Register (UNKNOWN_VLAN) ALE Table Control Register (ALE_TBLCTL) ALE Table Word 2 Register (ALE_TBLW2) ALE Table Word 1 Register (ALE_TBLW1) ALE Table Word 0 Register (ALE_TBLW0) ALE Port 0 Control Register (ALE_PORTCTL0) ALE Port 1 Control Register (ALE_PORTCTL1) ALE Port 2 Control Register (ALE_PORTCTL2) ALE Port 3 Control Register (ALE_PORTCTL3) ALE Port 4 Control Register (ALE_PORTCTL4) ALE Port 5 Control Register (ALE_PORTCTL5) Serializer/Deserializer (SerDes) SGMII Boot Configuration Registers SGMII SerDes Status Register (SGMII_SERDES_STS) SGMII PLL Configuration Register (SGMII_SERDES_CFGPLL) SGMII Receive Configuration Register n (SGMII_SERDES_CFGRXn) SGMII Transmit Configuration Register n (SGMII_SERDES_CFGTXn) SPRUGV9D June 2013 KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide ø-ix

10 List of Tables List of Tables Table 2-1 KeyStone I Gigabit Ethernet Switch Subsystem Modules Table 2-2 KeyStone II Gigabit Ethernet Switch Subsystem Modules Table 2-3 KeyStone I PS_FLAGS for GbE Switch Ingress Packets Table 2-4 KeyStone II PS_FLAGS for GbE Switch Ingress Packets Table 2-5 KeyStone I Time Synchronization Event Fields Table 2-6 KeyStone II Time Synchronization Event Fields Table 2-7 ALE Table Learned Address Control Bits Table 2-8 Free Table Entry Field Configuration Table 2-9 Multicast Address Table Entry Field Configuration Table 2-10 VLAN/Multicast Address Table Entry Field Configuration Table 2-11 Unicast Address Table Entry Field Configuration Table 2-12 OUI Unicast Address Table Entry Field Configuration Table 2-13 VLAN/Unicast Table Entry Field Configuration Table 2-14 VLAN Table Entry Field Configuration Table 2-15 ALE Table Entry Field Descriptions Table 2-16 Gigabit Ethernet Switch Subsystem Descriptor Error Flags Table 2-17 ALE Ingress Filtering Process Table 2-18 VLAN Aware Lookup Process Table 2-19 VLAN Unaware Lookup Process Table 2-20 ALE Egress Process Table 2-21 ALE Learning Process Table 3-1 KeyStone I Gigabit Ethernet Switch Subsystem Modules Table 3-2 KeyStone II Gigabit Ethernet Switch Subsystem Module Table 3-3 KeyStone I Gigabit Ethernet Switch Subsystem Complete Register Listing Table 3-4 KeyStone II Gigabit Ethernet Switch Subsystem Complete Register Listing Table 3-5 Ethernet Switch Subsystem Module Table 3-6 Ethernet Switch Subsystem Identification and Version Register (ES_SS_IDVER) Field Descriptions Table 3-7 SGMII Registers Table 3-8 SGMII Identification and Version Register (SGMII_IDVER) Field Descriptions Table 3-9 Software Reset Register (SOFT_RESET) Field Descriptions Table 3-10 SGMII Control Register (SGMII_CONTROL) Field Descriptions Table 3-11 Status Register (STATUS) Field Descriptions Table 3-12 Advertised Ability Register (MR_ADV_ABILITY) Field Descriptions Table 3-13 Advertised Ability and Link Partner Advertised Ability for SGMII Mode Table 3-14 Link Partner Advertised Ability Register (MR_LP_ADV_ABILITY) Field Descriptions Table 3-15 MDIO Registers Table 3-16 MDIO Version Register (MDIO _VERSION) Field Descriptions Table 3-17 MDIO Control Register (MDIO_CONTROL) Field Descriptions Table 3-18 PHY Alive Status Register Field Descriptions Table 3-19 PHY Link Status Register (LINK) Field Descriptions Table 3-20 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions Table 3-21 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions Table 3-22 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions Table 3-23 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions Table 3-24 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions Table 3-25 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field Descriptions Table 3-26 MDIO User Access Register 0 (USERACCESS0) Field Descriptions Table 3-27 MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions Table 3-28 MDIO User Access Register 1 (USERACCESS1) Field Descriptions Table 3-29 MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions Table 3-30 KeyStone I Ethernet Switch Submodules Table 3-31 KeyStone II Ethernet Switch Submodules ø-x KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide SPRUGV9D June 2013

11 List of Tables Table 3-32 KeyStone I Ethernet Switch Registers Table 3-33 KeyStone II Ethernet Switch Registers Table 3-34 GbE Switch Identification and Version Register (CPSW_IDVER) Field Descriptions Table 3-35 GbE Switch Control Register (CPSW_CONTROL) Field Descriptions for KeyStone I and KeyStone II Table 3-36 Emulation Control Register (EM_CONTROL) Field Descriptions Table 3-37 KeyStone I Statistics Port Enable (STAT_PORT_EN) Field Descriptions Table 3-38 KeyStone II Statistics Port Enable (STAT_PORT_EN) Field Descriptions Table 3-39 KeyStone I Priority Type Register (PTYPE) Field Descriptions Table 3-40 KeyStone II Priority Type Register (PTYPE) Field Descriptions Table 3-41 KeyStone I and KeyStone II MAC Short Gap Threshold Register (GAP_THRESH) Field Descriptions Table 3-42 Transmit FIFO Start Words Register (TX_START_WDS) Field Descriptions Table 3-43 KeyStone I Flow Control Register (FLOW_CONTROL) Field Descriptions Table 3-44 KeyStone II Flow Control Register (FLOW_CONTROL) Field Descriptions Table 3-45 KeyStone I Port 0 Source Identification Register (P0_CPPI_SRC_ID) Field Descriptions Table 3-46 KeyStone II Port 0 Source Identification Register (P0_CPPI_SRC_ID) Field Descriptions Table 3-47 Port 0 VLAN Register (P0_PORT_VLAN) Field Descriptions Table 3-48 Port 0 Receive Packet Priority to Header Priority Mapping Register (P0_RX_PRI_MAP) Field Descriptions Table 3-49 Port 0 RX Maximum Length Register (P0_RX_MAXLEN) Field Descriptions Table 3-50 Port 1 Max Blocks Register (P1_MAX_BLKS) Field Descriptions Table 3-51 Port 1 Block Count Register (P1_BLK_CNT) Field Descriptions Table 3-52 Port 1 VLAN Register (P1_PORT_VLAN) Field Descriptions Table 3-53 Port 1 Transmit Header Priority to Switch Priority Mapping Register (P1_TX_PRI_MAP) Field Descriptions Table 3-54 MAC1 Source Address Low Register (MAC1_SA_LO) Field Descriptions Table 3-55 MAC1 Source Address High Register (MAC1_SA_HI) Field Descriptions Table 3-56 KeyStone I Port 1 Time Sync Control Register (P1_TS_CTL) Field Descriptions Table 3-57 KeyStone II Port 1 Time Sync Control Register (P1_TS_CTL) Field Descriptions Table 3-58 Port 1 Time Sync Sequence ID and LTYPE Register (P1_TS_SEQ_LTYPE) Field Descriptions Table 3-59 Port 1 Time Sync Control 2 Register (P1_TS_CTL2) Field Descriptions Table 3-60 Port 1Time Sync Control Register and LTYPE2 (P1_TS_CTL_LTYPE2) Field Descriptions (KeyStone II Only) Table 3-61 Port 1 Time Sync VLAN LTYPE Register (P1_TS_VLAN_LTYPE) Field Descriptions Table 3-62 Port 2 Max Blocks Register (P2_MAX_BLKS) Field Descriptions Table 3-63 Port 2 Block Count Register (P2_BLK_CNT) Field Descriptions Table 3-64 Port 2 VLAN Register (P2_PORT_VLAN) Field Descriptions Table 3-65 Port 2 Transmit Header Priority to Switch Priority Mapping Register (P2_TX_PRI_MAP) Field Descriptions Table 3-66 MAC2 Source Address Low Register (MAC2_SA_LO) Field Descriptions Table 3-67 MAC2 Source Address High Reserved Register (MAC2_SA_HI) Field Descriptions Table 3-68 KeyStone I Port 2 Time Sync Control Register (P2_TS_CTL) Field Descriptions Table 3-69 KeyStone II Port 2 Time Sync Control Register (P2_TS_CTL) Field Descriptions Table 3-70 Port 2 Time Sync Sequence ID and LTYPE Register (P2_TS_SEQ_LTYPE) Field Descriptions Table 3-71 Port 2 Time Sync VLAN LTYPE Register (P2_TS_VLAN_LTYPE) Field Descriptions Table 3-72 Port 2 Time Sync Control Register 2 (P2_TS_CTL2) Field Descriptions Table 3-73 Port 2 Time Sync Control Register and LTYPE2 (P2_TS_CTL_LTYPE2) Field Descriptions (KeyStone II Only) Table 3-74 Port 3 Max Blocks Register (P3_MAX_BLKS) Field Descriptions Table 3-75 Port 3 Block Count Register (P3_BLK_CNT) Field Descriptions Table 3-76 Port 3 VLAN Register (P3_PORT_VLAN) Field Descriptions Table 3-77 Port 3 Transmit Header Priority to Switch Priority Mapping Register (P3_TX_PRI_MAP) Field Descriptions Table 3-78 MAC3 Source Address Low Register (MAC3_SA_LO) Field Descriptions Table 3-79 MAC3 Source Address High Register (MAC3_SA_HI) Field Descriptions Table 3-80 Port 3 Time Sync Control Register (P3_TS_CTL) Field Descriptions Table 3-81 Port 3 Time Sync Sequence ID and LTYPE Register (P3_TS_SEQ_LTYPE) Field Descriptions Table 3-82 Port 3 Time Sync VLAN LTYPE Register (P3_TS_VLAN_LTYPE) Field Descriptions Table 3-83 Port 3 Time Sync Control and LTYPE2 Register (P3_TS_CTL_LTYPE2) Field Descriptions Table 3-84 Port 3 Time Sync Control 2 Register (P3_TS_CTL2) Field Descriptions Table 3-85 Port 4 Max Blocks Register (P4_MAX_BLKS) Field Descriptions SPRUGV9D June 2013 KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide ø-xi

12 List of Tables Table 3-86 Port 4 Block Count Register (P4_BLK_CNT) Field Descriptions Table 3-87 Port 4 VLAN Register (P4_PORT_VLAN) Field Descriptions Table 3-88 Port 4 Transmit Header Priority to Switch Priority Mapping Register (P4_TX_PRI_MAP) Field Descriptions Table 3-89 MAC4 Source Address Low Register (MAC4_SA_LO) Field Descriptions Table 3-90 MAC4 Source Address High Register (MAC4_SA_HI) Field Descriptions Table 3-91 Port 4 Time Sync Control Register (P4_TS_CTL) Field Descriptions Table 3-92 Port 4 Time Sync Sequence ID and LTYPE Register (P4_TS_SEQ_LTYPE) Field Descriptions Table 3-93 Port 4 Time Sync VLAN LTYPE Register (P4_TS_VLAN_LTYPE) Field Descriptions Table 3-94 Port 4 Time Sync Control Register and LTYPE2 (P4_TS_CTL_LTYPE2) Field Descriptions Table 3-95 Port 4 Time Sync Control 2 Register (P4_TS_CTL2) Field Descriptions Table 3-96 EMAC Registers Table 3-97 MAC Identification and Version Register (MAC_IDVER) Field Descriptions Table 3-98 MAC Control Register (MAC_CONTROL) Field Descriptions Table 3-99 MAC Status Register (MACSTATUS) Field Descriptions Table Software Reset Register (SOFT_RESET) Field Descriptions Table Receive Maximum Length Register (RX_MAXLEN) Field Descriptions Table Receive Pause Timer Register (RX_PAUSE) Field Descriptions Table Transmit Pause Timer Register (TX_PAUSE) Field Descriptions Table Emulation Control Register (EM_CONTROL) Field Descriptions Table Receive Packet Priority to Header Priority Mapping Register (MAC_RX_PRI_MAP) Field Descriptions Table STATS Registers Table Good Receive Frames Register (RXGOODFRAMES) Field Descriptions Table Broadcast Receive Frames Register (RXBROADCASTFRAMES) Field Descriptions Table Multicast Receive Frames Register (RXMULTICASTFRAMES) Field Descriptions Table Pause Receive Frames Register (RXPAUSEFRAMES) Field Descriptions Table Receive CRC Errors Register (RXCRCERRORS) Field Descriptions Table Receive Align/Code Errors Register (RXALIGNCODEERRORS) Field Descriptions Table Oversized Receive Frames Register (RXOVERSIZEDFRAMES) Field Descriptions Table Receive Jabber Frames Register (RXJABBERFRAMES) Field Descriptions Table Undersized (Short) Receive Frames Register (RXUNDERSIZEDFRAMES) Field Descriptions Table Receive Fragment Frames Register (RXFRAGMENTS) Field Descriptions Table Receive Octets Register (RXOCTETS) Field Descriptions Table Good Transmit Frames Register (TXGOODFRAMES) Field Descriptions Table Broadcast Transmit Frames Register (TXBROADCASTFRAMES) Field Descriptions Table Multicast Transmit Frames Register (TXMULTICASTFRAMES) Field Descriptions Table Pause Transmit Frames Register (TXPAUSEFRAMES) Field Descriptions Table Deferred Transmit Frames Register (TXDEFERREDFRAMES) Field Descriptions Table Transmit Frames Collision Register (TXCOLLISIONFRAMES) Field Descriptions Table Transmit Frames Single Collision Register (TXSINGLECOLLFRAMES) Field Descriptions Table Transmit Frames Multiple Collision Register (TXMULTCOLLFRAMES) Field Descriptions Table Transmit Excessive Collisions Register (TXECESSIVECOLLISIONS) Field Descriptions Table Transmit Late Collisions Register (TXLATECOLLISIONS) Field Descriptions Table Transmit Frames Underrun Register (TXUNDERRUNS) Field Descriptions Table Transmit Carrier Sense Errors Register (TXCARRIERSENSEERRORS) Field Descriptions Table Transmit Octets Register (TXOCTETS) Field Descriptions Table Receive and Transmit 64 Octet Frames Register (64OCTETFRAMES) Field Descriptions Table Receive and Transmit Octet Frames Register (65T127OCTETFRAMES) Field Descriptions Table Receive and Transmit Octet Frames Register (128T255OCTETFRAMES) Field Descriptions Table Receive and Transmit Octet Frames Register (256T511OCTETFRAMES) Field Descriptions Table Receive and Transmit Octet Frames Register (512T1023OCTETFRAMES) Field Descriptions Table Receive and Transmit 1024 and Up Octet Frames Register (1024TUPOCTETFRAMES) Field Descriptions Table Net Octets Register (NETOCTETS) Field Descriptions Table Receive Start of Frame Overrun Register (RXSOFOVERRUNS) Field Descriptions Table Receive Middle of Frame Overrun Register (RXMOFOVERRUNS) Field Descriptions ø-xii KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide SPRUGV9D June 2013

13 List of Tables Table Receive DMA Overruns Register (RXDMAOVERRUNS) Field Descriptions Table KeyStone I CPTS Registers Table KeyStone II CPTS Registers Table CPTS Identification and Version Register (CPTS_IDVER) Field Descriptions Table Time Sync Control Register (TS_CTL) Field Descriptions Table RFTCLK Select Register (CPTS_RFTCLK_SEL) Field Descriptions Table Time Stamp Event Push Register (TS_PUSH) Field Descriptions Table Interrupt Status Raw Register (INTSTAT_RAW) Field Descriptions Table Interrupt Status Masked Register (INTSTAT_MASKED) Field Descriptions Table Interrupt Enable Register (INT_ENABLE) Field Descriptions Table Event Pop Register (EVENT_POP) Field Descriptions Table Event Low Register (EVENT_LOW) Field Descriptions Table Event Middle Register (EVENT_MID) Field Descriptions Table Event High Register (EVENT_HIGH) Field Descriptions Table ALE Registers Table ALE Identification and Version Register (ALE_IDVER) Field Descriptions Table ALE Control Register (ALE_CONTROL) Field Descriptions Table ALE Prescale Register (ALE_PRESCALE) Field Descriptions Table ALE Unknown VLAN Register (UNKNOWN_VLAN) Field Descriptions Table ALE Table Control Register (ALE_TBLCTL) Field Descriptions Table ALE Table Word 2 Register (ALE_TBLW2) Field Descriptions Table ALE Table Word 1 Register (ALE_TBLW2) Field Descriptions Table ALE Table Word 0 Register (ALE_TBLW0) Field Descriptions Table ALE Port 0 Control Register (ALE_PORTCTL0) Field Descriptions Table ALE Port 1 Control Register (ALE_PORTCTL1) Field Descriptions Table ALE Port 2 Control Register (ALE_PORTCTL2) Field Descriptions Table ALE Port 3 Control Register (ALE_PORTCTL3) Field Descriptions Table ALE Port Control Register 4 (ALE_PORTCTL4) Field Descriptions Table ALE Port 5 Control Register (ALE_PORTCTL5) Field Descriptions Table SerDes SGMII Boot Configuration Registers Table SGMII SerDes Status Register (SGMII_SERDES_STS) Field Descriptions Table SGMII PLL Configuration Register (SGMII_SERDES_CGFPLL) Field Descriptions Table Ratescale Values Table SGMII SerDes PLL Multiply Modes Table SGMII RX Configuration Register n (SGMII_SERDES_CGFRXn) Field Descriptions Table Receiver Equalizer Configuration (EQ) Table SGMII TX Configuration Register n (SGMII_SERDES_CGFTXn) Field Descriptions Table Differential Output De-emphasis Table Differential Output Swing SPRUGV9D June 2013 KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide ø-xiii

14 List of Figures List of Figures Figure 1-1 KeyStone I Ethernet Switch Subsystem Block Diagram Figure 1-2 KeyStone II Ethernet Switch Subsystem Block Diagram Figure 2-1 Free Table Entry Figure 2-2 Multicast Address Table Entry Figure 2-3 VLAN/Multicast Table Entry Figure 2-4 Unicast Table Entry Figure 2-5 OUI Unicast Table Entry Figure 2-6 VLAN/Unicast Table Entry Figure 2-7 VLAN Table Entry Figure 2-8 SGMII Mode with PHY Configuration Figure 2-9 SGMII Master to SGMII Slave with Autonegotiation Configuration Figure 2-10 SGMII Master to SGMII Master with Forced Link Configuration Figure 3-1 Ethernet Switch Subsystem Identification and Version Register (ES_SS_IDVER) Figure 3-2 SGMII Identification and Version Register (SGMII_IDVER) Figure 3-3 Software Reset Register (SOFT_RESET) Figure 3-4 SGMII Control Register (SGMII_CONTROL) Figure 3-5 Status Register (STATUS) Figure 3-6 Advertised Ability Register (MR_ADV_ABILITY) Figure 3-7 Link Partner Advertised Ability Register (MR_LP_ADV_ABILITY) Figure 3-8 MDIO Version Register (MDIO_VERSION) Figure 3-9 MDIO Control Register (MDIO_CONTROL) Figure 3-10 PHY Alive Status Register (ALIVE) Figure 3-11 PHY Link Status Register (LINK) Figure 3-12 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Figure 3-13 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Figure 3-14 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Figure 3-15 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Figure 3-16 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Figure 3-17 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Figure 3-18 MDIO User Access Register 0 (USERACCESS0) Figure 3-19 MDIO User PHY Select Register 0 (USERPHYSEL0) Figure 3-20 MDIO User Access Register 1 (USERACCESS1) Figure 3-21 MDIO User PHY Select Register 1 (USERPHYSEL1) Figure 3-22 GbE Switch Identification and Version Register (CPSW_IDVER) Figure 3-23 GbE Switch Control Register (CPSW_CONTROL) Figure 3-24 Emulation Control Register (EM_CONTROL) Figure 3-25 KeyStone I Statistics Port Enable (STAT_PORT_EN) Figure 3-26 KeyStone II Statistics Port Enable (STAT_PORT_EN) Figure 3-27 KeyStone I Priority Type Register (PTYPE) Figure 3-28 KeyStone II Priority Type Register (PTYPE) Figure 3-29 KeyStone I and KeyStone II MAC Short Gap Threshold Register (GAP_THRESH) Figure 3-30 Transmit FIFO Start Words Register (TX_START_WDS) Figure 3-31 KeyStone I Flow Control Register (FLOW_CONTROL) Figure 3-32 KeyStone II Flow Control Register (FLOW_CONTROL) Figure 3-33 KeyStone I Port 0 Source Identification Register (P0_CPPI_SRC_ID) Figure 3-34 KeyStone II Port 0 Source Identification Register (P0_CPPI_SRC_ID) Figure 3-35 Port 0 VLAN Register (P0_PORT_VLAN) Figure 3-36 Port 0 Receive Packet Priority to Header Priority Mapping Register (P0_RX_PRI_MAP) Figure 3-37 Port 0 RX Maximum Length Register (P0_RX_MAXLEN) Figure 3-38 Port 1 Max Blocks Register (P1_MAX_BLKS) Figure 3-39 Port 1 Block Count Register (P1_BLK_CNT) Figure 3-40 Port 1 VLAN Register (P1_PORT_VLAN) ø-xiv KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide SPRUGV9D June 2013

15 List of Figures Figure 3-41 Port 1 Transmit Header Priority to Switch Priority Mapping Register (P1_TX_PRI_MAP) Figure 3-42 MAC1 Source Address Low Register (MAC1_SA_LO) Figure 3-43 MAC1 Source Address High Register (MAC1_SA_HI) Figure 3-44 KeyStone I Port 1 Time Sync Control Register (P1_TS_CTL) Figure 3-45 KeyStone II Port 1 Time Sync Control Register (P1_TS_CTL) Figure 3-46 Port 1 Time Sync Sequence ID and LTYPE Register (P1_TS_SEQ_LTYPE) Figure 3-47 Port 1 Time Sync Control Register 2 (P1_TS_CTL2) Figure 3-48 Port 1 Time Sync Control Register and LTYPE2 (P1_TS_CTL_LTYPE2) Figure 3-49 Port 1 Time Sync VLAN LTYPE Register (P1_TS_VLAN_LTYPE) Figure 3-50 Port 2 Max Blocks Register (P2_MAX_BLKS) Figure 3-51 Port 2 Block Count Register (P2_BLK_CNT) Figure 3-52 Port 2 VLAN Register (P2_PORT_VLAN) Figure 3-53 Port 2 Transmit Header Priority to Switch Priority Mapping Register (P2_TX_PRI_MAP) Figure 3-54 MAC2 Source Address Low Register (MAC2_SA_LO) Figure 3-55 MAC2 Source Address High Reserved Register (MAC2_SA_HI) Figure 3-56 KeyStone I Port 2 Time Sync Control Register (P2_TS_CTL) Figure 3-57 KeyStone II Port 2 Time Sync Control Register (P1_TS_CTL) Figure 3-58 Port 2 Time Sync Sequence ID and LTYPE Register (P2_TS_SEQ_LTYPE) Figure 3-59 Port 2 Time Sync VLAN LTYPE Register (P2_TS_VLAN_LTYPE) Figure 3-60 Port 2Time Sync Control Register 2 (P3_TS_CTL2) Figure 3-61 Port 2 Time Sync Control Register and LTYPE2 (P2_TS_CTL_LTYPE2) Figure 3-62 Port 3 Max Blocks Register (P3_MAX_BLKS) Figure 3-63 Port 3 Block Count Register (P3_BLK_CNT) Figure 3-64 Port 3 VLAN Register (P3_PORT_VLAN) Figure 3-65 Port 3 Transmit Header Priority to Switch Priority Mapping Register (P3_TX_PRI_MAP) Figure 3-66 MAC3 Source Address Low Register (MAC3_SA_LO) Figure 3-67 MAC3 Source Address High Register (MAC3_SA_HI) Figure 3-68 Port 3 Time Sync Control Register (P3_TS_CTL) Figure 3-69 Port 3 Time Sync Sequence ID and LTYPE Register (P3_TS_SEQ_LTYPE) Figure 3-70 Port 3 Time Sync VLAN LTYPE Register (P3_TS_VLAN_LTYPE) Figure 3-71 Port 3 Time Sync Control and LTYPE2 Register (P3_TS_CTL_LTYPE2) Figure 3-72 Port 3 Time Sync Control Register 2 (P3_TS_CTL2) Figure 3-73 Port 4 Max Blocks Register (P4_MAX_BLKS) Figure 3-74 Port 4 Block Count Register (P4_BLK_CNT) Figure 3-75 Port 4 VLAN Register (P4_PORT_VLAN) Figure 3-76 Port 4 Transmit Header Priority to Switch Priority Mapping Register (P4_TX_PRI_MAP) Figure 3-77 MAC4 Source Address Low Register (MAC4_SA_LO) Figure 3-78 MAC4 Source Address High Register (MAC4_SA_HI) Figure 3-79 Port 4 Time Sync Control Register (P4_TS_CTL) Figure 3-80 Port 4 Time Sync Sequence ID and LTYPE Register (P4_TS_SEQ_LTYPE) Figure 3-81 Port 4 Time Sync VLAN LTYPE Register (P4_TS_VLAN_LTYPE) Figure 3-82 Port 4 Time Sync Control Register and LTYPE2 (P4_TS_CTL_LTYPE2) Figure 3-83 Port 4 Time Sync Control Register 2 (P4_TS_CTL2) Figure 3-84 MAC Identification and Version Register (MAC_IDVER) Figure 3-85 MAC Control Register (MAC_CONTROL) Figure 3-86 MAC Status Register (MACSTATUS) Figure 3-87 Software Reset Register (SOFT_RESET) Figure 3-88 Receive Maximum Length Register (RX_MAXLEN) Figure 3-89 Receive Pause Timer Register (RX_PAUSE) Figure 3-90 Transmit Pause Timer Register (TX_PAUSE) Figure 3-91 Emulation Control Register (EM_CONTROL) Figure 3-92 Receive Packet Priority to Header Priority Mapping Register (MAC_RX_PRI_MAP) Figure 3-93 Good Receive Frames Register (RXGOODFRAMES) Figure 3-94 Broadcast Receive Frames Register (RXBROADCASTFRAMES) SPRUGV9D June 2013 KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide ø-xv

16 List of Figures Figure 3-95 Multicast Receive Frames Register (RXMULTICASTFRAMES) Figure 3-96 Pause Receive Frames Register (RXPAUSEFRAMES) Figure 3-97 Receive CRC Errors Register (RXCRCERRORS) Figure 3-98 Receive Align/Code Errors Register (RXALIGNCODEERRORS) Figure 3-99 Oversize Receive Frames Register (RXOVERSIZEDFRAMES) Figure Receive Jabber Frames Register (RXJABBERFRAMES) Figure Undersize (Short) Receive Frames Register (RXUNDERSIZEDFRAMES) Figure Receive Fragment Register (RXFRAGMENTS) Figure Receive Octets Register (RXOCTETS) Figure Good Transmit Frames Register (TXGOODFRAMES) Figure Broadcast Transmit Frames Register (TXBROADCASTFRAMES) Figure Multicast Transmit Frames (TXMULTICASTFRAMES) Figure Pause Transmit Frames Register (TXPAUSEFRAMES) Figure Deferred Transmit Frames Register (TXDEFERREDFRAMES) Figure Transmit Frames Collision Register (TXCOLLISIONFRAMES) Figure Transmit Frames Single Collision Register (TXSINGLECOLLFRAMES) Figure Transmit Frames Multiple Collision Register (TXMULTCOLLFRAMES) Figure Transmit Excessive Collision Register (TXEXCESSIVECOLLISIONS) Figure Transmit Late Collisions Register (TXLATECOLLISIONS) Figure Transmit Frames Underrun Register (TXUNDERRUN) Figure Transmit Carrier Sense Errors Register (TXCARRIERSENSEERRORS) Figure Transmit Octets Register (TXOCTETS) Figure Receive and Transmit 64 Octet Frames Register (64OCTETFRAMES) Figure Receive and Transmit Octet Frames Register (65T127OCTETFRAMES) Figure Receive and Transmit Octet Frames Register (128T255OCTETFRAMES) Figure Receive and Transmit Octet Frames Register (256T511OCTETFRAMES) Figure Receive and Transmit Octet Frames Register (512T1023OCTETFRAMES) Figure Receive and Transmit 1024 and Up Octet Frames Register (1024TUPOCTETFRAMES) Figure Net Octets Register (NETOCTETS) Figure Receive Start of Frame Overruns Register (RXSOFOVERRUNS) Figure Receive Middle of Frame Overruns Register (RXMOFOVERRUNS) Figure Receive DMA Overruns Register (RXDMAOVERRUNS) Figure CPTS Identification and Version Register (CPTS_IDVER) Figure Time Sync Control Register (TS_CTL) Figure RFTCLK Select Register (CPTS_RFTCLK_SEL) Figure Time Stamp Event Push Register (TS_PUSH) Figure Interrupt Status Raw Register (INTSTAT_RAW) Figure Interrupt Status Masked Register (INTSTAT_MASKED) Figure Interrupt Enable Register (INT_ENABLE) Figure Event Pop Register (EVENT_POP) Figure Event Low Register (EVENT_LOW) Figure Event MIddle Register (EVENT_MID) Figure Event High Register (EVENT_HIGH) Figure ALE Identification and Version Register (ALE_IDVER) Figure ALE Control Register (ALE_CONTROL) Figure ALE Prescale Register (ALE_PRESCALE) Figure ALE Unknown VLAN Register (UNKNOWN_VLAN) Figure ALE Table Control Register (ALE_TBLCTL) Figure ALE Table Word 2 Register (ALE_TBLW2) Figure ALE Table Word 1 Register (ALE_TBLW1) Figure ALE Table Word 0 Register (ALE_TBLW0) Figure ALE Port 0 Control Register (ALE_PORTCTL0) Figure ALE Port 1 Control Register (ALE_PORTCTL1) Figure ALE Port 2 Control Register (ALE_PORTCTL2) ø-xvi KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide SPRUGV9D June 2013

17 List of Figures Figure ALE Port 3 Control Register (ALE_PORTCTL3) Figure ALE Port 4 Control Register (ALE_PORTCTL4) Figure ALE Port 5 Control Register (ALE_PORTCTL5) Figure SGMII SerDes Status Register (SGMII_SERDES_STS) Figure SGMII PLL Configuration Register (SGMII_SERDES_CGFPLL) Figure SGMII Receive Configuration Register n (SGMII_SERDES_CFGRXn) Figure SGMII Transmit Configuration Register n (SGMII_SERDES_CFGTXn) SPRUGV9D June 2013 KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide ø-xvii

18 List of Procedures List of Procedures Procedure 2-1 Time Synchronization Module Configuration Procedure 2-2 Popping Time Synchronization Events from the Event FIFO Procedure 2-3 Digital Loopback Configuration Procedure 2-4 SGMII to PHY Configuration Procedure 2-5 Setting up the SGMII in Master Mode with Autonegotiation Procedure 2-6 Setting up the SGMII in Slave Mode with Autonegotiation Procedure 2-7 SGMII to SGMII with Forced Link Procedure 2-8 GbE Switch Subsystem Initialization Procedure ø-xviii KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide SPRUGV9D June 2013

19 Preface About This Manual This document gives a functional description of the Ethernet Switch Subsystem and related portions of the Serializer/Deserializer (SerDes) module. The Ethernet Switch Subsystem consists of the Ethernet Media Access Controller (EMAC) module, Serial Gigabit Media Independent Interface (SGMII) modules, Physical Layer (PHY) device Management Data Input/Output (MDIO) module, Ethernet Switch module, and other associated submodules that are integrated on the device. Notational Conventions This document uses the following conventions: Commands and keywords are in boldface font. Arguments for which you supply values are in italic font. Terminal sessions and information the system displays are in screen font. Information you must enter is in boldface screen font. Elements in square brackets ([ ]) are optional. Notes use the following conventions: Note Means reader take note. Notes contain helpful suggestions or references to material not covered in the publication. The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. CAUTION Indicates the possibility of service interruption if precautions are not taken. WARNING Indicates the possibility of damage to equipment if precautions are not taken. SPRUGV9D June 2013 KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide ø-xix

20 Preface Related Documentation from Texas Instruments Multicore Navigator for KeyStone Devices User Guide Network Coprocessor (NETCP) for KeyStone Devices User Guide Packet Accelerator (PA) for KeyStone Devices User Guide Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide Security Accelerator (SA) for KeyStone Devices User Guide SPRUGR9 SPRUGZ6 SPRUGS4 SPRUGV2 SPRUGY6 Trademarks C66x is a trademark of Texas Instruments Incorporated. All other brand names and trademarks mentioned in this document are the property of Texas Instruments Incorporated or their respective owners, as applicable. ø-xx KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide SPRUGV9D June 2013

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