CS5460: Operating Systems. Lecture: Virtualization 2. Anton Burtsev March, 2013

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1 CS5460: Operating Systems Lecture: Virtualization 2 Anton Burtsev March, 2013

2 Paravirtualization: Xen

3 Full virtualization Complete illusion of physical hardware Trap _all_ sensitive instructions Virtualized OS PTE update (mov) Example: page table update Hypervisor

4 Full virtualization Complete illusion of physical hardware Trap _all_ sensitive instructions Example: page table update Virtualized OS PTE update (mov) Trap Hypervisor

5 Full virtualization Complete illusion of physical hardware Trap _all_ sensitive instructions Example: page table update Traps are slow Binary translation is faster, for some events Not for PTE updates, why? Virtualized OS PTE update (mov) Next instruction Trap Hypervisor if (safe) { update_pte(); emulate_mov(); }

6 Performance problems Traps are slow Binary translation is faster For some events Not for PTE updates, why? Virtualized OS PTE update (mov) Next instruction Trap Hypervisor if (safe) { update_pte(); emulate_mov(); }

7 Paravirtualization No illusion of hardware Instead: paravirtualized interface Explicit hypervisor calls to update sensitive state Page tables, interrupt flag But Guest OS needs porting Applications run natively in Ring 3

8 Paravirtualization Paravirtualized OS PTE update Batch updates update 1 update 2 Invoke hypervisor Hypervisor if (safe) update

9 Xen

10 Segmentation and paging

11 Hypervisor protection

12 Hardware support for virtualization: KVM

13 Basic idea Guest instruction stream VM Entry VMCS Guest State Host instruction stream Host State VM Exit

14 New mode of operation:vmx root VMX root operation 4 privilege levels VMX non-root operation 4 privilege levels as well, but unable to invoke VMX root instructions Guest runs until it performs exception causing it to exit Rich set of exit events Guest state and exit reason are stored in VMCS

15 Virtual machine control structure (VMCS) Guest State Loaded on entries Saved on exits Host State Saved on entries Loaded on exits Control fields Execution control, exits control, entries control

16 Guest state Register state Non-register state Activity state: active inactive (HLT, Shutdown, wait for Startup IPI interprocessor interrupt)) Interruptibility state

17 Host state Only register state ALU registers, also: Base page table address (CR3) Segment selectors Global descriptors table Interrupt descriptors table

18 VM-execution controls (asynchronous events control) External interrupts (maskable or IRQs) cause exits(yes/no) If not, then they delivered through guest IDT Bit 31 Bit 0 Reserved NMI cause exits (yes/no) If not, then they are delivered normally through guest IDT (descriptor 2)

19 VM-execution controls HLT PAUSE INVLPG Unconditional I/O Reserved MONITOR Bit 31 Activate I/O bitmaps (synchronous events control, not all reasons are shown) Bit 0

20 Exception bitmap (one for each of 32 IA-32 exceptions) IA-32 defines 32 exception vectors (interrupts 0-31) Each of them is configured to cause or not VM-exit Bit 31 Bit 0 14 page fault

21 I/O Bitmaps Two addresses on 4KB memory areas (A and B) A B Safe I/O addresses (not causing exits)

22 Exit information Information describing conditions of VM-exit is saved in VMCS It's different for different types of event

23 KVM

24 Memory virtualization: brute force. Write / read protected page table area. Every access results in VM-Exit and passes control to hypervisor Helper structures describe actual guest VM layout Guest PD CR3 PT Hypervisor TLB Hardware CPU stores pointer on guest page table directory Maintained for each guest. On VM-Exit hypervisor adjusts guest page accordingly.

25 Memory virtualization: shadow page tables Guest page table hierarchy It's writable, but can be inconsistent with active page table hierarchy stored by the hypervisor Active page table hierarchy Guest PD CR3 VMM maintains it for each VM that it supports PT TLB PD PT Hardware CPU stores pointer on active page table hierarchy. On Intel CPUs TLB is always refilled from active page table directory

26 Nested page tables 0 paged by gcr3 Guest Virtual gcr3 0 gpt Guest Physical Translation can be cached in TLB paged by hcr3 hcr3 VMM Host Virtual paged by CR3 0 hpt gpt Host Physical PT CR3 used by VMM

27 Page table lookup 4-level page table

28 Nested page table lookup

29 Efficient I/O

30 Where is the bottleneck What is the bottleneck in case of virtualization? CPU? CPU bound workloads execute natively on the real CPU Sometimes JIT compilation (binary translation makes them even faster [Dynamo] Everything what is inside VM is fast! What is the most frequent operation disturbing execution of VM? Device I/O! Disk, Network, Graphics

31 Virtual devices in Xen 31

32 Virtual devices in Xen 32

33 Virtual devices in Xen 33

34 Virtual devices in Xen 34

35 Virtual devices in Xen 35

36 How to make the I/O fast? Take into account specifics of the devicedriver communication Bulk Session oriented Connection is established once (during boot) No short IPCs, like function calls Costs of establishing an IPC channel are irrelevant Throughput oriented Large packets (512B 4K) Devices have high delays anyway Asynchronous Again, no function calls, devices are already asynchronous

37 Shared rings and events

38 Shared rings

39 Shared rings

40 Shared rings

41 Shared rings

42 Where is a performance bottleneck here?

43 Eliminate cache thrashing

44 GPUs Sending frames from the framebuffer No hardware acceleration Too slow OpenGL/DirectX level virtualization Send high-level OpenGL commands over rings OpenGL operations will be executed on the real GPU

45 Devices supporting virtualization

46 Some VM tricks: suspend/resume, checkpoints migration

47 Suspend

48 Resume

49 Checkpoints Checkpoints are almost suspend/resume Except that a copy of the entire VM s state has to be saved Memory Disk OK, it s relatively small 128MB-4GB Problem: disks are huge 100GB-1TB How to save storage efficiently?

50 Branching storage

51 Branching storage: snapshot

52 Branching storage: writes

53 Branching storage: snapshot

54 Migration Migration is essentially a live checkpoint between machines The goal: minimal downtime How to make the checkpoint faster?

55 Migration: memory

56 Migration: memory

57 Migration: memory

58 Migration: memory

59 Migration: storage

60 Migration

61 References Intel 64 and IA-32 Architectures Software Developer's Manual. Volume 3C: System Programming Guide, Part 3 Ravi Bhargava, Benjamin Serebrin, Francesco Spadini, and Srilatha Manne. Accelerating twodimensional page walks for virtualized systems. In ASPLOS'08.

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