TEST REPORT POWER SUPPLY AND THERMAL

Transcription

1 CERN European Organization for Nuclear Research Beams Department Radio Frequency RF Feedbacks and Beam Control TEST REPORT POWER SUPPLY AND THERMAL By: Petri Leinonen BE-RF-FB Date: (Update )

2 TABLE OF CONTENTS 1. INTRODUCTION TEST SETUP Device under test (DUT) Measurement setup in the lab Communication setup POWER SUPPLY TESTS Experiment 1: power supply voltages Objective Test setup Test results Analysis of the results Experiment 2: Power rail noise Objective Test setup Test results Analysis of the results THERMAL TESTS Experiment 3: Thermal measurement Objective Test setup Test results Analysis of the results CONCLUSION APPENDIX... 16

3 3 1. INTRODUCTION This document describes the results of the power supply and thermal tests of the version 1 of the FMC-DAC-4-CH-16bit-250MSPS mezzanine card; EDA The mezzanine card provides four independent channels, each generating a sample and hold analogue voltage proportional to its 16 bit input digital word fed through the connector linking it to the carrier board. The on-board Digital-to-Analogue Converters (DAC) generate a current which full scale value can be programmed via a Serial Peripheral Interface (SPI) between values ranging from 8.64mA to 31.7mA. After this stage an I-to-V-conversion is performed. The produced voltage is amplified and fed to a dual-position attenuator (typically 0dB and -18 db). The aim of this latter circuit is to extend the dynamic range of the output from 16 to 19 bits. When the digital signal has low amplitude, it is digitally amplified by 18 db and simultaneously attenuated by the same amount in the analogue domain. This result in more bits involved for the same output amplitude and thus more resolution. The signal is then further amplified and filtered to remove the sampling aliases. The sampling rate is from DC to 250 Ms/s. The mezzanine card is designed to be plugged on a carrier card which has a High Pin Count (HPC) FMC 400-pin connector and includes an FPGA where the mezzanine card data is being processed. This unit is foreseen to be used in a so-called beam control system, typically to generate a radio frequency (RF) modulated signal that feeds, after amplification, the accelerating cavities. In this latter context, the firmware block controlling this DAC board is called SDDS (Slave Direct Digital Synthesizer). Within the beam control system, the sampling clock is a high harmonic of the particles revolution frequency, provided by another FMC mezzanine board called Master Direct Digital Synthesizer or MDDS. This sampling rate value was chosen in order to ease the creation of the accelerating voltage which is also a harmonic of the revolution. 1 CERN Identification number for documents in EDMS(Equipment Data Management Service) EDA-02069:

4 4 2. TEST SETUP The test setup consists of three boards: a DAC mezzanine card, a transition board and a ML605 evaluation board. The ML605 provides the data processing (in a Virtex 6 FPGA) and the power via the transition board to the mezzanine card. In addition, the ML605 evaluation kit provides various interfaces and connectors to be used with the external world. The transition board provides a clock signal for the DAC board and it is used to change some voltage levels in order to be compliant with the 2.5V FPGA IOs.

5 Device under test (DUT) Figure 1. The mezzanine card hardware: a) the bottom side b) and the top side.

6 Measurement setup in the lab Figure 2. DUT, Transition board and ML605 evaluation kit test setup (from top to bottom) Communication setup The evaluation kit provides a test platform for the firmware and the daughter card hardware. At first, the communication channel was established between the daughter card and the ML605 board. The programming of the FPGA is done with the JTAG connection. After initializing the JTAG chain under Xilinx ISE, the FPGA was loaded with the firmware code. The communication itself happens through an UART-port. The data is sent from the computer and received by the evaluation kit, via a USB-cable, in serial format. The evolution kit has an USB-to-UART bridge on board which allows the data to be transferred via the USB port. The baud rate of the connection is 9600 bps. Python was used for programming the computer user interface. Python is a high-level object orientated language and it was selected to be the test interface with the evaluation kit. Python provides an open-source environment and easily readable code structure. In addition, it is a scripting language which makes it a powerful tool for hardware testing.

7 7 3. POWER SUPPLY TESTS 3.1. Experiment 1: power supply voltages Objective The aim is to verify the power supply voltages and to find out whether they are within the ±5% tolerance as specified in the FMC standard Test setup The power supply was measured with an oscilloscope (Tektronix DPO72545, 2.5GHz, 40Gs/s) and with a multimeter (Fluke 87). The transition board works as an adapter and routes the power pins (+12V, +3.3V, +3.3VAUX and the VADJ of +3.3V) from the ML605 evaluation kit via the DAC transition board to the DAC daughter card. The schematic of the DAC mezzanine card (EDA-02069) and the transition board (EDA-02227) can be found from the CERN EDMS web site Test results Table 1 shows the results of the DAC mezzanine card power supply with the peak-to-peak noise amplitudes. The Appendix 1 shows the power distribution network of the mezzanine card. Table 1: Measured power supply values with their tolerances Power supply Measured value 5% tolerance +12V V, ok +[ ]V +5V +5.02, ok +[ ]V -5V V, too low -[ ]V +3.3V V, ok +[ ]V +3.3V filtered_analog V, ok +[ ]V +3.3VAUX V, ok +[ ]V +1.8V V, ok +[ ]V +0.4V V, ok +[ ]V Analysis of the results The -5V has a 221mV voltage drop and this might cause the bias voltage amplifier to shift. Complete tests were carried out for the switching regulator (MAX889T) and it appeared that the component was not able to provide even a small amount of current to any resistive load. The voltage started to drop even when only a 10mA was drawn from the regulator. This already created a voltage drop of 30mV. The second version of the DAC board will be

8 8 equipped with another regulator. The +0.4V in Table 1 is the common mode voltage which is needed for the differential clock input of the D/A-converter Experiment 2: Power rail noise Objective The aim is to measure the power rail noise level. See Test setup Test results Figure 3 shows the reference noise which comes from the instrument and any possible probes attached. The reference value of 27.6mV is a good comparison value and will be negligible compared to the measured power supply noise value. Figure 3. Reference noise.

9 9 Figure 4 shows the noise results of one of the power rails, 2.5V. Figure 4. The noise peak-to-peak amplitude of the 2.5V power rail which is generated by the ML605 regulators.

10 10 Figure 5 indicates the 500 khz switching noise measured in the 3.3V power rail. Figure kHz switching noise in the 3.3V filtered_analog power rail.

11 11 Figure kHz switching noise seen in the ground plane. Table 2: Power supply voltages with their peak-to-peak noise levels. Power supply +12V +5V -5V +3.3V +3.3V filtered_analog +3.3VAUX +2.5V +1.8V Peak-to-peak noise 300mV 150mV 150mV 120mV 90mV 328mV 171mV 240mV Analysis of the results The power and ground planes suffer from a 500kHz switching noise which is generated by the MAX889T charge pump. Also the evaluation kit ML605 has DC-DC converter modules, PTD08A010W and PTD08A020W, which work with 500 khz frequency. Thus, additional side bands are added to the spectrum of the transition board clock signal and the clock fan-out buffer is affected by this switching noise. The mezzanine card suffers from this switching noise in all of the supplies because of poor filtering on the mezzanine card. The peak-to-peak noise levels can be seen from the table above.

12 12 The instrument has a noise floor of 27.2 mv pp and therefore is negligible compared to the measured noise levels.

13 13 4. THERMAL TESTS 4.1. Experiment 3: Thermal measurement Objective The aim of the thermal measurement is to measure the overall temperature on the board Test setup Thermal tests were carried out by using a Fluke Ti20 Thermal imager. The instrument measures the temperature on the board in Celsius and shows the results real time with an infra-red image Test results All the prototypes have an overall temperature of 30 C throughout the board besides the LT1763 regulator chip which dissipates +70 degrees Celsius. Figure 7 shows the LT1763 regulator with an infra-red image on the top of the image. Figure 7. Thermal image of the LT1763 regulator on the DAC board heating up to +70 Celsius Analysis of the results The physical size of the chip is x mm and that creates the component to heat up in a small area of 0.20cm 2. This happens because of the voltage drop between the input +12V and the output +5V turns into heat. The heat distributes throughout the ground planes in the PCB and that provides some cooling for the chip but not sufficient enough. The investigation with the thermal imager did not show any additional heat sources. During the measurements the pointer of the imager was placed directly on the chip and it showed that the heat comes from the silicon die itself as expected. The use of fans reduced

14 14 the temperature by almost 5 C but that still will cause component aging and/or noise due to the heat on board. Replacing this component with a switching regulator is an option but it will produce more noise to the power supply and it should be filtered accordingly. The LT1763 regulator is generating the +5V and the +5V acts as an input for the generation of - 5V. The +5V and -5V power up the amplifiers. The noise source of the amplifier needs to be kept to a minimum and therefore a new regulator chip needs to be selected for the version 2 of the HW.

15 15 5. CONCLUSION The power supply and thermal test results of the DAC mezzanine card EDA version 1 show that most of the voltages are within tolerance of ±5%. +12V, +5V, -5V, +3.3V, +3.3V filtered_analog, +3.3VAUX, +1.8V and +0.4V were measured and besides -5V, all of them were sufficient to supply the power on the mezzanine card. The power supply noise levels were also measured and some of them were too high. The next version of the hardware needs better filtering on board and in that way the noise levels could be reduced. In addition, the linear regulator that generates the +5V creates too much heat and that will again produce more noise on board. For the second version of the mezzanine card the +5V and -5V power supplies will be replaced with switching DC-DC regulators. This will solve the problem regarding the heat and noise levels as long as sufficient filtering is provided.

16 16 6. APPENDIX Appendix 1. Simplified model of the power generation on the DAC mezzanine card