Compiler Optimisation
|
|
|
- Tabitha McBride
- 7 years ago
- Views:
Transcription
1 Compiler Optimisation 6 Instruction Scheduling Hugh Leather IF 1.18a hleather@inf.ed.ac.uk Institute for Computing Systems Architecture School of Informatics University of Edinburgh 2017
2 Introduction This lecture: Scheduling to hide latency and exploit ILP Dependence graph Local list Scheduling + priorities Forward versus backward scheduling Software pipelining of loops
3 Latency, functional units, and ILP Instructions take clock cycles to execute (latency) Modern machines issue several operations per cycle Cannot use results until ready, can do something else Execution time is order-dependent Latencies not always constant (cache, early exit, etc) Operation Cycles load, store 3 load / cache 100s loadi, add, shift 1 mult 2 div 40 branch 0 8
4 Machine types In order Deep pipelining allows multiple instructions Superscalar Multiple functional units, can issue > 1 instruction Out of order Large window of instructions can be reordered dynamically VLIW Compiler statically allocates to FUs
5 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Simple schedule 1 a := 2*a*b*c Cycle Operations Operands waiting loadai r r 1 add r 1, r 1 r 1 loadai r r 2 mult r 1, r 2 r 1 loadai r r 2 mult r 1, r 2 r 1 storeai r 1 r Done 1 loads/stores 3 cycles, mults 2, adds 1
6 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Simple schedule 1 a := 2*a*b*c Cycle Operations Operands waiting 1 loadai r r 1 r 1 2 r 1 3 r 1 add r 1, r 1 r 1 loadai r r 2 mult r 1, r 2 r 1 loadai r r 2 mult r 1, r 2 r 1 storeai r 1 r Done 1 loads/stores 3 cycles, mults 2, adds 1
7 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Simple schedule 1 a := 2*a*b*c Cycle Operations Operands waiting 1 loadai r r 1 r 1 2 r 1 3 r 1 4 add r 1, r 1 r 1 r 1 loadai r r 2 mult r 1, r 2 r 1 loadai r r 2 mult r 1, r 2 r 1 storeai r 1 r Done 1 loads/stores 3 cycles, mults 2, adds 1
8 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Simple schedule 1 a := 2*a*b*c Cycle Operations Operands waiting 1 loadai r r 1 r 1 2 r 1 3 r 1 4 add r 1, r 1 r 1 r 1 5 loadai r r 2 r 2 6 r 2 7 r 2 mult r 1, r 2 r 1 loadai r r 2 mult r 1, r 2 r 1 storeai r 1 r Done 1 loads/stores 3 cycles, mults 2, adds 1
9 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Simple schedule 1 a := 2*a*b*c Cycle Operations Operands waiting 1 loadai r r 1 r 1 2 r 1 3 r 1 4 add r 1, r 1 r 1 r 1 5 loadai r r 2 r 2 6 r 2 7 r 2 8 mult r 1, r 2 r 1 r 1 9 Next op does not use r 1 r 1 loadai r r 2 mult r 1, r 2 r 1 storeai r 1 r Done 1 loads/stores 3 cycles, mults 2, adds 1
10 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Simple schedule 1 a := 2*a*b*c Cycle Operations Operands waiting 1 loadai r r 1 r 1 2 r 1 3 r 1 4 add r 1, r 1 r 1 r 1 5 loadai r r 2 r 2 6 r 2 7 r 2 8 mult r 1, r 2 r 1 r 1 9 loadai r r 2 r 1, r 2 10 r 2 11 r 2 mult r 1, r 2 r 1 storeai r 1 r Done 1 loads/stores 3 cycles, mults 2, adds 1
11 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Simple schedule 1 a := 2*a*b*c Cycle Operations Operands waiting 1 loadai r r 1 r 1 2 r 1 3 r 1 4 add r 1, r 1 r 1 r 1 5 loadai r r 2 r 2 6 r 2 7 r 2 8 mult r 1, r 2 r 1 r 1 9 loadai r r 2 r 1, r 2 10 r 2 11 r 2 12 mult r 1, r 2 r 1 r 1 13 r 1 storeai r 1 r Done 1 loads/stores 3 cycles, mults 2, adds 1
12 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Simple schedule 1 a := 2*a*b*c Cycle Operations Operands waiting 1 loadai r r 1 r 1 2 r 1 3 r 1 4 add r 1, r 1 r 1 r 1 5 loadai r r 2 r 2 6 r 2 7 r 2 8 mult r 1, r 2 r 1 r 1 9 loadai r r 2 r 1, r 2 10 r 2 11 r 2 12 mult r 1, r 2 r 1 r 1 13 r 1 14 storeai r 1 r store to complete 15 store to complete 16 store to complete Done 1 loads/stores 3 cycles, mults 2, adds 1
13 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Schedule loads early 2 a := 2*a*b*c Cycle Operations Operands waiting loadai r r 1 loadai r r 2 loadai r r 3 add r 1, r 1 r 1 mult r 1, r 2 r 1 mult r 1, r 2 r 1 storeai r 1 r Done 2 loads/stores 3 cycles, mults 2, adds 1
14 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Schedule loads early 2 a := 2*a*b*c Cycle Operations Operands waiting 1 loadai r r 1 r 1 loadai r r 2 loadai r r 3 add r 1, r 1 r 1 mult r 1, r 2 r 1 mult r 1, r 3 r 1 storeai r 1 r Done 2 loads/stores 3 cycles, mults 2, adds 1
15 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Schedule loads early 2 a := 2*a*b*c Cycle Operations Operands waiting 1 loadai r r 1 r 1 2 loadai r r 2 r 1, r 2 loadai r r 3 add r 1, r 1 r 1 mult r 1, r 2 r 1 mult r 1, r 3 r 1 storeai r 1 r Done 2 loads/stores 3 cycles, mults 2, adds 1
16 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Schedule loads early 2 a := 2*a*b*c Cycle Operations Operands waiting 1 loadai r r 1 r 1 2 loadai r r 2 r 1, r 2 3 loadai r r 3 r 1, r 2, r 3 add r 1, r 1 r 1 mult r 1, r 2 r 1 mult r 1, r 3 r 1 storeai r 1 r Done 2 loads/stores 3 cycles, mults 2, adds 1
17 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Schedule loads early 2 a := 2*a*b*c Cycle Operations Operands waiting 1 loadai r r 1 r 1 2 loadai r r 2 r 1, r 2 3 loadai r r 3 r 1, r 2, r 3 4 add r 1, r 1 r 1 r 1, r 2, r 3 mult r 1, r 2 r 1 mult r 1, r 3 r 1 storeai r 1 r Done 2 loads/stores 3 cycles, mults 2, adds 1
18 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Schedule loads early 2 a := 2*a*b*c Cycle Operations Operands waiting 1 loadai r r 1 r 1 2 loadai r r 2 r 1, r 2 3 loadai r r 3 r 1, r 2, r 3 4 add r 1, r 1 r 1 r 1, r 2, r 3 5 mult r 1, r 2 r 1 r 1, r 3 6 r 1 mult r 1, r 3 r 1 storeai r 1 r Done 2 loads/stores 3 cycles, mults 2, adds 1
19 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Schedule loads early 2 a := 2*a*b*c Cycle Operations Operands waiting 1 loadai r r 1 r 1 2 loadai r r 2 r 1, r 2 3 loadai r r 3 r 1, r 2, r 3 4 add r 1, r 1 r 1 r 1, r 2, r 3 5 mult r 1, r 2 r 1 r 1, r 3 6 r 1 7 mult r 1, r 3 r 1 r 1 8 r 1 storeai r 1 r Done 2 loads/stores 3 cycles, mults 2, adds 1
20 Effect of scheduling Superscalar, 1 FU: New op each cycle if operands ready Schedule loads early 2 a := 2*a*b*c Cycle Operations Operands waiting 1 loadai r r 1 r 1 2 loadai r r 2 r 1, r 2 3 loadai r r 3 r 1, r 2, r 3 4 add r 1, r 1 r 1 r 1, r 2, r 3 5 mult r 1, r 2 r 1 r 1, r 3 6 r 1 7 mult r 1, r 3 r 1 r 1 8 r 1 9 storeai r 1 r store to complete 10 store to complete 11 store to complete Done Uses one more register 11 versus 16 cycles 31% faster! 2 loads/stores 3 cycles, mults 2, adds 1
21 Scheduling problem Schedule maps operations to cycle; a Ops, S(a) N Respect latency; a, b Ops, a dependson b = S(a) S(b) + λ(b) Respect function units; no more ops per type per cycle than FUs can handle Length of schedule, L(S) = max a Ops (S(a) + λ(a)) Schedule S is time-optimal if S 1, L(S) L(S 1 ) Problem: Find a time-optimal schedule 3 Even local scheduling with many restrictions is NP-complete 3 A schedule might also be optimal in terms of registers, power, or space
22 List scheduling Local greedy heuristic to produce schedules for single basic blocks 1 Rename to avoid anti-dependences 2 Build dependency graph 3 Prioritise operations 4 For each cycle 1 Choose the highest priority ready operation & schedule it 2 Update ready queue
23 List scheduling Dependence/Precedence graph Schedule operation only when operands ready Build dependency graph of read-after-write (RAW) deps Label with latency and FU requirements Example: a = 2*a*b*c
24 List scheduling Dependence/Precedence graph Schedule operation only when operands ready Build dependency graph of read-after-write (RAW) deps Label with latency and FU requirements Anti-dependences (WAR) restrict movement Example: a = 2*a*b*c
25 List scheduling Dependence/Precedence graph Schedule operation only when operands ready Build dependency graph of read-after-write (RAW) deps Label with latency and FU requirements Anti-dependences (WAR) restrict movement renaming removes Example: a = 2*a*b*c
26 List scheduling List scheduling algorithm Cycle 1 Ready leaves of (D) Active while(ready Active ) a Active where S(a) + λ(a) Cycle Active Active - a b succs(a) where isready(b) Ready Ready b if a Ready and b, a priority b priority Ready Ready - a S(op) Cycle Active Active a Cycle Cycle + 1
27 List scheduling Priorities Many different priorities used Quality of schedules depends on good choice The longest latency path or critical path is a good priority Tie breakers Last use of a value - decreases demand for register as moves it nearer def Number of descendants - encourages scheduler to pursue multiple paths Longer latency first - others can fit in shadow Random
28 List scheduling Example: Schedule with priority by critical path length
29 List scheduling Example: Schedule with priority by critical path length
30 List scheduling Example: Schedule with priority by critical path length
31 List scheduling Example: Schedule with priority by critical path length
32 List scheduling Example: Schedule with priority by critical path length
33 List scheduling Example: Schedule with priority by critical path length
34 List scheduling Example: Schedule with priority by critical path length
35 List scheduling Example: Schedule with priority by critical path length
36 List scheduling Example: Schedule with priority by critical path length
37 List scheduling Example: Schedule with priority by critical path length
38 List scheduling Example: Schedule with priority by critical path length
39 List scheduling Example: Schedule with priority by critical path length
40 List scheduling Forward vs backward Can schedule from root to leaves (backward) May change schedule time List scheduling cheap, so try both, choose best
41 List scheduling Forward vs backward Opcode loadi lshift add addi cmp store Latency
42 List scheduling Forward vs backward Forwards Int Int Stores 1 loadi 1 lshift 2 loadi 2 loadi 3 3 loadi 4 add 1 4 add 2 add 3 5 add 4 addi store 1 6 cmp store 2 7 store 3 8 store 4 9 store cbr Backwards Int Int Stores 1 loadi 1 2 addi lshift 3 add 4 loadi 3 4 add 3 loadi 2 store 5 5 add 2 loadi 1 store 4 6 add 1 store 3 7 store 2 8 store cmp 12 cbr
43 Scheduling Larger Regions Schedule extended basic blocks (EBBs) Super block cloning Schedule traces Software pipelining
44 Scheduling Larger Regions Extended basic blocks Extended basic block EBB is maximal set of blocks such that Set has a single entry, B i Each block B j other than B i has exactly one predecessor
45 Scheduling Larger Regions Extended basic blocks Extended basic block EBB is maximal set of blocks such that Set has a single entry, B i Each block B j other than B i has exactly one predecessor
46 Scheduling Larger Regions Extended basic blocks Schedule entire paths through EBBs Example has four EBB paths
47 Scheduling Larger Regions Extended basic blocks Schedule entire paths through EBBs Example has four EBB paths
48 Scheduling Larger Regions Extended basic blocks Schedule entire paths through EBBs Example has four EBB paths
49 Scheduling Larger Regions Extended basic blocks Schedule entire paths through EBBs Example has four EBB paths
50 Scheduling Larger Regions Extended basic blocks Schedule entire paths through EBBs Example has four EBB paths Having B 1 in both causes conflicts Moving an op out of B 1 causes problems
51 Scheduling Larger Regions Extended basic blocks Schedule entire paths through EBBs Example has four EBB paths Having B 1 in both causes conflicts Moving an op out of B 1 causes problems Must insert compensation code
52 Scheduling Larger Regions Extended basic blocks Schedule entire paths through EBBs Example has four EBB paths Having B 1 in both causes conflicts Moving an op into B 1 causes problems
53 Scheduling Larger Regions Superblock cloning Join points create context problems
54 Scheduling Larger Regions Superblock cloning Join points create context problems Clone blocks to create more context
55 Scheduling Larger Regions Superblock cloning Join points create context problems Clone blocks to create more context Merge any simple control flow
56 Scheduling Larger Regions Superblock cloning Join points create context problems Clone blocks to create more context Merge any simple control flow Schedule EBBs
57 Scheduling Larger Regions Trace scheduling Edge frequency from profile (not block frequency)
58 Scheduling Larger Regions Trace scheduling Edge frequency from profile (not block frequency) Pick hot path Schedule with compensation code
59 Scheduling Larger Regions Trace scheduling Edge frequency from profile (not block frequency) Pick hot path Schedule with compensation code Remove from CFG
60 Scheduling Larger Regions Trace scheduling Edge frequency from profile (not block frequency) Pick hot path Schedule with compensation code Remove from CFG Repeat
61 Loop scheduling Loop structures can dominate execution time Specialist technique software pipelining Allows application of list scheduling to loops Why not loop unrolling?
62 Loop scheduling Loop structures can dominate execution time Specialist technique software pipelining Allows application of list scheduling to loops Why not loop unrolling? Allows loop effect to become arbitrarily small, but Code growth, cache pressure, register pressure
63 Software pipelining Consider simple loop to sum array
64 Software pipelining Schedule on 1 FU - 5 cycles load 3 cycles, add 1 cycle, branch 1 cycle
65 Software pipelining Schedule on VLIW 3 FUs - 4 cycles load 3 cycles, add 1 cycle, branch 1 cycle
66 Software pipelining A better steady state schedule exists load 3 cycles, add 1 cycle, branch 1 cycle
67 Software pipelining Requires prologue and epilogue (may schedule others in epilogue) load 3 cycles, add 1 cycle, branch 1 cycle
68 Software pipelining Respect dependences and latency including loop carries load 3 cycles, add 1 cycle, branch 1 cycle
69 Software pipelining Complete code load 3 cycles, add 1 cycle, branch 1 cycle
70 Software pipelining Some definitions Initiation interval (ii) Number of cycles between initiating loop iterations Original loop had ii of 5 cycles Final loop had ii of 2 cycles Recurrence Loop-based computation whose value is used in later loop iteration Might be several iterations later Has dependency chain(s) on itself Recurrence latency is latency of dependency chain
71 Software pipelining Algorithm Choose an initiation interval, ii Compute lower bounds on ii Shorter ii means faster overall execution Generate a loop body that takes ii cycles Try to schedule into ii cycles, using modulo scheduler If it fails, increase ii by one and try again Generate the needed prologue and epilogue code For prologue, work backward from upward exposed uses in the scheduled loop body For epilogue, work forward from downward exposed definitions in the scheduled loop body
72 Software pipelining Initial initiation interval (ii) Starting value for ii based on minimum resource and recurrence constraints Resource constraint ii must be large enough to issue every operation Let N u = number of FUs of type u Let I u = number of operations of type u I u /N u is lower bound on ii for type u max u ( I u /N u ) is lower bound on ii
73 Software pipelining Initial initiation interval (ii) Starting value for ii based on minimum resource and recurrence constraints Recurrence constraint ii cannot be smaller than longest recurrence latency Recurrence r is over k r iterations with latency λ r λ r /k u is lower bound on ii for type r max r ( λ r /k u ) is lower bound on ii
74 Software pipelining Initial initiation interval (ii) Starting value for ii based on minimum resource and recurrence constraints Start value = max(max u ( I u /N u ), max r ( λ r /k u ) For simple loop a = A[ i ] b = b + a i = i + 1 if i < n goto end Resource constraint Memory Integer Branch I u N u I u /N u Recurrence constraint b i k r 1 1 λ r 2 1 I u /N u 2 1
75 Software pipelining Modulo scheduling Modulo scheduling Schedule with cycle modulo initiation interval
76 Software pipelining Modulo scheduling Modulo scheduling Schedule with cycle modulo initiation interval
77 Software pipelining Modulo scheduling Modulo scheduling Schedule with cycle modulo initiation interval
78 Software pipelining Modulo scheduling Modulo scheduling Schedule with cycle modulo initiation interval
79 Software pipelining Modulo scheduling Modulo scheduling Schedule with cycle modulo initiation interval
80 Software pipelining Current research Much research in different software pipelining techniques Difficult when there is general control flow in the loop Predication in IA64 for example really helps here Some recent work in exhaustive scheduling -i.e. solve the NP-complete problem for basic blocks
81 Summary Scheduling to hide latency and exploit ILP Dependence graph - dependences between instructions + latency Local list Scheduling + priorities Forward versus backward scheduling Scheduling EBBs, superblock cloning, trace scheduling Software pipelining of loops
82 PPar CDT Advert 4-year programme: MSc by Research + PhD Research-focused: Work on your thesis topic from the start Collaboration between: University of Edinburgh s School of Informatics Ranked top in the UK by 2014 REF Edinburgh Parallel Computing Centre UK s largest supercomputing centre Research topics in software, hardware, theory and application of: Parallelism Concurrency Distribution Full funding available Industrial engagement programme includes internships at leading companies Now accepting applications! Find out more and apply at: pervasiveparallelism.inf.ed.ac.uk The biggest revolution in the technological landscape for fifty years
Software Pipelining. for (i=1, i<100, i++) { x := A[i]; x := x+1; A[i] := x
![Software Pipelining. for (i=1, i<100, i++) { x := A[i]; x := x+1; A[i] := x](/thumbs/25/6459870.jpg "Software Pipelining. for (i=1, i<100, i++) { x := A[i]; x := x+1; A[i] := x")
Software Pipelining for (i=1, i
AN IMPLEMENTATION OF SWING MODULO SCHEDULING WITH EXTENSIONS FOR SUPERBLOCKS TANYA M. LATTNER
AN IMPLEMENTATION OF SWING MODULO SCHEDULING WITH EXTENSIONS FOR SUPERBLOCKS BY TANYA M. LATTNER B.S., University of Portland, 2000 THESIS Submitted in partial fulfillment of the requirements for the degree
VLIW Processors. VLIW Processors
1 VLIW Processors VLIW ( very long instruction word ) processors instructions are scheduled by the compiler a fixed number of operations are formatted as one big instruction (called a bundle) usually LIW
Instruction Scheduling. Software Pipelining - 2
and Software Pipelining - 2 Department of Computer Science and Automation Indian Institute of Science Bangalore 560 012 NPTEL Course on Principles of Compiler Design Outline Simple Basic Block Scheduling
Administration. Instruction scheduling. Modern processors. Examples. Simplified architecture model. CS 412 Introduction to Compilers
CS 4 Introduction to Compilers ndrew Myers Cornell University dministration Prelim tomorrow evening No class Wednesday P due in days Optional reading: Muchnick 7 Lecture : Instruction scheduling pr 0 Modern
Module: Software Instruction Scheduling Part I
Module: Software Instruction Scheduling Part I Sudhakar Yalamanchili, Georgia Institute of Technology Reading for this Module Loop Unrolling and Instruction Scheduling Section 2.2 Dependence Analysis Section
Software Pipelining - Modulo Scheduling
EECS 583 Class 12 Software Pipelining - Modulo Scheduling University of Michigan October 15, 2014 Announcements + Reading Material HW 2 Due this Thursday Today s class reading» Iterative Modulo Scheduling:
Static Scheduling. option #1: dynamic scheduling (by the hardware) option #2: static scheduling (by the compiler) ECE 252 / CPS 220 Lecture Notes
basic pipeline: single, in-order issue first extension: multiple issue (superscalar) second extension: scheduling instructions for more ILP option #1: dynamic scheduling (by the hardware) option #2: static
EECS 583 Class 11 Instruction Scheduling Software Pipelining Intro
EECS 58 Class Instruction Scheduling Software Pipelining Intro University of Michigan October 8, 04 Announcements & Reading Material Reminder: HW Class project proposals» Signup sheet available next Weds
EE482: Advanced Computer Organization Lecture #11 Processor Architecture Stanford University Wednesday, 31 May 2000. ILP Execution
EE482: Advanced Computer Organization Lecture #11 Processor Architecture Stanford University Wednesday, 31 May 2000 Lecture #11: Wednesday, 3 May 2000 Lecturer: Ben Serebrin Scribe: Dean Liu ILP Execution
Instruction scheduling
Instruction ordering Instruction scheduling Advanced Compiler Construction Michel Schinz 2015 05 21 When a compiler emits the instructions corresponding to a program, it imposes a total order on them.
Software Pipelining. Y.N. Srikant. NPTEL Course on Compiler Design. Department of Computer Science Indian Institute of Science Bangalore 560 012
Department of Computer Science Indian Institute of Science Bangalore 560 2 NPTEL Course on Compiler Design Introduction to Overlaps execution of instructions from multiple iterations of a loop Executes
Solution: start more than one instruction in the same clock cycle CPI < 1 (or IPC > 1, Instructions per Cycle) Two approaches:
Multiple-Issue Processors Pipelining can achieve CPI close to 1 Mechanisms for handling hazards Static or dynamic scheduling Static or dynamic branch handling Increase in transistor counts (Moore s Law):
More on Pipelining and Pipelines in Real Machines CS 333 Fall 2006 Main Ideas Data Hazards RAW WAR WAW More pipeline stall reduction techniques Branch prediction» static» dynamic bimodal branch prediction
Fli;' HEWLETT. Iterative Modulo Scheduling. B. Ramakrishna Rau Compiler and Architecture Research HPL-94-115 November, 1995
Fli;' HEWLETT a:~ PACKARD Iterative Modulo Scheduling B. Ramakrishna Rau Compiler and Architecture Research HPL-94-115 November, 1995 modulo scheduling, instruction scheduling, software pipelining, loop
Using Power to Improve C Programming Education
Using Power to Improve C Programming Education Jonas Skeppstedt Department of Computer Science Lund University Lund, Sweden jonas.skeppstedt@cs.lth.se jonasskeppstedt.net jonasskeppstedt.net jonas.skeppstedt@cs.lth.se
Software Pipelining by Modulo Scheduling. Philip Sweany University of North Texas
Software Pipelining by Modulo Scheduling Philip Sweany University of North Texas Overview Opportunities for Loop Optimization Software Pipelining Modulo Scheduling Resource and Dependence Constraints Scheduling
Instruction Set Design
Instruction Set Design Instruction Set Architecture: to what purpose? ISA provides the level of abstraction between the software and the hardware One of the most important abstraction in CS It s narrow,
INSTRUCTION LEVEL PARALLELISM PART VII: REORDER BUFFER
Course on: Advanced Computer Architectures INSTRUCTION LEVEL PARALLELISM PART VII: REORDER BUFFER Prof. Cristina Silvano Politecnico di Milano cristina.silvano@polimi.it Prof. Silvano, Politecnico di Milano
A Lab Course on Computer Architecture
A Lab Course on Computer Architecture Pedro López José Duato Depto. de Informática de Sistemas y Computadores Facultad de Informática Universidad Politécnica de Valencia Camino de Vera s/n, 46071 - Valencia,
CS521 CSE IITG 11/23/2012
CS521 CSE TG 11/23/2012 A Sahu 1 Degree of overlap Serial, Overlapped, d, Super pipelined/superscalar Depth Shallow, Deep Structure Linear, Non linear Scheduling of operations Static, Dynamic A Sahu slide
A high-level implementation of software pipelining in LLVM
A high-level implementation of software pipelining in LLVM Roel Jordans 1, David Moloney 2 1 Eindhoven University of Technology, The Netherlands r.jordans@tue.nl 2 Movidius Ltd., Ireland 2015 European
To appear in MICRO-25 Conference Proceedings, December 1992 1. Enhanced Modulo Scheduling for Loops with Conditional Branches
To appear in MICRO-5 Conference Proceedings, December 199 1 Enhanced Modulo Scheduling for Loops with Conditional Branches Nancy J. Warter Grant E. Haab John W. Bockhaus Krishna Subramanian Coordinated
Multi-core architectures. Jernej Barbic 15-213, Spring 2007 May 3, 2007
Multi-core architectures Jernej Barbic 15-213, Spring 2007 May 3, 2007 1 Single-core computer 2 Single-core CPU chip the single core 3 Multi-core architectures This lecture is about a new trend in computer
Scheduling Shop Scheduling. Tim Nieberg
Scheduling Shop Scheduling Tim Nieberg Shop models: General Introduction Remark: Consider non preemptive problems with regular objectives Notation Shop Problems: m machines, n jobs 1,..., n operations
Software Programmable DSP Platform Analysis Episode 7, Monday 19 March 2007, Ingredients. Software Pipelining. Data Dependence. Resource Constraints
Software Programmable DSP Platform Analysis Episode 7, Monday 19 March 7, Ingredients Software Pipelining Data & Resource Constraints Resource Constraints in C67x Loop Scheduling Without Resource Bounds
Introduction to Data-flow analysis
Introduction to Data-flow analysis Last Time LULESH intro Typed, 3-address code Basic blocks and control flow graphs LLVM Pass architecture Data dependencies, DU chains, and SSA Today CFG and SSA example
Software implementation of Post-Quantum Cryptography
Software implementation of Post-Quantum Cryptography Peter Schwabe Radboud University Nijmegen, The Netherlands October 20, 2013 ASCrypto 2013, Florianópolis, Brazil Part I Optimizing cryptographic software
Lecture 2 Introduction to Data Flow Analysis
Lecture 2 Introduction to Data Flow Analysis I. Introduction II. Example: Reaching definition analysis III. Example: Liveness analysis IV. A General Framework (Theory in next lecture) Reading: Chapter
Post-Pass Periodic Register Allocation to Minimise Loop Unrolling Degree
Post-Pass Periodic Register Allocation to Minimise Loop Unrolling Degree Mounira BACHIR, Sid-Ahmed-Ali TOUATI, Albert COHEN April 10, 2009 Abstract This paper solves an open problem regarding loop unrolling
Chapter 5 Instructor's Manual
The Essentials of Computer Organization and Architecture Linda Null and Julia Lobur Jones and Bartlett Publishers, 2003 Chapter 5 Instructor's Manual Chapter Objectives Chapter 5, A Closer Look at Instruction
Evaluation of Different Task Scheduling Policies in Multi-Core Systems with Reconfigurable Hardware
Evaluation of Different Task Scheduling Policies in Multi-Core Systems with Reconfigurable Hardware Mahyar Shahsavari, Zaid Al-Ars, Koen Bertels,1, Computer Engineering Group, Software & Computer Technology
Cost Model: Work, Span and Parallelism. 1 The RAM model for sequential computation:
CSE341T 08/31/2015 Lecture 3 Cost Model: Work, Span and Parallelism In this lecture, we will look at how one analyze a parallel program written using Cilk Plus. When we analyze the cost of an algorithm
Introduction to Cloud Computing
Introduction to Cloud Computing Parallel Processing I 15 319, spring 2010 7 th Lecture, Feb 2 nd Majd F. Sakr Lecture Motivation Concurrency and why? Different flavors of parallel computing Get the basic
Wiggins/Redstone: An On-line Program Specializer
Wiggins/Redstone: An On-line Program Specializer Dean Deaver Rick Gorton Norm Rubin {dean.deaver,rick.gorton,norm.rubin}@compaq.com Hot Chips 11 Wiggins/Redstone 1 W/R is a Software System That: u Makes
2) Write in detail the issues in the design of code generator.
COMPUTER SCIENCE AND ENGINEERING VI SEM CSE Principles of Compiler Design Unit-IV Question and answers UNIT IV CODE GENERATION 9 Issues in the design of code generator The target machine Runtime Storage
Interpreters and virtual machines. Interpreters. Interpreters. Why interpreters? Tree-based interpreters. Text-based interpreters
Interpreters and virtual machines Michel Schinz 2007 03 23 Interpreters Interpreters Why interpreters? An interpreter is a program that executes another program, represented as some kind of data-structure.
Fli;' HEWLETT. Software Pipelining and Superblock Scheduling: Compilation Techniques for VLIW Machines
Fli;' HEWLETT a:~ PACKARD Software Pipelining and Superblock Scheduling: Compilation Techniques for VLIW Machines Meng Lee, Partha Tirumalai, Tin-Fook Ngai Computer Systems Laboratory HPL-92-78 June, 1992
Where we are CS 4120 Introduction to Compilers Abstract Assembly Instruction selection mov e1 , e2 jmp e cmp e1 , e2 [jne je jgt ] l push e1 call e
![Where we are CS 4120 Introduction to Compilers Abstract Assembly Instruction selection mov e1 , e2 jmp e cmp e1 , e2 [jne je jgt ] l push e1 call e](/thumbs/25/6532540.jpg "Where we are CS 4120 Introduction to Compilers Abstract Assembly Instruction selection mov e1 , e2 jmp e cmp e1 , e2 [jne je jgt ] l push e1 call e")
0/5/03 Where we are CS 0 Introduction to Compilers Ross Tate Cornell University Lecture 8: Instruction Selection Intermediate code synta-directed translation reordering with traces Canonical intermediate
Computer Architecture Lecture 2: Instruction Set Principles (Appendix A) Chih Wei Liu 劉 志 尉 National Chiao Tung University cwliu@twins.ee.nctu.edu.
Computer Architecture Lecture 2: Instruction Set Principles (Appendix A) Chih Wei Liu 劉 志 尉 National Chiao Tung University cwliu@twins.ee.nctu.edu.tw Review Computers in mid 50 s Hardware was expensive
CSE 504: Compiler Design. Data Flow Analysis
Data Flow Analysis Pradipta De pradipta.de@sunykorea.ac.kr Current Topic Iterative Data Flow Analysis LiveOut sets Static Single Assignment (SSA) Form Data Flow Analysis Techniques to reason about runtime
PROBLEMS #20,R0,R1 #$3A,R2,R4
506 CHAPTER 8 PIPELINING (Corrisponde al cap. 11 - Introduzione al pipelining) PROBLEMS 8.1 Consider the following sequence of instructions Mul And #20,R0,R1 #3,R2,R3 #$3A,R2,R4 R0,R2,R5 In all instructions,
Parallel Computing. Benson Muite. benson.muite@ut.ee http://math.ut.ee/ benson. https://courses.cs.ut.ee/2014/paralleel/fall/main/homepage
Parallel Computing Benson Muite benson.muite@ut.ee http://math.ut.ee/ benson https://courses.cs.ut.ee/2014/paralleel/fall/main/homepage 3 November 2014 Hadoop, Review Hadoop Hadoop History Hadoop Framework
IA-64 Application Developer s Architecture Guide
IA-64 Application Developer s Architecture Guide The IA-64 architecture was designed to overcome the performance limitations of today s architectures and provide maximum headroom for the future. To achieve
! Solve problem to optimality. ! Solve problem in poly-time. ! Solve arbitrary instances of the problem. #-approximation algorithm.
Approximation Algorithms 11 Approximation Algorithms Q Suppose I need to solve an NP-hard problem What should I do? A Theory says you're unlikely to find a poly-time algorithm Must sacrifice one of three
Algorithm Design and Analysis
Algorithm Design and Analysis LECTURE 27 Approximation Algorithms Load Balancing Weighted Vertex Cover Reminder: Fill out SRTEs online Don t forget to click submit Sofya Raskhodnikova 12/6/2011 S. Raskhodnikova;
Spring 2011 Prof. Hyesoon Kim
Spring 2011 Prof. Hyesoon Kim Today, we will study typical patterns of parallel programming This is just one of the ways. Materials are based on a book by Timothy. Decompose Into tasks Original Problem
İSTANBUL AYDIN UNIVERSITY
İSTANBUL AYDIN UNIVERSITY FACULTY OF ENGİNEERİNG SOFTWARE ENGINEERING THE PROJECT OF THE INSTRUCTION SET COMPUTER ORGANIZATION GÖZDE ARAS B1205.090015 Instructor: Prof. Dr. HASAN HÜSEYİN BALIK DECEMBER
THE FLORIDA STATE UNIVERSITY COLLEGE OF ARTS AND SCIENCES APPLICATION CONFIGURABLE PROCESSORS CHRISTOPHER J. ZIMMER
THE FLORIDA STATE UNIVERSITY COLLEGE OF ARTS AND SCIENCES APPLICATION CONFIGURABLE PROCESSORS By CHRISTOPHER J. ZIMMER A Thesis submitted to the Department of Computer Science In partial fulfillment of
Outline. NP-completeness. When is a problem easy? When is a problem hard? Today. Euler Circuits
Outline NP-completeness Examples of Easy vs. Hard problems Euler circuit vs. Hamiltonian circuit Shortest Path vs. Longest Path 2-pairs sum vs. general Subset Sum Reducing one problem to another Clique
COMPUTER ORGANIZATION ARCHITECTURES FOR EMBEDDED COMPUTING
COMPUTER ORGANIZATION ARCHITECTURES FOR EMBEDDED COMPUTING 2013/2014 1 st Semester Sample Exam January 2014 Duration: 2h00 - No extra material allowed. This includes notes, scratch paper, calculator, etc.
Linux Process Scheduling Policy
Lecture Overview Introduction to Linux process scheduling Policy versus algorithm Linux overall process scheduling objectives Timesharing Dynamic priority Favor I/O-bound process Linux scheduling algorithm
NVIDIA Tools For Profiling And Monitoring. David Goodwin
NVIDIA Tools For Profiling And Monitoring David Goodwin Outline CUDA Profiling and Monitoring Libraries Tools Technologies Directions CScADS Summer 2012 Workshop on Performance Tools for Extreme Scale
FPGA area allocation for parallel C applications
1 FPGA area allocation for parallel C applications Vlad-Mihai Sima, Elena Moscu Panainte, Koen Bertels Computer Engineering Faculty of Electrical Engineering, Mathematics and Computer Science Delft University
on an system with an infinite number of processors. Calculate the speedup of
1. Amdahl s law Three enhancements with the following speedups are proposed for a new architecture: Speedup1 = 30 Speedup2 = 20 Speedup3 = 10 Only one enhancement is usable at a time. a) If enhancements
The Microarchitecture of Superscalar Processors
The Microarchitecture of Superscalar Processors James E. Smith Department of Electrical and Computer Engineering 1415 Johnson Drive Madison, WI 53706 ph: (608)-265-5737 fax:(608)-262-1267 email: jes@ece.wisc.edu
Making Dynamic Memory Allocation Static To Support WCET Analyses
Making Dynamic Memory Allocation Static To Support WCET Analyses Jörg Herter Jan Reineke Department of Computer Science Saarland University WCET Workshop, June 2009 Jörg Herter, Jan Reineke Making Dynamic
Lecture 10 Partial Redundancy Elimination
References Lecture 10 Partial Redundancy Elimination Global code motion optimization Remove partially redundant expressions Loop invariant code motion Can be extended to do Strength Reduction No loop analysis
Why have SSA? Birth Points (cont) Birth Points (a notion due to Tarjan)
Why have SSA? Building SSA Form SSA-form Each name is defined exactly once, thus Each use refers to exactly one name x 17-4 What s hard? Straight-line code is trivial Splits in the CFG are trivial x a
Lecture 11: Multi-Core and GPU. Multithreading. Integration of multiple processor cores on a single chip.
Lecture 11: Multi-Core and GPU Multi-core computers Multithreading GPUs General Purpose GPUs Zebo Peng, IDA, LiTH 1 Multi-Core System Integration of multiple processor cores on a single chip. To provide
Graph Analytics in Big Data. John Feo Pacific Northwest National Laboratory
Graph Analytics in Big Data John Feo Pacific Northwest National Laboratory 1 A changing World The breadth of problems requiring graph analytics is growing rapidly Large Network Systems Social Networks
Computer Organization and Architecture
Computer Organization and Architecture Chapter 11 Instruction Sets: Addressing Modes and Formats Instruction Set Design One goal of instruction set design is to minimize instruction length Another goal
Instruction Set Architecture. or How to talk to computers if you aren t in Star Trek
Instruction Set Architecture or How to talk to computers if you aren t in Star Trek The Instruction Set Architecture Application Compiler Instr. Set Proc. Operating System I/O system Instruction Set Architecture
A Systematic Approach to Model-Guided Empirical Search for Memory Hierarchy Optimization
A Systematic Approach to Model-Guided Empirical Search for Memory Hierarchy Optimization Chun Chen, Jacqueline Chame, Mary Hall, and Kristina Lerman University of Southern California/Information Sciences
Load Balancing. Load Balancing 1 / 24
Load Balancing Backtracking, branch & bound and alpha-beta pruning: how to assign work to idle processes without much communication? Additionally for alpha-beta pruning: implementing the young-brothers-wait
Course on Advanced Computer Architectures
Course on Advanced Computer Architectures Surname (Cognome) Name (Nome) POLIMI ID Number Signature (Firma) SOLUTION Politecnico di Milano, September 3rd, 2015 Prof. C. Silvano EX1A ( 2 points) EX1B ( 2
Obfuscation: know your enemy
Obfuscation: know your enemy Ninon EYROLLES neyrolles@quarkslab.com Serge GUELTON sguelton@quarkslab.com Prelude Prelude Plan 1 Introduction What is obfuscation? 2 Control flow obfuscation 3 Data flow
Advanced Computer Architecture-CS501. Computer Systems Design and Architecture 2.1, 2.2, 3.2
Lecture Handout Computer Architecture Lecture No. 2 Reading Material Vincent P. Heuring&Harry F. Jordan Chapter 2,Chapter3 Computer Systems Design and Architecture 2.1, 2.2, 3.2 Summary 1) A taxonomy of
OpenCL Optimization. San Jose 10/2/2009 Peng Wang, NVIDIA
OpenCL Optimization San Jose 10/2/2009 Peng Wang, NVIDIA Outline Overview The CUDA architecture Memory optimization Execution configuration optimization Instruction optimization Summary Overall Optimization
Optimising Cloud Computing with SBSE
Optimising Cloud Computing with SBSE David R. White & Jeremy Singer {david.r.white, jeremy.singer}@glasgow.ac.uk University of Glasgow Monday 25 July 2011 OUTLINE VIRTUAL MACHINES OPPORTUNITIES FOR SBSE
A Comparison Of Shared Memory Parallel Programming Models. Jace A Mogill David Haglin
A Comparison Of Shared Memory Parallel Programming Models Jace A Mogill David Haglin 1 Parallel Programming Gap Not many innovations... Memory semantics unchanged for over 50 years 2010 Multi-Core x86
Static Program Transformations for Efficient Software Model Checking
Static Program Transformations for Efficient Software Model Checking Shobha Vasudevan Jacob Abraham The University of Texas at Austin Dependable Systems Large and complex systems Software faults are major
CPU Performance Equation
CPU Performance Equation C T I T ime for task = C T I =Average # Cycles per instruction =Time per cycle =Instructions per task Pipelining e.g. 3-5 pipeline steps (ARM, SA, R3000) Attempt to get C down
On some Potential Research Contributions to the Multi-Core Enterprise
On some Potential Research Contributions to the Multi-Core Enterprise Oded Maler CNRS - VERIMAG Grenoble, France February 2009 Background This presentation is based on observations made in the Athole project
Graph Database Proof of Concept Report
Objectivity, Inc. Graph Database Proof of Concept Report Managing The Internet of Things Table of Contents Executive Summary 3 Background 3 Proof of Concept 4 Dataset 4 Process 4 Query Catalog 4 Environment
FLIX: Fast Relief for Performance-Hungry Embedded Applications
FLIX: Fast Relief for Performance-Hungry Embedded Applications Tensilica Inc. February 25 25 Tensilica, Inc. 25 Tensilica, Inc. ii Contents FLIX: Fast Relief for Performance-Hungry Embedded Applications...
Very Large Instruction Word Architectures (VLIW Processors and Trace Scheduling)
Very Large Instruction Word Architectures (VLIW Processors and Trace Scheduling) Binu Mathew {mbinu} @ {cs.utah.edu} 1 What is a VLIW Processor? Recent high performance processors have depended on Instruction
The Use of Traces for Inlining in Java Programs
The Use of Traces for Inlining in Java Programs Borys J. Bradel and Tarek S. Abdelrahman Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto, Toronto, Ontario,
Multi-Threading Performance on Commodity Multi-Core Processors
Multi-Threading Performance on Commodity Multi-Core Processors Jie Chen and William Watson III Scientific Computing Group Jefferson Lab 12000 Jefferson Ave. Newport News, VA 23606 Organization Introduction
Approximation Algorithms
Approximation Algorithms or: How I Learned to Stop Worrying and Deal with NP-Completeness Ong Jit Sheng, Jonathan (A0073924B) March, 2012 Overview Key Results (I) General techniques: Greedy algorithms
Overview. CISC Developments. RISC Designs. CISC Designs. VAX: Addressing Modes. Digital VAX
Overview CISC Developments Over Twenty Years Classic CISC design: Digital VAX VAXÕs RISC successor: PRISM/Alpha IntelÕs ubiquitous 80x86 architecture Ð 8086 through the Pentium Pro (P6) RJS 2/3/97 Philosophy
GPU Computing with CUDA Lecture 4 - Optimizations. Christopher Cooper Boston University August, 2011 UTFSM, Valparaíso, Chile
GPU Computing with CUDA Lecture 4 - Optimizations Christopher Cooper Boston University August, 2011 UTFSM, Valparaíso, Chile 1 Outline of lecture Recap of Lecture 3 Control flow Coalescing Latency hiding
1. Memory technology & Hierarchy
1. Memory technology & Hierarchy RAM types Advances in Computer Architecture Andy D. Pimentel Memory wall Memory wall = divergence between CPU and RAM speed We can increase bandwidth by introducing concurrency
Chapter 11. 11.1 Load Balancing. Approximation Algorithms. Load Balancing. Load Balancing on 2 Machines. Load Balancing: Greedy Scheduling
Approximation Algorithms Chapter Approximation Algorithms Q. Suppose I need to solve an NP-hard problem. What should I do? A. Theory says you're unlikely to find a poly-time algorithm. Must sacrifice one
GameTime: A Toolkit for Timing Analysis of Software
GameTime: A Toolkit for Timing Analysis of Software Sanjit A. Seshia and Jonathan Kotker EECS Department, UC Berkeley {sseshia,jamhoot}@eecs.berkeley.edu Abstract. Timing analysis is a key step in the
Operating Systems. Virtual Memory
Operating Systems Virtual Memory Virtual Memory Topics. Memory Hierarchy. Why Virtual Memory. Virtual Memory Issues. Virtual Memory Solutions. Locality of Reference. Virtual Memory with Segmentation. Page
Real-time Process Network Sonar Beamformer
Real-time Process Network Sonar Gregory E. Allen Applied Research Laboratories gallen@arlut.utexas.edu Brian L. Evans Dept. Electrical and Computer Engineering bevans@ece.utexas.edu The University of Texas
! Solve problem to optimality. ! Solve problem in poly-time. ! Solve arbitrary instances of the problem. !-approximation algorithm.
Approximation Algorithms Chapter Approximation Algorithms Q Suppose I need to solve an NP-hard problem What should I do? A Theory says you're unlikely to find a poly-time algorithm Must sacrifice one of
Dynamic programming formulation
1.24 Lecture 14 Dynamic programming: Job scheduling Dynamic programming formulation To formulate a problem as a dynamic program: Sort by a criterion that will allow infeasible combinations to be eli minated
Q. Consider a dynamic instruction execution (an execution trace, in other words) that consists of repeats of code in this pattern:
Pipelining HW Q. Can a MIPS SW instruction executing in a simple 5-stage pipelined implementation have a data dependency hazard of any type resulting in a nop bubble? If so, show an example; if not, prove
Thread level parallelism
Thread level parallelism ILP is used in straight line code or loops Cache miss (off-chip cache and main memory) is unlikely to be hidden using ILP. Thread level parallelism is used instead. Thread: process
Week 1 out-of-class notes, discussions and sample problems
Week 1 out-of-class notes, discussions and sample problems Although we will primarily concentrate on RISC processors as found in some desktop/laptop computers, here we take a look at the varying types
Pipelining Review and Its Limitations
Pipelining Review and Its Limitations Yuri Baida yuri.baida@gmail.com yuriy.v.baida@intel.com October 16, 2010 Moscow Institute of Physics and Technology Agenda Review Instruction set architecture Basic
Introduction to Parallel Programming and MapReduce
Introduction to Parallel Programming and MapReduce Audience and Pre-Requisites This tutorial covers the basics of parallel programming and the MapReduce programming model. The pre-requisites are significant
IMCM: A Flexible Fine-Grained Adaptive Framework for Parallel Mobile Hybrid Cloud Applications
Open System Laboratory of University of Illinois at Urbana Champaign presents: Outline: IMCM: A Flexible Fine-Grained Adaptive Framework for Parallel Mobile Hybrid Cloud Applications A Fine-Grained Adaptive
Software Pipelining: An Effective Scheduling Technique for VLIW Machines
Software Pipelining: An Effective Scheduling Technique for VLIW Machines Monica Lam Department of Computer Science Carnegie Mellon University Pittsburgh, Pennsylvania 15213 Abstract This paper shows that
Putting Checkpoints to Work in Thread Level Speculative Execution
Putting Checkpoints to Work in Thread Level Speculative Execution Salman Khan E H U N I V E R S I T Y T O H F G R E D I N B U Doctor of Philosophy Institute of Computing Systems Architecture School of
Bindel, Spring 2010 Applications of Parallel Computers (CS 5220) Week 1: Wednesday, Jan 27
Logistics Week 1: Wednesday, Jan 27 Because of overcrowding, we will be changing to a new room on Monday (Snee 1120). Accounts on the class cluster (crocus.csuglab.cornell.edu) will be available next week.
CHAPTER 7: The CPU and Memory
CHAPTER 7: The CPU and Memory The Architecture of Computer Hardware, Systems Software & Networking: An Information Technology Approach 4th Edition, Irv Englander John Wiley and Sons 2010 PowerPoint slides