Instruction Scheduling. Software Pipelining - 2

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1 and Software Pipelining - 2 Department of Computer Science and Automation Indian Institute of Science Bangalore NPTEL Course on Principles of Compiler Design

2 Outline Simple Basic Block Scheduling Trace, Superblock and Hyperblock scheduling Software pipelining

3 Basic Block Scheduling Basic block consists of micro-operation sequences (MOS), which are indivisible Each MOS has several steps, each requiring resources Each step of an MOS requires one cycle for execution Precedence constraints and resource constraints must be satisfied by the scheduled program PC s relate to data dependences and execution delays RC s relate to limited availability of shared resources

execution Precedence constraints and resource constraints must be satisfied by the scheduled program

4 The Basic Block Scheduling Problem Basic block is modelled as a digraph, G = (V, E) R: number of resources Nodes (V ): MOS; Edges (E): Precedence Label on node v resource usage functions, ρ v(i) for each step of the MOS associated with v length l(v) of node v Label on edge e: Execution delay of the MOS, d(e) Problem: Find the shortest schedule σ : V N such that e = (u, v) E, σ(v) σ(u) d(e) and v V i, ρv (i σ(v)) R, where length of the schedule is max {σ(v)+l(v)} v V

with v length l(v) of node v Label on edge e: Execution delay of the MOS, d(e) Problem: Find the shortest schedule σ

5 - Precedence and Resource Constraints

6 A Simple List Scheduling Algorithm Find the shortest schedule σ : V N, such that precedence and resource constraints are satisfied. Holes are filled with NOPs. FUNCTION ListSchedule (V,E) BEGIN Ready = root nodes of V; Schedule = φ; WHILE Ready φ DO BEGIN v = highest priority node in Ready; Lb = SatisfyPrecedenceConstraints (v, Schedule, σ); σ(v) = SatisfyResourceConstraints (v, Schedule, σ, Lb); Schedule = Schedule + {v}; Ready = Ready {v} + {u NOT (u Schedule) AND (w, u) E, w Schedule}; END RETURN σ; END

FUNCTION ListSchedule (V,E) BEGIN Ready = root nodes of V; Schedule = φ; WHILE Ready φ DO BEGIN v = highest priority node in

7 List Scheduling - Ready Queue Update

8 Constraint Satisfaction Functions FUNCTION SatisfyPrecedenceConstraint(v, Sched, σ) BEGIN RETURN ( max σ(u)+d(u, v)) u Sched END FUNCTION SatisfyResourceConstraint(v, Sched, σ, Lb) BEGIN FOR i := Lb TO DO u Sched IF 0 j < l(v), ρ v (j)+ ρu (i + j σ(u)) R THEN RETURN (i); END

σ(u)+d(u, v)) u Sched END FUNCTION SatisfyResourceConstraint(v,

9 Precedence Constraint Satisfaction

10 Resource Constraint Satisfaction

11 List Scheduling - Priority Ordering for Nodes 1 Height of the node in the DAG (i.e., longest path from the node to a terminal node 2 Estart, and Lstart, the earliest and latest start times Violating Estart and Lstart may result in pipeline stalls Estart(v) = max i=1,,k (Estart(u i)+d(u i, v)) where u 1, u 2,, u k are predecessors of v. Estart value of the source node is 0. Lstart(u) = min i=1,,k (Lstart(v i) d(u, v i )) where v 1, v 2,, v k are successors of u. Lstart value of the sink node is set as its Estart value. Estart and Lstart values can be computed using a top-down and a bottom-up pass, respectively, either statically (before scheduling begins), or dynamically during scheduling

12 Estart Computation

13 Lstart Computation

14 List Scheduling - Slack 1 A node with a lower Estart (or Lstart) value has a higher priority 2 Slack = Lstart Estart Nodes with lower slack are given higher priority Instructions on the critical path may have a slack value of zero and hence get priority

Nodes with lower slack are given higher priority Instructions

15 Simple List Scheduling - Example - 1 INSTRUCTION SCHEDULING - EXAMPLE LEGEND 1 path length node no. exec time latency path length (n) = exec time (n), if n is a leaf = max { latency (n,m) + path length (m) } m ε succ (n) Schedule = {3, 1, 2, 4, 6, 5}

exec time 3 2 1 5 3 1 0 2 latency 3 4 1 2 0 path length (n) = exec time

16 Simple List Scheduling - Example - 2 latencies add,sub,store: 1 cycle; load: 2 cycles; mult: 3 cycles µ ¹¾µ path length and slack are shown on the left side and right side of the pair of numbers in parentheses ½ Ø½ ÐÓ ¾ Ø¾ ÐÓ Ø Ø½ µà ¹Ä Ú Ð Ó 8(0, 0)0 7(0, 1)1 i1 ld i2 ld Ø Ø½¹¾ Ø Ø¾ 3(2, 5)3 6(2, 2)0 1(2, 7)5 Ø Ø Ø¾ i3 add sub i4 i5 add Ø Ø Ø µ ¹ Ö Ó ØØ 5(3, 3)0 ØØ mult i6 i9 st 0(8, 8)0 µ Û Ø Ø ÖØ Ä Ø ÖØµÎ ÐÙ 2(6, 6)0 i7 add i8 st 1(7, 7)0

Ø¾ ÐÓ Ø Ø½ µà ¹Ä Ú Ð Ó 8(0, 0)0 7(0, 1)1 i1 ld i2 ld Ø Ø½¹¾ Ø Ø¾ 3(2, 5)3 6(2, 2)0 1(2, 7)5 Ø Ø Ø¾ i3 add sub

17 Simple List Scheduling - Example - 2 (contd.) latencies add,sub,store: 1 cycle; load: 2 cycles; mult: 3 cycles 2 Integer units and 1 Multiplication unit, all capable of load and store as well Heuristic used: height of the node or slack int1 int2 mult Cycle # Instr.No. Instruction i1, i2 t 1 load a, t 2 load b i4, i3 t 4 t 1 2, t 3 t i6, i5 t 5 t 2 + 3, t 6 t 4 t i5 not sched. in cycle due to shortage of int units i7 t 7 t 3 + t i8 c st t i9 b st t 5

store as well Heuristic used: height of the node or slack int1 int2 mult Cycle # Instr.No.

18 Resource Usage Models - Instruction Reservation Table r 0 r 1 r 2 r 3 r 4 t t t t No. of resources in the machine: 4

19 Resource Usage Models - Global Reservation Table r 0 r 1 r 2 r M t t t t T M: No. of resources in the machine T: Length of the schedule

20 Resource Usage Models - Global Reservation Table GRT is constructed as the schedule is built (cycle by cycle) All entries of GRT are initialized to 0 GRT maintains the state of all the resources in the machine GRTs can answer questions of the type: can an instruction of class I be scheduled in the current cycle (say t k )? Answer is obtained by ANDing RT of I with the GRT starting from row t k If the resulting table contains only 0 s, then YES, otherwise NO The GRT is updated after scheduling the instruction with a similar OR operation

of class I be scheduled in the current cycle (say t k )?

21 Simple List Scheduling - Disadvantages Checking resource constraints is inefficient here because it involves repeated ANDing and ORing of bit matrices for many instructions in each scheduling step Space overhead may become considerable, but still manageable

22 Global Acyclic Scheduling Average size of a basic block is quite small (5 to 20 instructions) Effectiveness of instruction scheduling is limited This is a serious concern in architectures supporting greater ILP VLIW architectures with several function units superscalar architectures (multiple instruction issue) Global scheduling is for a set of basic blocks Overlaps execution of successive basic blocks Trace scheduling, Superblock scheduling, Hyperblock scheduling, Software pipelining, etc.

23 Trace Scheduling A Trace is a frequently executed acyclic sequence of basic blocks in a CFG (part of a path) Identifying a trace Identify the most frequently executed basic block Extend the trace starting from this block, forward and backward, along most frequently executed edges Apply list scheduling on the trace (including the branch instructions) Execution time for the trace may reduce, but execution time for the other paths may increase However, overall performance will improve

24 Trace Example ß ¼µ ÓÖ ¼ ½¼¼ µ Ð Ð µà ¹Ä Ú Ð Ó ÙÑ ÙÑ ±±Ö½ ¼ ½ ½ Ö¾ ±±Ö ¼ ±±Ö ¼¼ ¾ Ö ¾ Ö¾ ¼µ ÓØÓ ±±Ö Ö ÐÓ Ö½µ ÐÓ Ö½µ Ö Ö½µ Ö ÓØÓ Ö Ö Ö ½¼ Ö½ ½½ Ö½ Ö µ ÓØÓ ½ Ö½µ Ö¾ Ö Ö µ Ñ ÐÝ Ó Ö½ B1 B2 B3 µ ÓÒØÖÓÐ ÐÓÛ Ö Ô B4 main trace

25 Trace - Basic Block Schedule Ì Ñ 2-way issue architecture with 2 integer units ¼add, sub, store: 1 cycle, load: 2 cycles, goto: no stall ½¾ ½ ÁÒØºÍÒ Ø½ ÐÓ Ö½µ ÁÒØºÍÒ Ø¾ 9 cycles for the main trace and 6 cycles for the off-trace ¾ Ö¾ ¼µ ÓØÓ Ö Ö½µ Ö ÐÓ Ö½µ Ö Ö µ Ö Ö¾ ÓØÓ µ ½½ Ö½ Ö µ ÓØÓ ½ Ö Ö Ö ½¼ Ö½ Ö½µ Ö¾ Ö½

26 Trace Schedule

27 Trace Schedule Ì Ñ ¼½¾ ½ ÁÒØºÍÒ Ø½ ÐÓ Ö½µ Ö ÁÒØºÍÒ Ø¾ ÐÓ Ö½µ 6 cycles for the main trace and 7 cycles for the off-trace µ µ ½½ Ö½ Ö µ ÓØÓ ½ ¾ Ö½µ Ö Ö Ö¾ ¼µ ÓØÓ Ö Ö ½¼ Ö½ Ö Ö Ö Ö Ö¾ Ö½µ Ö¾ Ö½ ½¾ ÓØÓ

28 Trace Scheduling - Issues Side exits and side entrances are ignored during scheduling of a trace Required compensation code is inserted during book-keeping (after scheduling the trace) Speculative code motion - load instruction moved ahead of conditional branch Example: Register r3 should not be live in block B3 (off-trace path) May cause unwanted exceptions Requires additional hardware support!

29 Compensation Code - Side Exit

30 Compensation Code - Side Exit

31 Compensation Code - Side Entry

32 Compensation Code - Side Entry

Software Pipelining. Y.N. Srikant. NPTEL Course on Compiler Design. Department of Computer Science Indian Institute of Science Bangalore 560 012

Software Pipelining. Y.N. Srikant. NPTEL Course on Compiler Design. Department of Computer Science Indian Institute of Science Bangalore 560 012 Department of Computer Science Indian Institute of Science Bangalore 560 2 NPTEL Course on Compiler Design Introduction to Overlaps execution of instructions from multiple iterations of a loop Executes