ECE2049: Embedded Computing in Engineering Design A Term Fall Lecture #6: Memory Organization and Digital I/O using the MSP430F5529

Transcription

1 ECE2049: Embedded Computing in Engineering Design A Term Fall 2016 Lecture #6: Memory Organization and Digital I/O using the MSP430F5529 Reading for Today: Davies , MSP430x5xx User Guide Ch 12 Reading for Next Class: Davies , MSP430x5xx User Guide Ch 12 Homework #2 (on Web): Due Friday 9/9/16 Lab #0 (on web): Report (1 per team) due Tues (9/6) in class Be sure to attach Sign off sheet (Don't print out code) Lab #1 (on web): Pre lab sign off in Lab this week! Last class: Specifics of the MSP430F5529 architecture MSP430F5529 is Little Endian, has Von Neumann architecture This class: Memory organization and digital I/O >> MSP430 family uses Von Neumann architecture >> MSP 430 family contains over 100 versions of this CPU with various memory/ peripheral configurations -- Really a System on a Chip

2 >> We'll be using MSP430F KB Flash memory > Code storage -- 8 KB RAM (+2 KB RAM associated with USB) > Data storage -- LCD controller bit Hardware multiplier, Serial interfaces (UART), analog to-digital converter (ADC) and a slew of other peripherals -- Multiple timers, comparator, USB controller, DMA, general IO ports... Memory Organization >> Memory = group of sequential locations where binary data is stored -- In MSP430, each memory location holds 1 byte -- Each byte has unique address which CPU uses to read to and write from that location (think mailbox ) -- Multibyte data is stored Little Endian! (low byte, high byte) >> 2 types of memory: Volatile and Non-volatile Volatile = Loses contents when power removed or interrupted Non-Volatile =Keeps contents when power removed or interrupted

3 RAM = 8 KB (+2 KB) = DATA memory = Volatile >> Read and Write = retrieving or writing DATA to/from RAM (under programmer control) (MSP430F5529 has a RAM retention low power mode) FLASH = 128 KB = CODE memory (primarily!) = Non-volatile >> Fetch = retrieving of instruction from CODE (Flash) memory (automatic CPU function) >> Flash is writable under program control -- time required to write >> time required to read -- Must be erased in multi-byte segments (e.g 512 bytes) MSP430 is 16 bit microcontroller >> 16 bit word size => 16 bit internal registers >> 16 bit data bus BUT MSP430x5xxx and '6xxx families have and extended 20 bit memory address bus to allow access to up to 1MB of memory >> Now a word about how memory sizes are (mis?) labeled... By JEDEC standard 1 KB = 2 10 bytes = 1024 bytes

4 IEC standard calls 2 10 bytes = 1024 bytes = 1 kilobinary = 1 KiB = 1 kibibyte >> RAM starts at 02400h, implemented in 2KB banks (sectors) -- Variables used during program execution are stored in RAM >> Our 128 KB of Flash starts at 04400h and ends at 0FFFFh. (Interrupt Vector Table is written within Flash) >> Code is written to Flash when you program the chip from CCS starting at address 04400h (by default, can give compiler directives specify other location) Internal Registers Additionally, inside the CPU, there are sixteen 16-bit register >> Registers R0 R3 have dedicated functions >> Registers R4 R15 are user registers -- Like scratch pad for data values being used by current or recent instructions -- Retrieving an operand from a CPU register is much more efficient than reading it in from memory -- CCS compiler tries to maximize register use >> Whats the deal with the addresses below 00FFFh assigned to peripherals? They are what you use to do IO!!

5 MSP430F5529 Basic Digital I/O Lowest level of input/output Inputting or outputting logic levels to the pins of the MSP430 package >> Eight independent, individually configurable digital I/O ports >> Ports 1 7 are each 8 bits wide, Port 8 is 3 bits wide >> Each pin of each port can be configured individually as input or output >> Each pin of each port can be individually read from or written to >> Sequential ports can be logically combined to create 16 bit port For example, Port 1 & 2 together are Port A >> Ports 1 and 2 can generate interrupts which are control signals that can be accepted or ignored by the '430 We'll be using interrupts later in the term >> Each port is controlled by six byte addressable (i.e. 1 byte wide) registers >> All the I/O port registers are memory mapped meaning each register associated with an IO port or other peripheral device has a unique address > and in CCS a predefined name (see msp430f5529.cmd and msp430f5529.h) How do you know what the addresses are? The 6 registers controlling the Digital I/O ports are Function Select Register:

6 Direction Register: Input Register: Output Register: Drive Strength Pull up/down Resistor Enable >> Using the digital I/O ports is conceptually simple... >> Make extensive use of C's Bitwise operations & ~ ^ (and &= = ~=) > Recall Truth Tables for AND (&), OR ( ), NOT (~) and exclusive OR = XOR (^) X Y Z=X & Y X Y W=X Y X C = ~X X Y V=X ^ Y

7 Ex: Using CCS C configure Port 3 for digital I/O with Pins 1 and 0 as inputs and Pins 7 thru 4 and outputs.