Quo Vadis Embedded OS? V

Transcription

1 Quo Vadis Embedded? V

2 Introduction Motivation ECUs gain more and more functionality due to increasing computing power of automotive microcontrollers and new vehicle features. 2

3 Introduction Operating Systems Characteristics General Purpose RT for embedded systems RT for deep embedded systems Soft Real-Time Hard Real Time Hard Real Time Bad Jitter behaviour Good interrupt latency Very good interrupt latency Bad interrupt latency Good jitter behavior Very good Jitter behavior Large Footprint Small/Medium Footprint Very small footprint Dynamic executable handling Dynamic executable handling Statically configured PIX compliance PIX compliance AUTAR / EK Broad support for Peripherals Slow startup time Large Communities Libraries Apps Programming languages Support for peripherals is vendor specific Fast startup time Typically microkernel approach Some Microkernels compliant to ISO26262 Support for peripherals is vendor specific Very Fast startup time Monolithic Compliance to Automotive SPICE ISO

4 Introduction Drivers for increasing functionality of ECUs Infotainment Image Processing / Sensor Fusion Hardware 2D/3D accel. support ADAS: Camera/Radar/LIDAR Video Codecs, Streaming support, multi-media library, etc Image processing and machine learning Connectivity Vision: Dynamic Software Platform Increasing Performance Multicore GPUs, Car-2-X (LTE, WiFi, GPS, etc.) Multimedia (USB, SD-Card, NFC, etc.) App-Store for automotive applications Currently not in the direct focus 4

5 Introduction Use Cases Process 1 (nat. PIX) IPC MCU MEM GP/Embedded RT Process 2(MSR) IPC High Level functionality + ASR Classic connectivity Process 1 (ADAPTIVE) MCU Middleware PIX Process 2 (ADAPTIVE) AUTAR Adaptive MCU 1 (GP) IPC ECU SPI/ETH MCU 2 (MSR) IPC Multiprocessor Core 1 (GP) MCU Core 1 or 2 (MSR) Core 1 (MSR 1) MCU Core 2 (MSR 2) IPC MEM IPC IPC MEM IPC Full Hypervisor Lean Hypervisor High Level functionality + ASR Classic connectivity Consolidation 5

6 Agenda Introduction How to integrate high level functionality? And what about deep embedded systems? Summary 6

7 How to integrate high level functionality? AUTAR Adaptive Targets Highly automated driving Car2-X Connectivity Vehicle in the cloud PIX as basic runtime environment Planned Dynamics The whole system needs to be 1. Fail-Safe 2. Fail-Operational 3. Secure 7

8 How to integrate high level functionality? PIX only systems High Level functionality already implemented on PIX Image processing algorithms 2D/3D visualization Machine learning AUTAR BSW elements can be executed on top of PIX to fill this gap. MSR Guest PIX Process AUTAR Wrapper SYS DIAG AMD XCP Application MICRAR RTE MEM CAN LIN COM FR ETH V2G 1 IO AVB 1 LIBS Other BSW components PIX PIX MCALs MCAL EXT Microcontroller 8

9 How to integrate high level functionality? PIX only systems Tight Timing constrainings may not be met in this setup HW Fault metrics are typically an issue HW too complex Higher ASIL levels may not be reachable PIX Process AUTAR Wrapper SYS DIAG AMD XCP Application MICRAR RTE MEM CAN LIN COM FR ETH V2G 1 LIBS AVB 1 IO Can also be realized by Multiprocessor setup Hypervisor setup PIX PIX MCALs MCAL EXT Microcontroller 9

10 How to integrate high level functionality? Using a hypervisor to add high level functionality in a safety environment PIX Guest ASR Guest Suitable for mixed criticality Process Process Process Process SWC SWC Current HW architectures typically offer a separate safety core PIX ASR High Level functionality can still run on the high performance cores Hypervisor Safety relevant functionality is isolated on separate safety core ASIL decomposition CPU Hardware IO CPU Safe CPU Safe IO Another alternative is redundancy Direct Access Virtualized Access IPC over Hypervisor 10

11 Agenda Introduction How to integrate high level functionality? And what about deep embedded systems? Summary 11

12 And what about deep embedded systems? And what about deep embedded systems? There is still the need for deep embedded systems Cost as a driver Amdahl s Law Parallelity Automotive MCUs have more and more cores Next generation has up to 6 cores Restriction of parallelizability Communication Shared Resources Synchronization Speedup Parallelizability is the key Nr. of processors 12

13 And what about deep embedded systems? Consolidation the AUTAR way AUTAR supports multicore functionality ASR SWC SWC SWC SWC SWC SWC SWCs can be distributed among cores RTE According to Amdahls Law parallelizability is the key to success BSW If parallelizability is not possible multicore systems can become slower than single core systems Alternative use case for multicore systems? CPU IO CPU IO CPU IO Hardware 13

14 And what about deep embedded systems? System partitioning Multicore systems can also be used for consolidation ASR Guest A ASR Guest B SWC SWC SWC SWC SWC SWC Mixed criticality possible SW/HW supports up to ASIL-D ASR ASR 1:n mapping of Guests to Cores Lean Hypervisor Otherwise hierarchical scheduling becomes a topic VIO Elimination of shared resource usage where possible Virtualization of shared resources where necessary CPU IO CPU IO CPU IO Hardware Direct Access Virtualized Access Shared IO IPC over Hypervisor 14

15 And what about deep embedded systems? System partitioning ASR Guest A ASR Guest B Small hypervisor footprint No or low virtualization overhead SWC SWC SWC SWC SWC SWC Each partition can be configured separately Easy integration ASR Lean Hypervisor ASR VIO Hypervisor may provide inter partition communication interface CPU IO CPU IO CPU IO Shared IO Hardware Direct Access Virtualized Access IPC over Hypervisor 15

16 Agenda Introduction How to integrate high level functionality? And what about deep embedded systems? Summary 16

17 Summary Summary There are different approaches to integrate high level functionality in embedded systems AUTAR Adaptive is on its way Until that PIX Only systems with hosted ASR components Hypervisor setups Redundancy Automotive MCUs gain more and more cores (many core systems) Lean hypervisor setups that focus in separation only PIX Guest ASR Guest ASR Guest A ASR Guest B Process Process Process Process SWC SWC SWC SWC SWC SWC SWC SWC PIX ASR ASR ASR Hypervisor Lean Hypervisor VIO CPU Hardware IO Direct Access Virtualized Access CPU Safe Safe CPU IO IPC over Hypervisor CPU IO CPU IO CPU IO Hardware Direct Access Virtualized Access Shar ed IO IPC over Hypervisor 17

18 For more information about Vector and our products please visit Author: Dr. Timo Kerstan Vector Germany Vector Informatik GmbH. All rights reserved. Any distribution or copying is subject to prior written approval by Vector. V