Tilera s Many-core Processor

Transcription

1 Tilera s Many-core Processor A scalable architecture on a single chip. J. Whitesell & S. Ladavich Tuesday, May 14 th,

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3 History of Tilera 3

4 History of Tilera Pros and Cons of Building a Manycore Architecture 4

5 History of Tilera Pros and Cons of Building a Manycore Architecture The Tilera Approach 5

6 History of Tilera Pros and Cons of Building a Manycore Architecture The Tilera Approach Tilera s 6

7 History of Tilera Pros and Cons of Building a Manycore Architecture The Tilera Approach Tilera s Tile Architecture 7

8 History of Tilera Pros and Cons of Building a Manycore Architecture The Tilera Approach Tilera s Tile Architecture imesh Network Topology 8

9 History of Tilera Pros and Cons of Building a Manycore Architecture The Tilera Approach Applications Tilera s Tile Architecture imesh Network Topology 9

10 History of Tilera Pros and Cons of Building a Manycore Architecture The Tilera Approach Applications Server Tilera s Tile Architecture imesh Network Topology 10

11 History of Tilera Pros and Cons of Building a Manycore Architecture The Tilera Approach Applications Server Media Tilera s Tile Architecture imesh Network Topology 11

12 History of Tilera Pros and Cons of Building a Manycore Architecture The Tilera Approach Applications Server Media Cloud Tilera s Tile Architecture imesh Network Topology 12

13 History of Tilera Pros and Cons of Building a Manycore Architecture The Tilera Approach Applications Server Media Cloud Tilera s Tile Architecture imesh Network Topology Performance Analysis and Benchmarking 13

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15 Multi-processor made of single chips MIT s Dr. Anant Agarwal leads the way for Tiled Manycore

16 Multi-processor made of single chips node meshmesh based cache-coherent processor 2002 MIT s RAW architecture

17 Multi-processor made of single chips node meshmesh based cache-coherent processor MIT s RAW architecture DARPA pays the bill! Gives 10s of millions supporting RAW

18 Tilera has solved the multi-processor scalability problem! does not exist! Multi-processor made of single chips DARPA pays the bill! Gives 10s of millions supporting RAW node meshmesh based cache-coherent processor 2004 Tilera s stealth launch

19 Tilera has solved the multi-processor scalability problem! does not exist! Multi-processor made of single chips DARPA pays the bill! Gives 10s of millions supporting RAW node meshmesh based cache-coherent processor 2004 Tilera s stealth launch Tilera s corporate launch

20 Multi-processor made of single chips DARPA pays the bill! Gives 10s of millions supporting RAW node meshmesh based cache-coherent processor Tilera s stealth launch Tilera s corporate launch Latest line Gx series is released 20

21 Traditional Architectures aren t Scalable Most Multi-Core Chips Stop Around 8 Cores Bus Interconnect Creates a Bottleneck for MM Access Consumes Chip-Area & Power 21

22 On-Chip Memory Limits Software Support Efficient API Development is Challenging Parallel Languages and Programmers are Needed 22

23 On-Chip Communication is Fast! Reduced Overheads Finer Grain Size On-Chip Network Footprint is Small! Natural Tiled Connections 2-D Mesh Suits 2-D Substrate 23

24 Create a Basic Modular Unit Homogeneous Across Chip Known as a Tile Full-Featured Processor Core Processor Engine Cache Engine Switch Engine Capable of Running an OS Basic Look Inside a Tile 24

25 Processor Engine 64-bit VLIW Architecture 3 Execution Pipelines ALU, Flow Control, LD/ST Cache Engine Dynamic Distributed Cache Shared L2 Caches (L3) Switch Engine Direct Neighbor Connections I/O Connections on Periphery Detailed Look Inside a Tile 25

26 Networks are easy! 26

27 Networks are easy! Communication is cheap! 27

28 Leverage Multiple Independent Networks 28

29 1) How many networks are needed? 29

30 1) How many networks are needed? 2) What functionalities do the networks have? 30

31 How are the message types and communications defined? Message Types: Dedicated Networks: 31

32 How are the message types and communications defined? Message Types: Implicit Message Passing Explicit Message Passing Dedicated Networks: 32

33 How are the message types and communications defined? Message Types: 1 1)Implicit Implicit Message Passing Explicit Message Passing 1)MDN 2)TDN Dedicated Networks: 33

34 How are the message types and communications defined? Message Types: 1 1)Implicit Implicit Message Implicit Passing Messages Explicit through Message Passing Tile-to-tile shared address space Non-uniform / distributed cache access (NUCA) Dedicated Networks: Shared address space in off-chip / main memory Uniform memory access (UMA) 1)MDN 2)TDN 34

35 How are the message types and communications defined? Message Types: 1 1)Implicit Implicit Message Passing Explicit Message Passing Streaming Data Messages 1)MDN 2)TDN Dedicated Networks: 35

36 How are the message types and communications defined? Message Types: 1)Implicit 2)Message Passing 1 Implicit Message Passing Explicit Message Passing 2 Streaming Data Messages 1)MDN 2)TDN 3)UDN Dedicated Networks: 36

37 How are the message types and communications defined? Message Types: 1)Implicit 2)Message Passing 1 Implicit Message Passing Explicit Message Passing 2 Streaming Data Messages 1)MDN 2)TDN 3)UDN Dedicated Networks: Large Buffers Small Buffers 37

38 How are the message types and communications defined? Message Types: 1)Implicit 2)Message Passing 3)Streaming Data a) Small stream 1 Implicit Message Passing Streaming Data Explicit Message Passing Messages 2 Dedicated Networks: Large Buffers Small Buffers 3a 1)MDN 2)TDN 3)UDN 38

39 How are the message types and communications defined? Message Types: 1)Implicit 2)Message Passing 3)Streaming Data a) Small stream b) Large stream 1 Implicit Message Passing Streaming Data Explicit Message Passing Messages 2 Dedicated Networks: 3b Large Buffers Small Buffers 3a 1)MDN 2)TDN 3)UDN 39

40 How are the message types and communications defined? Message Types: 1)Implicit 2)Message Passing 3)Streaming Data a) Small stream b) Large stream 1 Implicit Message Passing Streaming Data Explicit Message Passing Messages 2 Dedicated Networks: 3b Large Buffers Small Buffers 3a 1)MDN 2)TDN 3)UDN Special Case: High Performance Streaming 40

41 How are the message types and communications defined? Message Types: 1)Implicit 2)Message Passing 3)Streaming Data a) Small stream b) Large stream c) Large/Continuous 1)MDN 2)TDN 3)UDN 4)STN Dedicated Networks: 1 3b Implicit Message Passing Large Buffers 3c Streaming Data Special Case: High Performance Streaming Explicit Message Passing Small Buffers 3a Messages 2 41

42 How are the message types and communications defined? Message Types: 1)Implicit 2)Message Passing 3)Streaming Data a) Small stream b) Large stream c) Large/Continuous 1)MDN 2)TDN 3)UDN 4)STN Dedicated Networks: 1 3b Implicit Message Passing Large Buffers 3c Streaming Data Special Case: High Performance Streaming Explicit Message Passing Small Buffers 3a Messages 2 Special Case: IO Messages System Traffic 42

43 How are the message types and communications defined? Message Types: 1)Implicit 2)Message Passing 3)Streaming Data a) Small stream b) Large stream c) Large/Continuous 4)System Level & IO 1)MDN 2)TDN 3)UDN 4)STN 5)IDN Dedicated Networks: 1 3b Implicit Message Passing Large Buffers 3c Streaming Data Special Case: High Performance Streaming Explicit Message Passing Small Buffers 3a 4 Messages 2 Special Case: IO Messages System Traffic 43

44 How are the message types and communications defined? Message Types: 1)Implicit 2)Message Passing 3)Streaming Data a) Small stream b) Large stream c) Large/Continuous 4)System Level & IO 1)MDN 2)TDN 3)UDN 4)STN 5)IDN Dedicated Networks: 1 3b 5 Independent Hardware Networks: Implicit Message Passing Explicit Message Passing Memory Dynamic Network Tile Dynamic Network User Dynamic Network Streaming Static Network Data Messages I/O Dynamic Network Large Buffers 3c Special Case: High Performance Streaming Small Buffers 3a 4 2 Special Case: IO Messages System Traffic 44

45 How are the message types and communications defined? Message Types: 1)Implicit 2)Message Passing 3)Streaming Data a) Small stream b) Large stream c) Large/Continuous 4)System Level & IO 1)MDN 2)TDN 3)UDN 4)STN 5)IDN Dedicated Networks: 1 3b 5 Independent Hardware Networks: Implicit Message Passing Explicit Message Passing Memory Dynamic Network Tile Dynamic Network User Dynamic Network Streaming Static Network Data Messages I/O Dynamic Network Large Buffers Small Buffers Which minimize overheads for all desired forms of communication 3c Special Case: High Performance Streaming 3a 4 2 Special Case: IO Messages System Traffic 45

46 Parallel Processing in Embedded Domain Network Lossless Packet Capture Intrusion Detection & Prevention Multimedia Video Conferencing IP Surveillance Cloud In-Memory Caching Server Load Balancing 46

47 Numerous Evaluations Single-Core Performance CoreMark Score Parallelized Performance Information Fusion Gaussian Elimination MemCached Comparisons of SMPs & Many-Core 47

48 Evaluates Single-Core Performance 4 Algorithms 1 Final Score Single-Core Single Thread CoreMark Comparison Tilera s Processors Feature: VLIW Architecture 3 Pipelines 64-bit Instr. Words All or None Exec. CoreMark Score 48

49 Embedded Wireless Sensor Networks Cluster Heads Receive from 10 Sensors Head Node Performs Reduction Moving Average Filter 49

50 Results Vary Based on Application Integer-Based Arithmetic Floating-Point Intensive Information Fusion Application Gaussian Elimination Application 50

51 Why? Tiles Lack a Dedicated Floating-point Unit! Information Fusion Application Gaussian Elimination Application 51

52 Distributed Memory Caching System Creates a Virtual Memory Pool Used for Key-Value Stores Designed to Alleviate Database Load Currently Implemented by Social Media Giants Facebook, Twitter, and Zynga 52

53 For a Fixed Memory Footprint Tilera Achieves 3.35x Less Power Better Performance per Watt 53

54 The Tile Architecture Exhibits Superior Scalability Modular Design Low Cost of On-Chip Communication Exploiting a Variety of Task Grain Sizes ILP and TLP High Performance per Watt Relatively Low Clock Speeds Idle Mode for Unused Tiles Reducing Costs of Web Datacenters 54

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56 Waingold, E.; Taylor, M.; Srikrishna, D.; Sarkar, V.; Lee, W.; Lee, V.; Kim, J.; Frank, M.; Finch, P.; Barua, R.; Babb, J.; Amarasinghe, S.; Agarwal, A., "Baring it all to software: Raw machines," Computer, vol.30, no.9, pp.86,93, Sep 1997 CURRENTLY NOT NEEDED Tilera Corporation, Tile Processor User Architecture Manual, UG101, Nov [Rev. 2.4] Wentzlaff, D.; Griffin, P.; Hoffmann, H.; Liewei Bao; Edwards, B.; Ramey, C.; Mattina, M.; Chyi-Chang Miao; Brown, J.F.; Agarwal, A., "On-Chip Interconnection Architecture of the Tile Processor," Micro, IEEE, vol.27, no.5, pp.15,31, Sept.-Oct Munir, A.; Gordon-Ross, A.; Ranka, S., "Parallelized benchmark-driven performance evaluation of SMPs and tiled multi-core architectures for embedded systems," Performance Computing and Communications Conference (IPCCC), 2012 IEEE 31st International, vol., no., pp.416,423, 1-3 Dec Berezecki, M.; Frachtenberg, E.; Paleczny, M.; Steele, K., "Many-core key-value store," Green Computing Conference and Workshops (IGCC), 2011 International, vol., no., pp.1,8, July 2011 R. Schooler, The TILE-Gx Processor: Enabling HPC through Massive-Scale Manycore, IEEE High Performance EMbedded Computing Conference Proceedings, Presentation Slides Links to Other Images (Presentation Only): Tilera Silicon - AMD Phenom Silicon - Scalability Graph - Tilera Products and Theme - Single Tile Detail