ISP Target System Header Selection for AVR & AT89S FLASH Microcontrollers

Transcription

1 ISP Header Selection for AVR & AT8S FLASH s.0 verview This application note details the possible connection methods between a and when implementing in-system programming (ISP) of Atmel AVR and AT8S FLASH microcontrollers. The various ISP header types which can be designed onto a are discussed, along with the relative advantages and disadvantages of each connection method..0 Definitions. ISP ISP stands for In- Programming. This is the mechanism by which Atmel AVR and AT8S microcontrollers can be programmed in-situ, without physically removing them from the. This type of programming can usually be performed at the Vcc voltage, with no requirement for a higher Vpp voltage to be applied to the device during programming.. ISP This is a programmer which is capable of producing the required logic and power signals to in-system program (ISP) the. Equinox manufacture a range of programmers which are designed to ISP Atmel AVR and AT8S microcontrollers in development, production and field environments.. This is the Atmel AVR or AT8S microcontroller which is to be in-system programmed.. The is the physical Printed Circuit Board (PCB) which contains the microcontroller to be in-system programmed.. In order to in-system program (ISP) the on the, the programmer must interface to the correct pins of the target device. This User Figure - board + ISP connector + programmer is usually achieved by designing a suitable connector onto the which brings out all the signals required to implement ISP using an external ISP as shown in fig. Application Note 0 Title Version.0 Page No Section... verview Section... Definitions Section... Which? Section... ISP Selection Guide Section... ISP Pin Assignments for Equinox s Appendix...0 Connections for the Activ8r/Micro-ISP s Appendix... Connections for the FS000A Appendix... Connections for the Convertor Appendix... Connections for the Atmel -way Header

2 ISP Header Selection for AVR & AT8S FLASH s.0 Which? The choice of interconnection method between the and the ISP depends on many factors including the chosen ISP programmer, space requirements, extra ISP functionality required and the quantity/throughput of s to be programmed. There is also now a trend to allow field service personnel and even customers to remotely upgrade the product firmware in the field. The factors influencing the selection of the are detailed below:. ISP Choice Most Equinox programmers feature the Equinox 0-way ISP Header. It is possible to convert this header pinout to any other required header pinout by making a suitable conversion cable/pcb. The table below details the standard connectors supported by the Equinox range of ISP programmers. Micro-ISP Activ8r FS000A PR0x Equinox 0-way IDC Header ES ES ES (internally user selectable) ES (user selectable using separate PCB) Atmel 0-way IDC Header N Use Converter N Use Converter ES (user selectable) ES (user selectable using separate PCB) Atmel -way IDC Header N Requires user to make custom lead N Requires user to make custom lead N Requires user to make custom lead N Requires user to make custom lead. PCB Space Requirements If the is very small or densely populated with components, spare board area for an may be hard to come by. In these instances it is often better to choose the -way IDC header or to go for a single-in-line way header as these connectors require the least space. Figure - Selection Guide for Equinox s

3 ISP Header Selection for AVR & AT8S FLASH s. Signals required for the specific microcontroller being programmed Most Atmel AVR and AT8S microcontrollers require only six connections to implement basic ISP programming as follows: Vcc, GND, MSI, MIS, SCK and RESET. However, there are certain instances where more pins are required to implement extra functionality. The extra pins are SS(Slave Select), SCK (Serial Clock ), PRG_LED and a second GRUND connection. The function of these pins is detailed in section. PC PC Ground ISP Vcc RST MSI MIS SCK GND Ground Common earth point Figure - Typical Connections for ISP Programming.

4 ISP Header Selection for AVR & AT8S FLASH s. Quantity / throughput of s to be programmed in Production If the intended use of the system is for development only, the manual insertion of an ISP cable should not present much of a problem. However, in automated high throughput production environments any manual insertion operations need to be avoided as they slow down the production cycle. A so-called bed-of-nails test fixture is often used which connects the relevant points on the to the programmer when the PCB is inserted into the test fixture. Status LED's Connections PCB Adaptor Module Bed of Nails Test Fixture Solder Connection PCB Test Pin Figure - Bed-of-nails Test Fixture To the. Method of reprogramming the in the field Many s are programmed once at the factory and then are never subsequently reprogrammed by the customer in the field. However, some manufacturers are now designing systems which can be reprogrammed once they have left the factory. In order to implement this functionality, the must have the ISP Header in a place which can be easily located by the customer.

5 ISP Header Selection for AVR & AT8S FLASH s.0 ISP Selection Guide The relevant advantages and disadvantages of each header type are shown in fig.. It is also possible to implement a custom ISP connector by using an interface cable or PCB between the programmer and the header. ISP Connection type Equinox 0-way IDC Header Atmel 0-way IDC Header Atmel -way IDC Header -way SIL Header Bed-of-nails Advantages Extra serial clock signal available on SCK for clocking AVR devices LED control pin available (Micro-ISP only) Second GRUND pin may be used by the target system to sense presence of the programmer. IDC plug and socket are polarised to prevent incorrect insertion of the ISP cable Used on all Equinox target systems and in all Equinox application notes Widely used on the Atmel STK00, 00 and 00 systems IDC plug and socket are polarised to prevent incorrect insertion of the ISP cable Small physical PCB footprint Ideal for volume production where board space is a premium. Simple to add to existing PCB design Easier alignment of bed-of-nails test pins No PCB area taken up by a dedicated connector Ideal for automated test handlers Figure - ISP Connection Type - Advantage/Disadvantage Guide Disadvantages Larger PCB footprint than -way header. Not compatible with the Atmel STK00, 00, 00 systems. Larger PCB footprint than -way header. No extra lines for SCK or LED control. No extra lines available for SCK or LED control. -way non-reversible connector may be hard to source. No polarisation of ISP header/plug available ISP connector is not available if the product is to be reprogrammed in the field. ISP cable lengths are often longer. Board may require special design to bring out ISP connections.

6 ISP Header Selection for AVR & AT8S FLASH s. - Signal Definitions The is used to connect signal and power lines from the target microcontroller to the ISP. The definitions of each of the signals is shown in fig. below. The six required connections which must be made to implement ISP are listed at the top of the table. The optional signals are detailed in the next section. Header Pin Label Type pin description Connect ATmega0 Note PRG_VCC P Vcc connection Vcc Vcc MSI signal (SPI Data ut) MSI PD/RXD PRG_SCK PRG_SS PRG_SCK PRG_LED I P MIS signal (SPI Data In) RESET Control Line Ground connection Serial Clock Signal Slave Select Serial Clock signal Note LED control Line N X X MIS RESET Ground SCK External scillator input pin LED PD0/TXD RESET Ground SCK LED PTINAL REQUIRED KE: x I P This connection must be made ptional No Connect Input utput Passive Note : The ATmega 0(L) microcontroller requires that is connected RXD and is connected to TXD. This is different from the AT0S and AT8S devices. Note : Required on some ATtiny and ATmega devices Figure - Signal Definitions

7 ISP Header Selection for AVR & AT8S FLASH s. ptional ISP Signals The following signal lines are not absolutely necessary to implement ISP but should be taken into consideration at the PCB design stage. These signal lines may not be present on all Equinox programmers... SCK - scillator pin There are a few instances when the target microcontroller may require a clock source to be supplied from the programmer during programming as detailed in fig 7. FS000A Hand Held Atmel Header Equinox Header SCK 0V Vcc User This requirement can arise for the following reasons: i Slow programming with Internal RC scillator If the target device normally runs from an Internal RC scillator with a nominal frequency of MHz, the maximum SPI frequency is limited to approximately 00 khz. This results in the overall programming time being increased. Many Equinox programmers are capable of swapping the scillator Selection to an External Clock Source for programming and then swapping it back to Internal RC scillator when programming is complete. This can result in a much faster programming cycle. Please consult the relevant Atmel data sheet for the following devices which feature Internal RC scillators : ATmega(L), ATmega(L), ATtiny(L), ATtiny(L). ii Incorrect oscillator source has been selected If the CKSEL fuse bits are incorrectly set on certain AVR devices, it is possible for the device to stop operating as it has no clock source. The SCK signal may be used to temporarily clock the device to set it back to the correct oscillator source. Please consult the relevant Atmel data sheet for the following devices which may exhibit this problem: ATmega(L), ATmega(L), ATtiny(L), ATtiny(L), AT0(L)S, AT0(L)S. Figure 7 - FS000A providing SCK signal to clock target microcontroller 7

8 ISP Header Selection for AVR & AT8S FLASH s.. PRG_LED Many Equinox programmers feature the PRG_LED pin which is capable of driving an LED on the. The LED is automatically illuminated at the start of a programming operation and is switched off at the end of the operation. This output may also be used to signal other logic devices on the that programming has commenced. Vcc Figure 8- LED Circuit R LED PRG_LED.. Second GRUND connection The Equinox features two GRUND connections for enhanced EMC. It is possible to connect one of the GRUND pins to the GRUND and then use the second GRUND pin to detect that an ISP is plugged into the. This can be useful if there is other logic on the Board which needs to be automatically isolated during programming. See fig. R TARGET_Vcc Figure - Detection of programmer presence using spare ground pin. (7) Sense Logic () (PING) 8

9 ISP Header Selection for AVR & AT8S FLASH s.0 ISP Pin Assignments for Equinox s The table shown in fig. 0 details the pin assignments for all Equinox ISP programmers. The Micro-ISP, Activ8r and FS000A all feature the Equinox 0-way Header, but the FS000A does not have the PRG_SS or PRG_LED lines. Please refer to the relevant appendix for further information on each programmer. Type Pin Number Appendix Micro-ISP/Activ8r Equinox 0-way Header Appendix PRG_VCC PRG_SS PRG_SCK PRG_LED PRG_SCK Equinox 0-way Header Appendix PRG_VCC PRG_SCK PRG_SCK FS000A Atmel 0-way Header Appendix PRG_VCC PRG_SCK Atmel -way Header (All programmers) Appendix PRG_VCC PRG_SCK Figure 0 - ISP Pin Assignments for Equinox s

10 ISP Header Selection for AVR & AT8S FLASH s Appendix - Connections for Activ8r/Micro-ISP s Figure indicates the position of for both the ISP cable supplied and a 0-way IDC header situated on the target system. Equinox Top View Red stripe indicates Figure indicates the pinout required for target system IDC header when using either a Micro-ISP or Activ8r programmer. Figure PRG_SCK PRG_LED PRG_SS PRG_SCK Equinox Bottom View 0-way Header on User Figure Activ8r 0V Vcc User Figure Micro-ISP 0V Vcc User Figure 0

11 ISP Header Selection for AVR & AT8S FLASH s Appendix - Connections for the FS000A Figure indicates the position of for both the ISP cable supplied and a 0-way IDC header situated on the target system. Equinox Top View Red stripe indicates Figures & indicate the pinouts required for target system 0-way IDC header when using either an Equinox or Atmel 0-way Headers Figure Equinox Bottom View 0-way Header on User Figure PRG_SCK PRG_SCK PRG_SCK Atmel 0-way header Equinox 0-way header Figure FS000A Portable ISP Atmel Header Equinox Header 0V Vcc User Figure

12 ISP Header Selection for AVR & AT8S FLASH s Appendix - Connections for the Convertor Equinox Top View Equinox Bottom View Red stripe indicates 0-way Header on User Figure indicates the position of for both the ISP cable supplied and a 0-way IDC header situated the cable convertor. The pinout for the Equinox 0-way header on the ISP cable convertor is shown in figure. Figure shows the pinout used for the Atmel 0-way header on the user target system. Using this header will require the use of the Convertor indicated in figure. Figure Figure Micro-ISP Convertor 0V Vcc User PRG_SCK PRG_SCK PRG_SCK Equinox 0-way header Atmel 0-way header Figure Figure

13 ISP Header Selection for AVR & AT8S FLASH s Appendix - Connections for the Atmel -way Header Figure shows the pinout used for the Atmel -way header on the user target system. Using the Atmel -way header will require the use of a custom made 0-way to -way ISP cable (see figure ). Figure FS000A Portable ISP Equinox 0-way Header Atmel -way Header Custom 0-way to -way ISP cable 0V Vcc User Pin Mapping for the Equinox 0-way to the Atmel -way ISP Equinox ISP Pin Atmel ISP Pin Function Vcc No connection SS No connection SCK MSI No connection PRG MIS 7 and GND 8 SCK 0 RESET Figure PRG_SCK Figure Equinox 0-way Atmel -way Figure