Architecture bits. (Chromosome) (Evolved chromosome) Downloading. Downloading PLD. GA operation Architecture bits

Size: px
Start display at page:

Download "Architecture bits. (Chromosome) (Evolved chromosome) Downloading. Downloading PLD. GA operation Architecture bits"

Transcription

1 A Pattern Recognition System Using Evolvable Hardware Masaya Iwata 1 Isamu Kajitani 2 Hitoshi Yamada 2 Hitoshi Iba 1 Tetsuya Higuchi ,Umezono,Tsukuba,Ibaraki,305,Japan Electrotechnical Laboratory ,Tennoudai,Tsukuba,Ibaraki,305,Japan University of Tsukuba Abstract. We describe a high-speed pattern recognition system using Evolvable Hardware (EHW), which can change its own hardware structure by genetic learning in order to adapt best to the environment. The purpose of the system is to show that EHW can work as a recognition device with such robustness for the noise as seen in the recognition systems based on neural networks. The advantage of EHW compared with a neural network is the high processing speed and the readability of the learned result. The readability means that the result is understandable in terms of Boolean functions. In this paper, we describe the architecture, the learning algorithm and the experiment on the pattern recognition system using EHW. 1 Introduction The interests on evolvable hardware (EHW) are growing rapidly since the idea of EHW was proposed independently in Japan and in Switzerland around 1992 [Higuchi94],[Marchal94]. And in 1995, the rst international workshop on evolvable hardware was held in Lausanne. EHW is a hardware which can adapt to the new environment which the designer doesn't anticipate. This contrasts with the conventional hardware where the adaptive changes are not allowed. EHW, built on programmable logic devices (PLDs), is an adaptive hardware whose architecture can be recongured by using genetic algorithms to adapt to the new environment. EHW is best suitable for applications where hardware specications can not be given in advance. Applications solved by articial neural network (ANN) are such examples because pattern classier functions can be obtained only after learning is complete. The purpose of this paper is to show that EHW may have the possibility to take the place of ANN when used for a pattern recognition system. EHW is expected to work as ANN-like robust pattern recognizer which realizes noiseinsensitive recognition. Advantages of EHW over ANN are as follows. First the processing speed is at least two orders of magnitude faster than ANN systems whose executions are mostly software-based. Second the the learned results of

2 EHW are readable. That means that the learned result is easily expressed in terms of readable Boolean functions. In ANN, on the contrary, it is dicult to read the learned result because it is represented just by the enumeration of real values for thresholds and weights. This paper consists of the following sections. Section 2 describes the EHW concept. Section 3 describes the pattern recognition using EHW. It introduces MDL (Minimum description length) and VGA (Variable length chromosome genetic algorithm) for increasing the capability of noise-insensitive recognition. Section 4 describes an architecture of the pattern recognition system using EHW and the experiment on the recognition of numerical characters. Section 5 discusses about the recognition system and Section 6 concludes this paper. 2 Evolvable Hardware (EHW) 2.1 Basic Idea Evolvable Hardware (EHW) is a hardware which modies its own hardware structure according to the environmental changes. EHW is implemented on a programmable logic device (PLD), whose architecture can be altered by downloading a binary bit string, i.e. architecture bits. The architecture bits are adaptively acquired by genetic algorithms (GA). The basic idea of EHW is to regard the architecture bits of a PLD as a chromosome for GA (see Fig. 1). The hardware structure is adaptively searched by GA. These architecture bits, i.e. the GA chromosome, are downloaded onto a PLD, on and after the genetic learning. Therefore, EHW can be considered as an on-line adaptive hardware. Architecture bits GA operation Architecture bits (Chromosome) (Evolved chromosome) Downloading Downloading PLD Evolution PLD Fig. 1. Evolvable Hardware (EHW) 2.2 Programmable Logic Device (PLD) We explain in more detail about PLD using the simplied model as shown in Fig. 2.

3 A PLD consists of logic cells and a fuse. In addition, architecture bits determine the architecture of the PLD. These bits are assumed to be stored in an architecture bit register (ABR). Each link of the fuse corresponds to a bit in the ABR. The fuse determines the interconnection between the device inputs and the logic cell. It also species the logic cell's AND-term inputs. If a link on a particular row of the fuse is switched on, which is indicated by a black dot in Fig. 2, then the corresponding input signal is connected to the row. In the architecture bits, these black and white dots are represented by 1 and 0 respectively. Consider the example PLD shown in Fig. 2. The rst row indicates that I 0 and I 2 are connected by an AND-term, which generates I 0 I 2. Similarly, the second row generates I 1. These AND-terms are connected by an OR gate. Thus, the resultant output is O 0 = I 0 I 2 + I 1. As mentioned above, both of the fuse and the functionality of the logic cell are represented in a binary string. The key idea of EHW is to regard this binary bit string as a chromosome for the sake of GA-based adaptive search. The hardware structure we actually use is a FPLA device, which is a commercial PLD (Fig. 3). This architecture mainly consists of an AND and OR s. A vertical line of the OR corresponds to a logic cell in Fig. 2. Inputs I 0 I 1... IM-1 Inputs I 0 I 1 I 2 Fuse Logic cell..... Architecture Bit Register O 0 Output Fig. 2. A Simplied PLD (Programmable Logic Device) Structure AND Architecture bits O 0 OR.... Outputs O 1 O N-1 Fig. 3. A FPLA Architecture for EHW 2.3 Genetic learning We describe the genotype representation of EHW and the genetic learning method. In our earlier works, the architecture bits were regarded as the GA chromosome and the chromosome length was xed. In spite of this simple representation, the hardware evolution was successful for combinatorial logic circuits (e.g. 6-multiplexer [Higuchi93]) and sequential logic circuits (e.g. 4-state machine, 3-bit counter [Higuchi94]). However, this straightforward representation had a serious limitation in the hardware evolution. All the fuse bits should have been included in the

4 genotype, even when eective bits in the fuse were only a few. This made the chromosome too long to be eectively searched by evolution. Therefore, we have introduced a new GA based on variable length chromosome called VGA [Kajitani95]. VGA is expected to evolve a large circuit more quickly. The chromosome length of VGA is smaller than the previous GA, especially when evolving a circuit with large inputs. VGA is described in more detail in section 3. The tness evaluation of GA is basically determined by the correctness of the EHW's output for the training data set. In the pattern recognition system we introduce MDL (Minimum Description Length) [Rissanen89] for the tness evaluation. Using MDL, the ability of robustness in recognizing noisy pattern is expected to increase. (For more details, see section 3.3) 3 Pattern Recognition 3.1 Motivation EHW has been applied to high-speed pattern recognition in order to establish a robust system in noisy environments [Iwata96]. This ability, i.e. robustness, seems to be the main feature of ANN. ANN is mostly run in a software-based way, i.e. executed by a workstation. Thus, current ANN may have diculty with real-time processing because of the speed limit of the software-based execution. Another desirable feature of EHW is its readability. The learned result by EHW is expressed as a Boolean function, whereas ANN represents it as thresholds and weights. Thus, the acquired result of EHW is more easily understood than that of ANN. We believe that this understandable feature leads to wider usage of EHW in industrial applications. For the sake of achieving exible recognition capability, it is necessary to cope with a pattern which is classiable not by a linear function, but by a nonlinear function. We have conducted an experiment in learning the exclusive-or problem in order to check the above capability. From the simulation result, we conrmed that EHW can learn non-linear functions successfully [Higuchi95]. In other words, EHW is supposed to fulll the minimum requirement towards the robust pattern recognition. 3.2 Procedure of pattern recognition The pattern recognition procedure consists of two phases as shown in Fig. 4. The rst is the learning phase of training patterns. The training patterns are genetically learned by EHW. We use VGA and MDL-based tness described in section 3.3 and 3.4. The second phase is the recognition of test patterns. Our aim is the noise-insensitive pattern recognition.

5 1. Learning EHW Recognition 2 GA operation EHW 2 y x Fig. 4. The Procedure of Pattern Recognition using EHW Fig. 5. An Example of Pattern Classication using MDL 3.3 Fitness evaluation by MDL (Minimum Description Length) MDL (Minimum Description Length) is an information criteria in machine learning in order to predict the rest of the data set with the given data set [Rissanen89]. Using MDL for pattern recognition, a noise-insensitive classier function is obtained eectively. A classier function which is noise-insensitive is more desirable than a classi- er which is noise-sensitive, since the latter is susceptible to noise and overtting occurs. For example, in Fig. 5, the function denoted with solid line classies two patterns in very strict way, but the function denoted with dotted line is better as the classier function because it is noise-insensitive [Itoh92]. Thus, MDL is dened so as to choose more simple and more general classier functions. We have introduced the above MDL criterion into the GA tness evaluation. The purpose is to establish a robust learning method for EHW. In general, the greater the number of \don't care" 1 inputs, the more robust (i.e. noiseinsensitive) the evolved hardware. Thus, we regard the number of \don't care" inputs as an index of MDL. More formally, the MDL value for our EHW is written as follows: MDL = A c log(c +1)+(10 A c ) log(e +1); (1) where C denotes the complexity of the EHW. E is the error rate of the EHW's output. The C value (i.e. the complexity of the EHW) determines the performance of the MDL. We introduce three types of C denitions as described in Appendix. To use MDL as the tness function of GA, it must be normalized so that it has the range of 0 MDL 1. Thus the tness is expressed as follows. Fitness = 1 0 MDL (2) 1 We call an input "don't care" if it is not included in the output expression. For instance, if O = I1 + I2 in case of a PLD shown in Fig. 2, then I0 is a "don't care" input.

6 Chromosome: (0,1) (4,1) (8,2) (9,1) (13,1) (14,1) Chromosome: (0,1) (4,1) (8,2) (9,1) (13,1) (14,1) AND Allele: (Location, Connection Type) OR Connection Type 1 2 AND OR Architecture bits: AND Inputs I 0 I 1 I 2 OR (a) Representation of an Allele Outputs O O 0 1 (b) An Example of a Chromosome Fig. 6. Chromosome Representation of Variable Length Chromosome GA 3.4 Variable length chromosome GA (VGA) We introduce a new GA based on variable length chromosome called VGA to increase the performance of GA. In conventional EHW, the whole architecture bits of PLDs were regarded as a chromosome of GA. We call this method simple GA (called SGA). However, in pattern recognition problem of 2D image here, many inputs are needed. This causes the increase of chromosome length, leading to the increase of GA learning time, and the restriction to evolved circuit size. Comparing with SGA, the chromosome length of VGA is smaller especially when evolving a circuit with large inputs. This is because VGA can deal with a part of architecture bits, which eectively determine the hardware structure. Because of this short chromosome, VGA can increase the maximum circuit size and establish an ecient adaptive search. The coding method of VGA is described in Fig. 6. An example of a chromosome and representation of an allele is shown in Fig. 6 (a). An allele in a chromosome consists of a location and a connection type. The location is the position of the allele in the fuse. There are two kinds of connection type. The AND connection type denes the input of the AND tobeeitherpositive or negative. The OR connection type denes the output of the AND to be connected or not to the input of the OR. For example, an allele (0,1) means that the connection type at location 0 is 1. By converting each allele into the connection pattern of the PLD, the chromosome is converted into the the architecture bits dening the PLD as shown in Fig. 6 (b). We use the roulette wheel selection strategy. Recombination operators are cut and splice, which are used in the messy GA [Goldberg93]. The splice operator is slightly dierent in the sense that a gene with the same locations (for instance, (0,1) and (0,2) ) are not allowed in one chromosome. A mutation operator is applied so as to change the values of the location and the connection type randomly. Splice operator concatenates two chromosomes. For more details of VGA, refer to [Kajitani95].

7 4 Pattern recognition system 4.1 The pattern recognition system We have developed the pattern recognition system (Fig. 7). The organization of the system is shown in Fig. 8. It consists of an EHW board including 4 FPGA chips (Xilinx 4025), a DOS/V machine, and an input tablet for drawing patterns. The DOS/V machine handles GA operations, the control of EHW board and the display of patterns. The PLD on FPGA is recongurable, which means that the system can be used as a universal EHW system. The overview of the EHW board is shown in Fig. 9. and the block diagram is shown in Fig. 10. In the EHW board, there are four FPGA (hatched area in the gure), board control registers, and SRAM which stores the conguration data of FPGA. In the EHW, a circuit represented by a chromosome is realized by an ABR (architecture bit register) and a PLD. The ABR stores architecture bits of the PLD. The PLD has the architecture of FPLA device (Fig. 3). In this gure, there are K individuals, i.e. K pairs of an ABR and a PLD in a FPGA chip. In the rst version of this system, we designed a genetically recongurable hardware device with four FPGAs. The processing time of the EHW board is 720 ns. EHW board FPGA (Xilinx XC4025) x 4 I / F Input pattern Input tablet PC (DOS/V) Recognition result GA operation Fig. 7. Pattern Recognition System using EHW Fig. 8. Block Diagram of Pattern Recognition System Fig. 9. The EHW Board

8 Host Machine (DOS / V) ISA Board 16 EHW board 16 Selector. 8 Selector Selector Mem. Select SRAM 1 SRAM 4 FPGA Select FPGA Reset reset Download done ABR 1 ABR 1 Control PLD 1 PLD 1 Registers..... ABR K ABR K PLD K PLD K IPR IPR OPR OPR FPGA 1 FPGA 4 IPR: Input Pattern Register, OPR: Output Pattern Register Fig. 10. Block Diagram of EHW Board 4.2 Experiment We have conducted the experiment in recognizing binary patterns of 828 pixels. They are 30 input patterns of 64 bits in the training set as shown in Fig. 11. Three patterns exactly represent numerical characters (i.e. 0, 1, and 2). The other 27 patterns represent the same numerical characters with noises (i.e. 5 bits are randomly ipped). The outputs of EHW consists of 3 bits; each bit corresponds to one of three characters. The initial length of a chromosome is 100. The probability of the cut and splice operators is 0.1. The mutation probability is The line number of AND in the PLD is 24. The test data set consists of 30 patterns, which are generated with random noises (i.e. less than 5 bits are ipped randomly). For dierent learning methods were examined, i.e. MDL-based EHW with three types of MDL denitions (MDL1, MDL2 and MDL3 which correspond to equations (3), (4), and (5) in Appendix, respectively) and non-mdl EHW. The recognition result of the test set is plotted in Fig. 12. From the gure, it is clear that MDL-based EHWs give better performance for noisy patterns than EHW without MDL. An important feature of EHW is that the resultant expression can be represented by a simple Boolean function. For example, in one run, learned results in case of MDL3 are O 0 = I 34 I 38 ;O 1 = I 22 I 38 + I 13,and O 2 = I 37, where I i (0 i 63) indicates the location of the pixel in the pattern and O i is the recognition output for the pattern of letter i. Clearly, the results obtained by EHW are easier to understand, compared with ANN.

9 Correctness of test Number of noise bits MDL1 MDL2 MDL3 No MDL Fig. 11. Training Patterns Fig. 12. Recognition Result of Test Set 5 Discussion In this section we discuss about 1) the Boolean function which has high recognition ability for noisy patterns, 2) the advantage of VGA over SGA. First we discuss the Boolean function which has high recognition ability for noisy patterns. Roughly speaking, the Boolean function with better recognition ability is the function which has less inputs, that is, the function with more \don't care" inputs. We conrmed that we can get such a function using MDL. However, we can get more robust functions by adding more terms in the equation. The method to obtain such functions is the subject of the future research. In the pattern recognition system, we used VGA instead of SGA. The main advantage of VGA in pattern recognition is that we can handle larger inputs than using SGA. For example, EHW could learn three patterns of 16 inputs by SGA with the chromosome length of 840. On the other hand, by VGA, EHW can learn three patterns of 64 inputs with the chromosome length of in average. In addition, the learning by VGA is much faster than SGA; generation by VGA, 4053 by SGA. The reason why VGA can handle larger inputs than SGA is that VGA encodes into the chromosome only the inputs which actually generate AND terms. So, the chromosome length can be kept small. If SGA is used for problems of this nature, we suer the increase of the chromosome length because of many inputs, leading to the increase of GA execution time. In addition, VGA has a very good matching with MDL because MDL directs the GA search to nd smaller circuits. Thus, we can say that VGA is suitable for pattern recognition problems because it handles many inputs and learns small circuits. 6 Conclusion In this paper, we described the pattern recognition system using EHW. The system aims to recognize noisy patterns as neural networks do. We described the learning algorithm using MDL (Minimum Description Length) and VGA (Variable length chromosome GA). The noise-insensitive function was obtained eectively by using MDL as a tness function of GA. By using VGA, EHW could handle larger inputs with faster learning speed than using simple GA. We developed the pattern recognition system to show the feasibility of EHW for noise-insensitive recognition. We conducted experiments of recognizing noisy patterns and we conrmed that EHW has the ability to recognize noisy patterns.

10 References [Goldberg89] Goldberg D., \Genetic Algorithms in Search, Optimization, and Machine Learning" Addison Wesley, [Goldberg93] Goldberg D. et al., \Rapid Accurate Optimization of Dicult Problems using Fast Messy Genetic Algorithms" Proc. 5th Int. Joint Conf. on Genetic Algorithms (ICGA93), [Higuchi93] Higuchi T. et al., \Evolvable Hardware with Genetic Learning" in Proc. Simulation of Adaptive Behavior, MIT Press, [Higuchi94] Higuchi T. et al., \Evolvable Hardware with Genetic Learning" in Massively Parallel Articial Intelligence (eds. H. Kitano), MIT Press, [Higuchi95] Higuchi T. et al., \Evolvable Hardware and its Application to Pattern Recognition and Fault-tolerant Systems" in 1st Int. Workshop Towards Evolvable Hardware, Springer Verlag, [Itoh92] Itoh, S., \Application of MDL principle to pattern classication problems" (in Japanese), J. of Japanese Society for Articial Intelligence, Vol. 7, No. 4, [Kajitani95] Kajitani I. et al., \Variable Length Chromosome GA for Evolvable Hardware" in Proc. 3rd Int. Conf. on Evolutionary Computation (ICEC96), [Marchal94] P. Marchal et al., \Embryological Development on Silicon" Articial Life IV, [Rissanen89] Rissanen, J., Stochastic Complexity in Statistical Inquiry, World Scientic Series in Computer Science, Vol. 15, Appendix Denition of Complexity value for MDL We describe the C value which is the complexity value for MDL. The C value (i.e. the complexity of the EHW) determines the performance of the MDL. We introduce three types of C denitions as follows:- C 1 = X i j AN D Oi j; (3) C 2 = j AN D j2jor j; (4) C 3 = X i j AN D Oi j2jor Oi j : (5) Where j AN D O j and j OR O j are the numbers of ANDs and ORs connected to the output O. j AN D j (j OR j) is the number of ANDs (ORs) on the AND (OR). Consider Fig. 6(b) for instance. ANDs and ORs are represented as black dots and 2 marks in the gure. The values of C 1, C 2 and C 3 are 3 (= 1 + 2), 9 (= 3 2 3) and 5 (= ) respectively, because j AN D O0 j, j OR O0 j, j AN D O1 j, j OR O1 j, j AN D j, and j OR j are 1, 1, 2, 2, 3 and 3. The denition of C 1 is not very precise because it does not include the information of OR gates. On the other hand, C 2 and C 3 are expected to give more exact MDL values. We tested several other denitions of the complexity. In this paper we tested best three denitions. This article was processed using the LaT E X macro package with LLNCS style

ON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT

ON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT 216 ON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT *P.Nirmalkumar, **J.Raja Paul Perinbam, @S.Ravi and #B.Rajan *Research Scholar,

More information

A Parallel Processor for Distributed Genetic Algorithm with Redundant Binary Number

A Parallel Processor for Distributed Genetic Algorithm with Redundant Binary Number A Parallel Processor for Distributed Genetic Algorithm with Redundant Binary Number 1 Tomohiro KAMIMURA, 2 Akinori KANASUGI 1 Department of Electronics, Tokyo Denki University, 07ee055@ms.dendai.ac.jp

More information

On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition

On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition Kyrre Glette and Jim Torresen University of Oslo Department of Informatics PO Box 1080 Blindern, 0316 Oslo, Norway {kyrrehg,jimtoer}@ifiuiono

More information

ISSN: 2319-5967 ISO 9001:2008 Certified International Journal of Engineering Science and Innovative Technology (IJESIT) Volume 2, Issue 3, May 2013

ISSN: 2319-5967 ISO 9001:2008 Certified International Journal of Engineering Science and Innovative Technology (IJESIT) Volume 2, Issue 3, May 2013 Transistor Level Fault Finding in VLSI Circuits using Genetic Algorithm Lalit A. Patel, Sarman K. Hadia CSPIT, CHARUSAT, Changa., CSPIT, CHARUSAT, Changa Abstract This paper presents, genetic based algorithm

More information

Goldberg, D. E. (1989). Genetic algorithms in search, optimization, and machine learning. Reading, MA:

Goldberg, D. E. (1989). Genetic algorithms in search, optimization, and machine learning. Reading, MA: is another objective that the GA could optimize. The approach used here is also adaptable. On any particular project, the designer can congure the GA to focus on optimizing certain constraints (such as

More information

Numerical Research on Distributed Genetic Algorithm with Redundant

Numerical Research on Distributed Genetic Algorithm with Redundant Numerical Research on Distributed Genetic Algorithm with Redundant Binary Number 1 Sayori Seto, 2 Akinori Kanasugi 1,2 Graduate School of Engineering, Tokyo Denki University, Japan 10kme41@ms.dendai.ac.jp,

More information

Memory Allocation Technique for Segregated Free List Based on Genetic Algorithm

Memory Allocation Technique for Segregated Free List Based on Genetic Algorithm Journal of Al-Nahrain University Vol.15 (2), June, 2012, pp.161-168 Science Memory Allocation Technique for Segregated Free List Based on Genetic Algorithm Manal F. Younis Computer Department, College

More information

A Robust Method for Solving Transcendental Equations

A Robust Method for Solving Transcendental Equations www.ijcsi.org 413 A Robust Method for Solving Transcendental Equations Md. Golam Moazzam, Amita Chakraborty and Md. Al-Amin Bhuiyan Department of Computer Science and Engineering, Jahangirnagar University,

More information

Comparison of Major Domination Schemes for Diploid Binary Genetic Algorithms in Dynamic Environments

Comparison of Major Domination Schemes for Diploid Binary Genetic Algorithms in Dynamic Environments Comparison of Maor Domination Schemes for Diploid Binary Genetic Algorithms in Dynamic Environments A. Sima UYAR and A. Emre HARMANCI Istanbul Technical University Computer Engineering Department Maslak

More information

Using a Genetic Algorithm to Solve Crossword Puzzles. Kyle Williams

Using a Genetic Algorithm to Solve Crossword Puzzles. Kyle Williams Using a Genetic Algorithm to Solve Crossword Puzzles Kyle Williams April 8, 2009 Abstract In this report, I demonstrate an approach to solving crossword puzzles by using a genetic algorithm. Various values

More information

14.10.2014. Overview. Swarms in nature. Fish, birds, ants, termites, Introduction to swarm intelligence principles Particle Swarm Optimization (PSO)

14.10.2014. Overview. Swarms in nature. Fish, birds, ants, termites, Introduction to swarm intelligence principles Particle Swarm Optimization (PSO) Overview Kyrre Glette kyrrehg@ifi INF3490 Swarm Intelligence Particle Swarm Optimization Introduction to swarm intelligence principles Particle Swarm Optimization (PSO) 3 Swarms in nature Fish, birds,

More information

A very brief introduction to genetic algorithms

A very brief introduction to genetic algorithms A very brief introduction to genetic algorithms Radoslav Harman Design of experiments seminar FACULTY OF MATHEMATICS, PHYSICS AND INFORMATICS COMENIUS UNIVERSITY IN BRATISLAVA 25.2.2013 Optimization problems:

More information

EVOLVABLE BINARY ARTIFICIAL NEURAL NETWORK FOR DATA CLASSIFICATION

EVOLVABLE BINARY ARTIFICIAL NEURAL NETWORK FOR DATA CLASSIFICATION EVOLVABLE BINARY ARTIFICIAL NEURAL NETWORK FOR DATA CLASSIFICATION Janusz Starzyk Jing Pang School of Electrical and Computer Science Ohio University Athens, OH 4570, U. S. A. (740) 59-580 ABSTRACT This

More information

A Comparison of Genotype Representations to Acquire Stock Trading Strategy Using Genetic Algorithms

A Comparison of Genotype Representations to Acquire Stock Trading Strategy Using Genetic Algorithms 2009 International Conference on Adaptive and Intelligent Systems A Comparison of Genotype Representations to Acquire Stock Trading Strategy Using Genetic Algorithms Kazuhiro Matsui Dept. of Computer Science

More information

Chapter 4 Multi-Stage Interconnection Networks The general concept of the multi-stage interconnection network, together with its routing properties, have been used in the preceding chapter to describe

More information

Memory Systems. Static Random Access Memory (SRAM) Cell

Memory Systems. Static Random Access Memory (SRAM) Cell Memory Systems This chapter begins the discussion of memory systems from the implementation of a single bit. The architecture of memory chips is then constructed using arrays of bit implementations coupled

More information

University of St. Thomas ENGR 230 ---- Digital Design 4 Credit Course Monday, Wednesday, Friday from 1:35 p.m. to 2:40 p.m. Lecture: Room OWS LL54

University of St. Thomas ENGR 230 ---- Digital Design 4 Credit Course Monday, Wednesday, Friday from 1:35 p.m. to 2:40 p.m. Lecture: Room OWS LL54 Fall 2005 Instructor Texts University of St. Thomas ENGR 230 ---- Digital Design 4 Credit Course Monday, Wednesday, Friday from 1:35 p.m. to 2:40 p.m. Lecture: Room OWS LL54 Lab: Section 1: OSS LL14 Tuesday

More information

Hardware and Software

Hardware and Software Hardware and Software 1 Hardware and Software: A complete design Hardware and software support each other Sometimes it is necessary to shift functions from software to hardware or the other way around

More information

Basics of Digital Logic Design

Basics of Digital Logic Design CSE 675.2: Introduction to Computer Architecture Basics of Digital Logic Design Presentation D Study: B., B2, B.3 Slides by Gojko Babi From transistors to chips Chips from the bottom up: Basic building

More information

Topics Digital Circuit Design. Chapter 5 Combinational Circuit Design

Topics Digital Circuit Design. Chapter 5 Combinational Circuit Design Topics 2102581 Digital Circuit Design Chapter 5 Combinational Circuit Design Combinational circuit design with gates, MUX, and decoder Combinational circuit design with PLD devices Combinational circuit

More information

Dividing up a primitive class results in subclasses that do not completely dene a concept. As a result, the two classes must make frequent reference t

Dividing up a primitive class results in subclasses that do not completely dene a concept. As a result, the two classes must make frequent reference t LECTURE 12 Some Tips on How to Program in C++ When it comes to learning how to program in C++, there's no substitute for experience. But there are some things that are good to keep in mind. Advice on how

More information

Estimation of the COCOMO Model Parameters Using Genetic Algorithms for NASA Software Projects

Estimation of the COCOMO Model Parameters Using Genetic Algorithms for NASA Software Projects Journal of Computer Science 2 (2): 118-123, 2006 ISSN 1549-3636 2006 Science Publications Estimation of the COCOMO Model Parameters Using Genetic Algorithms for NASA Software Projects Alaa F. Sheta Computers

More information

THE HUMAN BRAIN. observations and foundations

THE HUMAN BRAIN. observations and foundations THE HUMAN BRAIN observations and foundations brains versus computers a typical brain contains something like 100 billion miniscule cells called neurons estimates go from about 50 billion to as many as

More information

l 8 r 3 l 9 r 1 l 3 l 7 l 1 l 6 l 5 l 10 l 2 l 4 r 2

l 8 r 3 l 9 r 1 l 3 l 7 l 1 l 6 l 5 l 10 l 2 l 4 r 2 Heuristic Algorithms for the Terminal Assignment Problem Sami Khuri Teresa Chiu Department of Mathematics and Computer Science San Jose State University One Washington Square San Jose, CA 95192-0103 khuri@jupiter.sjsu.edu

More information

Welcome to the National Instruments presentation of the Spartan-3E Starter Board as an academic learning platform.

Welcome to the National Instruments presentation of the Spartan-3E Starter Board as an academic learning platform. Welcome to the National Instruments presentation of the Spartan-3E Starter Board as an academic learning platform. Understanding digital logic and FPGA concepts can be daunting for some undergraduate students,

More information

Memory and Programmable Logic

Memory and Programmable Logic Chapter 7 Memory and Programmable Logic 7 Outline! Introduction! RandomAccess Memory! Memory Decoding! Error Detection and Correction! ReadOnly Memory! Programmable Devices! Sequential Programmable Devices

More information

1. Introduction MINING AND TRACKING EVOLVING WEB USER TRENDS FROM LARGE WEB SERVER LOGS. Basheer Hawwash and Olfa Nasraoui

1. Introduction MINING AND TRACKING EVOLVING WEB USER TRENDS FROM LARGE WEB SERVER LOGS. Basheer Hawwash and Olfa Nasraoui MINING AND TRACKING EVOLVING WEB USER TRENDS FROM LARGE WEB SERVER LOGS Basheer Hawwash and Olfa Nasraoui Knowledge Discovery and Web Mining Lab Dept. of Computer Engineering and Computer Science University

More information

IAI : Biological Intelligence and Neural Networks

IAI : Biological Intelligence and Neural Networks IAI : Biological Intelligence and Neural Networks John A. Bullinaria, 2005 1. How do Humans do Intelligent Things? 2. What are Neural Networks? 3. What are Artificial Neural Networks used for? 4. Introduction

More information

FPGA Design of Reconfigurable Binary Processor Using VLSI

FPGA Design of Reconfigurable Binary Processor Using VLSI ISSN (Online) : 2319-8753 ISSN (Print) : 2347-6710 International Journal of Innovative Research in Science, Engineering and Technology Volume 3, Special Issue 3, March 2014 2014 International Conference

More information

Oscillations of the Sending Window in Compound TCP

Oscillations of the Sending Window in Compound TCP Oscillations of the Sending Window in Compound TCP Alberto Blanc 1, Denis Collange 1, and Konstantin Avrachenkov 2 1 Orange Labs, 905 rue Albert Einstein, 06921 Sophia Antipolis, France 2 I.N.R.I.A. 2004

More information

Face Locating and Tracking for Human{Computer Interaction. Carnegie Mellon University. Pittsburgh, PA 15213

Face Locating and Tracking for Human{Computer Interaction. Carnegie Mellon University. Pittsburgh, PA 15213 Face Locating and Tracking for Human{Computer Interaction Martin Hunke Alex Waibel School of Computer Science Carnegie Mellon University Pittsburgh, PA 15213 Abstract Eective Human-to-Human communication

More information

Genetic Algorithm Evolution of Cellular Automata Rules for Complex Binary Sequence Prediction

Genetic Algorithm Evolution of Cellular Automata Rules for Complex Binary Sequence Prediction Brill Academic Publishers P.O. Box 9000, 2300 PA Leiden, The Netherlands Lecture Series on Computer and Computational Sciences Volume 1, 2005, pp. 1-6 Genetic Algorithm Evolution of Cellular Automata Rules

More information

Introduction Number Systems and Conversion

Introduction Number Systems and Conversion UNIT 1 Introduction Number Systems and Conversion Objectives 1. Introduction The first part of this unit introduces the material to be studied later. In addition to getting an overview of the material

More information

Depth and Excluded Courses

Depth and Excluded Courses Depth and Excluded Courses Depth Courses for Communication, Control, and Signal Processing EECE 5576 Wireless Communication Systems 4 SH EECE 5580 Classical Control Systems 4 SH EECE 5610 Digital Control

More information

RAM & ROM Based Digital Design. ECE 152A Winter 2012

RAM & ROM Based Digital Design. ECE 152A Winter 2012 RAM & ROM Based Digital Design ECE 152A Winter 212 Reading Assignment Brown and Vranesic 1 Digital System Design 1.1 Building Block Circuits 1.1.3 Static Random Access Memory (SRAM) 1.1.4 SRAM Blocks in

More information

situation when the value of coecients (obtained by means of the transformation) corresponding to higher frequencies are either zero or near to zero. T

situation when the value of coecients (obtained by means of the transformation) corresponding to higher frequencies are either zero or near to zero. T Dithering as a method for image data compression Pavel Slav k (slavik@cslab.felk.cvut.cz), Jan P ikryl (prikryl@sgi.felk.cvut.cz) Czech Technical University Prague Faculty of Electrical Engineering Department

More information

Through Evolutionary Neural Networks. The University of Texas at Austin. Abstract

Through Evolutionary Neural Networks. The University of Texas at Austin. Abstract Discovering Complex Othello Strategies Through Evolutionary Neural Networks David E. Moriarty and Risto Miikkulainen Department of Computer Sciences The University of Texas at Austin Austin, TX 78712-1188

More information

Multimedia Data Processing Elements for Digital TV and Multimedia Services in Home Server Platform

Multimedia Data Processing Elements for Digital TV and Multimedia Services in Home Server Platform Multimedia Data Processing Elements for Digital TV and Multimedia Services in Home Server Platform Minte Chen IEEE Transactions on Consumer Electronics, Vol. 49, No.1, FEBRUARY 2003 IEEE Transactions on

More information

Analecta Vol. 8, No. 2 ISSN 2064-7964

Analecta Vol. 8, No. 2 ISSN 2064-7964 EXPERIMENTAL APPLICATIONS OF ARTIFICIAL NEURAL NETWORKS IN ENGINEERING PROCESSING SYSTEM S. Dadvandipour Institute of Information Engineering, University of Miskolc, Egyetemváros, 3515, Miskolc, Hungary,

More information

Chapter 2 Digital Components. Section 2.1 Integrated Circuits

Chapter 2 Digital Components. Section 2.1 Integrated Circuits Chapter 2 Digital Components Section 2.1 Integrated Circuits An integrated circuit (IC) is a small silicon semiconductor crystal, called a chip, containing the electronic components for the digital gates

More information

Basic Logic Gates Richard E. Haskell

Basic Logic Gates Richard E. Haskell BASIC LOGIC GATES 1 E Basic Logic Gates Richard E. Haskell All digital systems are made from a few basic digital circuits that we call logic gates. These circuits perform the basic logic functions that

More information

A Genetic Algorithm Processor Based on Redundant Binary Numbers (GAPBRBN)

A Genetic Algorithm Processor Based on Redundant Binary Numbers (GAPBRBN) ISSN: 2278 1323 All Rights Reserved 2014 IJARCET 3910 A Genetic Algorithm Processor Based on Redundant Binary Numbers (GAPBRBN) Miss: KIRTI JOSHI Abstract A Genetic Algorithm (GA) is an intelligent search

More information

Optimizing CPU Scheduling Problem using Genetic Algorithms

Optimizing CPU Scheduling Problem using Genetic Algorithms Optimizing CPU Scheduling Problem using Genetic Algorithms Anu Taneja Amit Kumar Computer Science Department Hindu College of Engineering, Sonepat (MDU) anutaneja16@gmail.com amitkumar.cs08@pec.edu.in

More information

Circle detection and tracking speed-up based on change-driven image processing

Circle detection and tracking speed-up based on change-driven image processing Circle detection and tracking speed-up based on change-driven image processing Fernando Pardo, Jose A. Boluda, Julio C. Sosa Departamento de Informática, Universidad de Valencia Avda. Vicente Andres Estelles

More information

GETTING STARTED WITH PROGRAMMABLE LOGIC DEVICES, THE 16V8 AND 20V8

GETTING STARTED WITH PROGRAMMABLE LOGIC DEVICES, THE 16V8 AND 20V8 GETTING STARTED WITH PROGRAMMABLE LOGIC DEVICES, THE 16V8 AND 20V8 Robert G. Brown All Rights Reserved August 25, 2000 Alta Engineering 58 Cedar Lane New Hartford, CT 06057-2905 (860) 489-8003 www.alta-engineering.com

More information

Genetic Algorithm an Approach to Solve Global Optimization Problems

Genetic Algorithm an Approach to Solve Global Optimization Problems Genetic Algorithm an Approach to Solve Global Optimization Problems PRATIBHA BAJPAI Amity Institute of Information Technology, Amity University, Lucknow, Uttar Pradesh, India, pratibha_bajpai@rediffmail.com

More information

Floating Point Fused Add-Subtract and Fused Dot-Product Units

Floating Point Fused Add-Subtract and Fused Dot-Product Units Floating Point Fused Add-Subtract and Fused Dot-Product Units S. Kishor [1], S. P. Prakash [2] PG Scholar (VLSI DESIGN), Department of ECE Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu,

More information

Combinational logic lab

Combinational logic lab ECE2883 HP: Lab 3- Logic Experts (LEs) Combinational logic lab Implementing combinational logic with Quartus We should be starting to realize that you, the SMEs in this course, are just a specific type

More information

ROC Graphs: Notes and Practical Considerations for Data Mining Researchers

ROC Graphs: Notes and Practical Considerations for Data Mining Researchers ROC Graphs: Notes and Practical Considerations for Data Mining Researchers Tom Fawcett 1 1 Intelligent Enterprise Technologies Laboratory, HP Laboratories Palo Alto Alexandre Savio (GIC) ROC Graphs GIC

More information

Low-resolution Image Processing based on FPGA

Low-resolution Image Processing based on FPGA Abstract Research Journal of Recent Sciences ISSN 2277-2502. Low-resolution Image Processing based on FPGA Mahshid Aghania Kiau, Islamic Azad university of Karaj, IRAN Available online at: www.isca.in,

More information

Sistemas Digitais I LESI - 2º ano

Sistemas Digitais I LESI - 2º ano Sistemas Digitais I LESI - 2º ano Lesson 6 - Combinational Design Practices Prof. João Miguel Fernandes (miguel@di.uminho.pt) Dept. Informática UNIVERSIDADE DO MINHO ESCOLA DE ENGENHARIA - PLDs (1) - The

More information

Introduction to Logistic Regression

Introduction to Logistic Regression OpenStax-CNX module: m42090 1 Introduction to Logistic Regression Dan Calderon This work is produced by OpenStax-CNX and licensed under the Creative Commons Attribution License 3.0 Abstract Gives introduction

More information

Counters and Registers. Dr. Anurag Srivastava

Counters and Registers. Dr. Anurag Srivastava Counters and Registers Dr. Anurag Srivastava 1 Basic of digital design Basic gates (AND,OR, NOR, NAND and INVERTER) Universal gates (NAND and NOR) Design of any function using basic gates F=xy+(xyz+zx+xz)xy

More information

NEUROEVOLUTION OF AUTO-TEACHING ARCHITECTURES

NEUROEVOLUTION OF AUTO-TEACHING ARCHITECTURES NEUROEVOLUTION OF AUTO-TEACHING ARCHITECTURES EDWARD ROBINSON & JOHN A. BULLINARIA School of Computer Science, University of Birmingham Edgbaston, Birmingham, B15 2TT, UK e.robinson@cs.bham.ac.uk This

More information

Software development process

Software development process OpenStax-CNX module: m14619 1 Software development process Trung Hung VO This work is produced by OpenStax-CNX and licensed under the Creative Commons Attribution License 2.0 Abstract A software development

More information

number of players in each group

number of players in each group TRAINING INTELLIGENT AGENTS USING HUMAN INTERNET DATA ELIZABETH SKLARy ALAN D. BLAIRz PABLO FUNESy JORDAN POLLACKy ydemo Lab, Dept. of Computer Science, Brandeis University, Waltham, MA 2454-911, USA E-mail:

More information

Proceedings of the First IEEE Conference on Evolutionary Computation - IEEE World Congress on Computational Intelligence, June

Proceedings of the First IEEE Conference on Evolutionary Computation - IEEE World Congress on Computational Intelligence, June Proceedings of the First IEEE Conference on Evolutionary Computation - IEEE World Congress on Computational Intelligence, June 26-July 2, 1994, Orlando, Florida, pp. 829-833. Dynamic Scheduling of Computer

More information

Hybrid Electronics Laboratory

Hybrid Electronics Laboratory Hybrid Electronics Laboratory Design and Simulation of Decoders, Encoders, Multiplexer and Demultiplexer Aim: To study decoders, encoders, multiplexer and demultiplexer. Objectives: 1. Implement and simulate

More information

SYSTEMS AND SOFTWARE REQUIREMENTS SPECIFICATION (SSRS) TEMPLATE. Version A.4, January 2014 FOREWORD DOCUMENT CONVENTIONS

SYSTEMS AND SOFTWARE REQUIREMENTS SPECIFICATION (SSRS) TEMPLATE. Version A.4, January 2014 FOREWORD DOCUMENT CONVENTIONS SYSTEMS AND SOFTWARE REQUIREMENTS SPECIFICATION (SSRS) TEMPLATE Version A.4, January 2014 FOREWORD This document was written to provide software development projects with a template for generating a System

More information

MULTI-AGENT SYSTEM FOR DECENTRALIZED COMPUTER NETWORK MANAGEMENT Krzysztof Cetnarowicz Jaros law Kozlak Institute of Computer Science, AGH - University of Mining and Metallurgy Al. Mickiewicza 30, 30-059

More information

DNA Mapping/Alignment. Team: I Thought You GNU? Lars Olsen, Venkata Aditya Kovuri, Nick Merowsky

DNA Mapping/Alignment. Team: I Thought You GNU? Lars Olsen, Venkata Aditya Kovuri, Nick Merowsky DNA Mapping/Alignment Team: I Thought You GNU? Lars Olsen, Venkata Aditya Kovuri, Nick Merowsky Overview Summary Research Paper 1 Research Paper 2 Research Paper 3 Current Progress Software Designs to

More information

Digital System Design. Digital System Design with Verilog

Digital System Design. Digital System Design with Verilog Digital System Design with Verilog Adapted from Z. Navabi Portions Copyright Z. Navabi, 2006 1 Digital System Design Automation with Verilog Digital Design Flow Design entry Testbench in Verilog Design

More information

Final Exam review: chapter 4 and 5. Supplement 3 and 4

Final Exam review: chapter 4 and 5. Supplement 3 and 4 Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much

More information

Effect of Using Neural Networks in GA-Based School Timetabling

Effect of Using Neural Networks in GA-Based School Timetabling Effect of Using Neural Networks in GA-Based School Timetabling JANIS ZUTERS Department of Computer Science University of Latvia Raina bulv. 19, Riga, LV-1050 LATVIA janis.zuters@lu.lv Abstract: - The school

More information

Hyperspectral images retrieval with Support Vector Machines (SVM)

Hyperspectral images retrieval with Support Vector Machines (SVM) Hyperspectral images retrieval with Support Vector Machines (SVM) Miguel A. Veganzones Grupo Inteligencia Computacional Universidad del País Vasco (Grupo Inteligencia SVM-retrieval Computacional Universidad

More information

CS 16: Assembly Language Programming for the IBM PC and Compatibles

CS 16: Assembly Language Programming for the IBM PC and Compatibles CS 16: Assembly Language Programming for the IBM PC and Compatibles First, a little about you Your name Have you ever worked with/used/played with assembly language? If so, talk about it Why are you taking

More information

The counterpart to a DAC is the ADC, which is generally a more complicated circuit. One of the most popular ADC circuit is the successive

The counterpart to a DAC is the ADC, which is generally a more complicated circuit. One of the most popular ADC circuit is the successive The counterpart to a DAC is the ADC, which is generally a more complicated circuit. One of the most popular ADC circuit is the successive approximation converter. 1 2 The idea of sampling is fully covered

More information

Nonlinear Model Predictive Control of Hammerstein and Wiener Models Using Genetic Algorithms

Nonlinear Model Predictive Control of Hammerstein and Wiener Models Using Genetic Algorithms Nonlinear Model Predictive Control of Hammerstein and Wiener Models Using Genetic Algorithms Al-Duwaish H. and Naeem, Wasif Electrical Engineering Department/King Fahd University of Petroleum and Minerals

More information

FPGA IMPLEMENTATION OF 4D-PARITY BASED DATA CODING TECHNIQUE

FPGA IMPLEMENTATION OF 4D-PARITY BASED DATA CODING TECHNIQUE FPGA IMPLEMENTATION OF 4D-PARITY BASED DATA CODING TECHNIQUE Vijay Tawar 1, Rajani Gupta 2 1 Student, KNPCST, Hoshangabad Road, Misrod, Bhopal, Pin no.462047 2 Head of Department (EC), KNPCST, Hoshangabad

More information

Lecture N -1- PHYS 3330. Microcontrollers

Lecture N -1- PHYS 3330. Microcontrollers Lecture N -1- PHYS 3330 Microcontrollers If you need more than a handful of logic gates to accomplish the task at hand, you likely should use a microcontroller instead of discrete logic gates 1. Microcontrollers

More information

Network Model. University of Tsukuba. of the system. Load balancing policies are often. used for balancing the workload of distributed systems.

Network Model. University of Tsukuba. of the system. Load balancing policies are often. used for balancing the workload of distributed systems. CDC-INV A Performance Comparison of Dynamic vs. Static Load Balancing Policies in a Mainframe { Personal Computer Network Model Hisao Kameda El-Zoghdy Said Fathy y Inhwan Ryu z Jie Li x yzx University

More information

Comp 150 Booleans and Digital Logic

Comp 150 Booleans and Digital Logic Comp 150 Booleans and Digital Logic Recall the bool date type in Python has the two literals True and False and the three operations: not, and, or. The operations are defined by truth tables (see page

More information

Evolutionary Testing of PHP Web Applications with WETT

Evolutionary Testing of PHP Web Applications with WETT Evolutionary Testing of PHP Web Applications with WETT Francesco Bolis, Angelo Gargantini, Marco Guarnieri, and Eros Magri Dip. di Ing. dell'informazione e Metodi Matematici, Università di Bergamo, Italy

More information

Hiroshi ISHIGURO, Ritsuko SATO & Toru ISHIDA. Kyoto University. Sakyo-ku, Kyoto , JAPAN.

Hiroshi ISHIGURO, Ritsuko SATO & Toru ISHIDA. Kyoto University. Sakyo-ku, Kyoto , JAPAN. Robot Oriented State Space Construction Hiroshi ISHIGURO, Ritsuko SATO & Toru ISHIDA Department of Information Science Kyoto University Sakyo-ku, Kyoto 606-01, JAPAN E-mail: ishiguro/ritsuko/ishida@kuis.kyoto-u.ac.jp

More information

Lab 4: 26 th March 2012. Exercise 1: Evolutionary algorithms

Lab 4: 26 th March 2012. Exercise 1: Evolutionary algorithms Lab 4: 26 th March 2012 Exercise 1: Evolutionary algorithms 1. Found a problem where EAs would certainly perform very poorly compared to alternative approaches. Explain why. Suppose that we want to find

More information

Foundations. Computational Intelligence

Foundations. Computational Intelligence Foundations Computational Intelligence Intelligence A standard dictionary definition of intelligence is: "1 a (1): The ability to learn or understand or to deal with new or trying situations : REASON;

More information

Evolutionary SAT Solver (ESS)

Evolutionary SAT Solver (ESS) Ninth LACCEI Latin American and Caribbean Conference (LACCEI 2011), Engineering for a Smart Planet, Innovation, Information Technology and Computational Tools for Sustainable Development, August 3-5, 2011,

More information

FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers

FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers Bogdan Mătăsaru and Tudor Jebelean RISC-Linz, A 4040 Linz, Austria email: bmatasar@risc.uni-linz.ac.at

More information

Differential Evolution Particle Swarm Optimization for Digital Filter Design

Differential Evolution Particle Swarm Optimization for Digital Filter Design Differential Evolution Particle Swarm Optimization for Digital Filter Design Bipul Luitel, and Ganesh K. Venayagamoorthy, Abstract In this paper, swarm and evolutionary algorithms have been applied for

More information

Effects of Symbiotic Evolution in Genetic Algorithms for Job-Shop Scheduling

Effects of Symbiotic Evolution in Genetic Algorithms for Job-Shop Scheduling Proceedings of the th Hawaii International Conference on System Sciences - 00 Effects of Symbiotic Evolution in Genetic Algorithms for Job-Shop Scheduling Yasuhiro Tsujimura Yuichiro Mafune Mitsuo Gen

More information

Practical Applications of Evolutionary Computation to Financial Engineering

Practical Applications of Evolutionary Computation to Financial Engineering Hitoshi Iba and Claus C. Aranha Practical Applications of Evolutionary Computation to Financial Engineering Robust Techniques for Forecasting, Trading and Hedging 4Q Springer Contents 1 Introduction to

More information

Introduction to Machine Learning and Data Mining. Prof. Dr. Igor Trajkovski trajkovski@nyus.edu.mk

Introduction to Machine Learning and Data Mining. Prof. Dr. Igor Trajkovski trajkovski@nyus.edu.mk Introduction to Machine Learning and Data Mining Prof. Dr. Igor Trakovski trakovski@nyus.edu.mk Neural Networks 2 Neural Networks Analogy to biological neural systems, the most robust learning systems

More information

An intelligent stock trading decision support system through integration of genetic algorithm based fuzzy neural network and articial neural network

An intelligent stock trading decision support system through integration of genetic algorithm based fuzzy neural network and articial neural network Fuzzy Sets and Systems 118 (2001) 21 45 www.elsevier.com/locate/fss An intelligent stock trading decision support system through integration of genetic algorithm based fuzzy neural network and articial

More information

Threshold Logic. 2.1 Networks of functions

Threshold Logic. 2.1 Networks of functions 2 Threshold Logic 2. Networks of functions We deal in this chapter with the simplest kind of computing units used to build artificial neural networks. These computing elements are a generalization of the

More information

Chapter 7 Memory and Programmable Logic

Chapter 7 Memory and Programmable Logic NCNU_2013_DD_7_1 Chapter 7 Memory and Programmable Logic 71I 7.1 Introduction ti 7.2 Random Access Memory 7.3 Memory Decoding 7.5 Read Only Memory 7.6 Programmable Logic Array 77P 7.7 Programmable Array

More information

9/14/2011 14.9.2011 8:38

9/14/2011 14.9.2011 8:38 Algorithms and Implementation Platforms for Wireless Communications TLT-9706/ TKT-9636 (Seminar Course) BASICS OF FIELD PROGRAMMABLE GATE ARRAYS Waqar Hussain firstname.lastname@tut.fi Department of Computer

More information

Memory Address Decoding

Memory Address Decoding Memory Address Decoding 1 ROAD MAP Memory Address Decoding S-RAM Interfacing Process Solved Examples For S-RAM Decoding D-RAM Interfacing 2 Memory Addressing The processor can usually address a memory

More information

AUTOMATIC ADJUSTMENT FOR LASER SYSTEMS USING A STOCHASTIC BINARY SEARCH ALGORITHM TO COPE WITH NOISY SENSING DATA

AUTOMATIC ADJUSTMENT FOR LASER SYSTEMS USING A STOCHASTIC BINARY SEARCH ALGORITHM TO COPE WITH NOISY SENSING DATA INTERNATIONAL JOURNAL ON SMART SENSING AND INTELLIGENT SYSTEMS, VOL. 1, NO. 2, JUNE 2008 AUTOMATIC ADJUSTMENT FOR LASER SYSTEMS USING A STOCHASTIC BINARY SEARCH ALGORITHM TO COPE WITH NOISY SENSING DATA

More information

An afterburner for the Tiger

An afterburner for the Tiger An afterburner for the Tiger Gunther Zielosko, Heiko Grimm 1. Objectives Anybody who deals with the BASIC-Tiger cannot complain about the programming convenience (even with complex tasks) and the great

More information

New binary representation in Genetic Algorithms for solving TSP by mapping permutations to a list of ordered numbers

New binary representation in Genetic Algorithms for solving TSP by mapping permutations to a list of ordered numbers Proceedings of the 5th WSEAS Int Conf on COMPUTATIONAL INTELLIGENCE, MAN-MACHINE SYSTEMS AND CYBERNETICS, Venice, Italy, November 0-, 006 363 New binary representation in Genetic Algorithms for solving

More information

Digital Systems. Role of the Digital Engineer

Digital Systems. Role of the Digital Engineer Digital Systems Role of the Digital Engineer Digital Design Engineers attempt to clearly define the problem(s) Possibly, break the problem into many smaller problems Engineers then develop a strategy for

More information

Introduction To Genetic Algorithms

Introduction To Genetic Algorithms 1 Introduction To Genetic Algorithms Dr. Rajib Kumar Bhattacharjya Department of Civil Engineering IIT Guwahati Email: rkbc@iitg.ernet.in References 2 D. E. Goldberg, Genetic Algorithm In Search, Optimization

More information

MODULE 11- DESIGN OF SYNCHRONOUS SEQUENTIAL COUNTERS AND STATE MACHINES

MODULE 11- DESIGN OF SYNCHRONOUS SEQUENTIAL COUNTERS AND STATE MACHINES Introduction to Digital Electronics Module 11: Design of Sequential Counters and State Machines 1 MODULE 11- DESIGN OF SYNCHRONOUS SEQUENTIAL COUNTERS AND STATE MACHINES OVERVIEW: A synchronous sequential

More information

Aims and Objectives. E 3.05 Digital System Design. Course Syllabus. Course Syllabus (1) Programmable Logic

Aims and Objectives. E 3.05 Digital System Design. Course Syllabus. Course Syllabus (1) Programmable Logic Aims and Objectives E 3.05 Digital System Design Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk How to go

More information

EXPERIMENT 5. ELEMENTARY GATE NETWORKS

EXPERIMENT 5. ELEMENTARY GATE NETWORKS EXPERIMENT 5. ELEMENTARY GATE NETWORKS I. Introduction 1) Objectives In this experiment, you will get familiar with some of commonly used elementary gate networks. In particular, multiplexer, comparator

More information

REDESIGN BASED OPTIMIZATION FOR DISTRIBUTED DATABASES

REDESIGN BASED OPTIMIZATION FOR DISTRIBUTED DATABASES STUDIA UNIV. BABE BOLYAI, INFORMATICA, Volume L, Number 1, 2005 REDESIGN BASED OPTIMIZATION FOR DISTRIBUTED DATABASES HOREA-ADRIAN GREBLA, ANCA GOG Abstract. The execution process of the queries in distributed

More information

ENG DIGITAL CIRCUITS AND MICROPROCESSORS (3 lecture hours, 1 design hour) Fall 2015: Tuesday/Thursday 7:00 PM 8:20 PM/8:30 PM 8:55 PM/AR128

ENG DIGITAL CIRCUITS AND MICROPROCESSORS (3 lecture hours, 1 design hour) Fall 2015: Tuesday/Thursday 7:00 PM 8:20 PM/8:30 PM 8:55 PM/AR128 ENG 312-02 DIGITAL CIRCUITS AND MICROPROCESSORS (3 lecture hours, 1 design hour) Course Information Professor: Francis Delahanty Fall 2015: Tuesday/Thursday 7:00 PM 8:20 PM/8:30 PM 8:55 PM/AR128 Course

More information

Lecture 2: The Complexity of Some Problems

Lecture 2: The Complexity of Some Problems IAS/PCMI Summer Session 2000 Clay Mathematics Undergraduate Program Basic Course on Computational Complexity Lecture 2: The Complexity of Some Problems David Mix Barrington and Alexis Maciel July 18, 2000

More information

Laser Gesture Recognition for Human Machine Interaction

Laser Gesture Recognition for Human Machine Interaction International Journal of Computer Sciences and Engineering Open Access Research Paper Volume-04, Issue-04 E-ISSN: 2347-2693 Laser Gesture Recognition for Human Machine Interaction Umang Keniya 1*, Sarthak

More information

Chapter 12. Algorithmic State Machine

Chapter 12. Algorithmic State Machine Chapter 12 Algorithmic State Machine 12.0 Introduction In Chapter 10, we introduced two models of synchronous sequential network, which are Mealy and Moore machines. In this chapter, we would like to introduce

More information