DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks

Transcription

1 S C I E N C E P A S S I O N T E C H N O L O G Y DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks Peter Pessl, Daniel Gruss, Clémentine Maurice, Michael Schwarz, Stefan Mangard IAIK, Graz University of Technology, Austria u

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3 Setting Cloud Servers Multi-CPU (multi-socket) systems Multiple tenants separate VMs dedicated CPUs no shared cache No shared memory no cross-vm memory deduplication Previously slow covert channel (< 1 kbps) no side channel 3

4 Overview Cross-CPU attacks using DRAM addressing (DRAMA) fast covert channel (up to 2 Mbps) first side-channel attack Reverse-engineered DRAM addressing two approaches Improving existing attacks 4

5 DRAM Organization Hierarchy of CPUs CPU 1 Interconnect CPU 2 MC MC DRAM Bus DRAM Bus 5

6 DRAM Organization Hierarchy of CPUs Channels DIMMs CPU MC DIMM Channel A Channel B DIMM DIMM DIMM 6

7 DRAM Organization Hierarchy of CPUs Channels DIMMs Ranks.. Bank 1 Bank 2 Bank 8.. Banks 7

8 DRAM Banks Row 1 Row 2 Row N Row Buffer Memory array rows of columns Row Buffer buffers one entire row (8 KB) 8

9 The Row Buffer Behavior similar to a cache row hits fast access row conflicts slow access 9

10 Reverse Engineering of DRAM Addressing 10

11 Reverse-Engineering DRAM Addressing Mapping to banks using physical-address bits Complex addressing functions distribute traffic to channels/banks undisclosed (Intel) Two approaches to reverse engineer Presumption: linear functions (XORs) 11

12 Approach 1: Probing the Memory Bus Probing of control signals CS, BA, measure voltage with Osci. recover logic value Repeated access to address until value is determined Function reconstruction linear algebra over bits 12

13 Approach 2: Fully Automated SW-based Exploit timing differences Measuring phase build sets of same-bank addresses alternating access to two addresses measure avg. access time Reconstruction phase exhaustive search over linear functions with up to n set coefficients Total time: seconds 13

14 Comparison Probing recover function labels find a ground truth equipment and access to internals of machine SW-based fully automated ability to run remotely, sandboxed, and on mobile devices 14

15 Some Results - Desktop BA0 BA1 Rank BA Ch. Intel Haswell (desktop system) DDR3 15

16 Some Results Server System BG0 CPU Rank BG1 BA0 BA Ch. Dual-CPU Intel Haswell-EP DDR4 16

17 Some Results Mobile Rank BA0 BA1 BA Ch. Samsung Exynos 7420 (Galaxy S6) LPDDR4 17

18 Cross-CPU Attacks and how it continues with Romeo and Juliet 18

19 High-speed covert channel 19

20 Concept Occupy different rows in the same bank Sender send 1: continuously access row send 0: don t do anything Receiver access row and measure avg. time infer sent bits based on time Sender Sender Receiver Receiver Receiver Row Buffer 20

21 Implementation Each bank is a channel use up to 8 banks in parallel multithreading Performance: desktop: 2.1 Mbps multi-cpu server: 1.2 Mbps Intel Haswell (desktop system) 21

22 Performance Comparison Performance Cross-CPU No Shared Memory Ours 2.1 Mbps Prime+Probe [2] 536 Kbps Flush+Reload [2] 2.3 Mbps Flush+Flush [2] 3.8 Mbps Memory Bus Contention [3] 746 bps Deduplication [4] 90 bps 22

23 Low-noise side-channel attack 23

24 Spying on Memory Accesses Memory in the same row/bank row size 8 KB / page size 4 KB Spy activates conflict row Victim computes and possibly accesses shared row Spy accesses shared row fast row hit victim access Victim Victim Spy Row Buffer Victim Victim Spy Spy 24

25 Example Keystrokes in Firefox address bar 25

26 Implementation high spatial accuracy (down to 512 B) very low number of false positives monitor single events Finding addresses: template attack [1] automatic location of vulnerable addresses scan large fraction of memory (4 KB pages) 26

27 Countermeasures to DRAMA Restrictions of rdtsc clflush Multi-CPU: separating DRAM for tenants only access to CPU-local memory degradation into single-cpu system Detection via high number of cache misses / row conflicts 27

28 Improving Attacks - Rowhammer Rowhammer inducing bit flips in DRAM by quickly switching rows requires addressing functions First documented bit flips on DDR4 Jan

29 The End of Romeo and Juliet 29

30 Source code for reverse-engineering tool and side-channel attack at 30

31 S C I E N C E P A S S I O N T E C H N O L O G Y DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks Peter Pessl, Daniel Gruss, Clémentine Maurice, Michael Schwarz, Stefan Mangard IAIK, Graz University of Technology, Austria 31 u

32 Bibliography [1] Gruss, Spreitzer, Mangard. Cache Template Attacks: Automating Attacks on Inclusive Last-Level Caches. In Usenix Security 2015 [2] Gruss, Maurice, Wagner, Mangard. Flush+Flush: A Fast and Stealthy Cache Attack. In DIMVA 16 [3] Wu, Xu, Wang. Whispers in the Hyper-space: High-bandwidth and Reliable Covert Channel Attacks Inside the Cloud. In Usenix Security 2012 [4] Xiao, Xu, Huang, Wang. Security implications of memory deduplication in a virtualized environment. In DSN 13 32