Technical Approach. Figure 2. Switch-level Schematic of FEEC Little Box

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1 Technical Approach Team Name: Future Energy Electronics Center Registration Code: 545-W31m Overview of Approach: Every component in the Future Energy Electronics Center (FEEC)'s prototype serves multiple purposes. While performing its intended function, each element also seamlessly augments the rest of the system with considerations toward volume, efficiency, thermal and technical requirements. Supervised by computer aided design (CAD) software, this integration allows for the maximum utilization of space - ensuring the little box lives up to its name. These design decisions enable every aspect of FEEC s prototype to perform the following multiple functions. Input ripple management is based on an FEEC-patented two-stage power conversion design 1 using a multiphase dc/dc converter as the front stage conditioning circuit. A proportional resonant (PR) controller 2 enhances the double line-frequency ripple current suppression. Compared with a conventional capacitive filter, this first stage design reduces ripple more effectively, is more efficient, and drastically shrinks volume; The dc/ac inverter stage offers high efficiency with the use of GaN devices, reduces output filter size through high frequency operation, minimizes differential mode (DM) electromagnetic interference (EMI) noise with a three-level inverter output voltage, and minimizes common mode (CM) EMI noise through complementary switch-pair s synchronized operation and symmetrical inductor design; Optimized output filter topology and cut-off frequency selection to minimize volume while ensuring compliance with FCC Class B EMI, leakage current, and harmonic limits; Copper serves as both a heat sink and enclosure. Figure 1. FEEC Little Box Achieves a Volume of 33 in 3 Figure 2. Switch-level Schematic of FEEC Little Box This system-level approach to design, combined with state-of-the-art devices and layout, achieves a power density of 61.2 W/in 3. The photograph and circuit diagram of our little box prototype with 33 in 3 volume are shown in Figures 1 and 2. Power is handled by three main stages: (1) a dc/dc stage to control the input ripple; (2) a dc/ac stage; and (3) a harmonic and EMI filter stage. The dc/ac inverter stage adopts an ac switch clamped converter, originally found in the early transistor clamp converter (TCC) 3, with a common name as T-type converter for three-phase inverters. In the single-phase full-bridge configuration, the power circuit itself was patented with a trade name Highly Efficient and Reliable Inverter Concept (HERIC) inverter 4. This inverter has been implemented with reactive power capability.

2 Innovations Achieved: a) 120Hz input current/voltage ripple requirement A front-end four-phase dc/dc converter stage regulates the dc-bus voltage for the inverter and controls the dc/dc inductor current to eliminate the input ripple. This FEEC design manages input ripple magnitude more effectively, occupies less volume, and operates more efficiently than a conventional electrolytic capacitor filter. As shown in Figure 3, an internal current loop and external voltage loop work together to minimize the 120Hz input ripple. The external voltage loop senses the voltage of the dc-link capacitor, Cbus, and passes it through a notch filter to eliminate the 120Hz ripple. The voltage Figure 3. Control Diagram of DC/DC Stage compensator, a PI controller, then generates a current reference, iref, for the internal current loop. The internal current loop controls the current of the inductor based on the current reference, iref. A PR controller is used by the internal current loop to boost the gain at 120Hz and to increase the output impedance of the double line frequency ripple. The results of this approach bring the percent of the input ripple well below the 20% and 3% requirements to 4.4% and 0.8% for current and voltage ripples, respectively. Furthermore, by adjusting the parameters of the PR controller, the magnitude of the double-line ripple on the input current and voltage can be controlled. This can be seen in the before and after figures below: Vin (28.9 Vpeak to peak) Vin (3.4 Vpeak to peak) Iin (2.3 Apeak to peak) Iin (0.22 Apeak to peak) Vout Iout Vout Iout Figure % Current Ripple and 7.2% Voltage Ripple Without FEEC PR Control Figure % Current Ripple and 0.8% Voltage Ripple With FEEC PR Control b) Miniaturization of components for DC/AC conversion Two-stage design By controlling input ripple in the dc/dc stage, less double-line frequency energy storage is required. Meanwhile, the dc bus voltage is stepped down to 365V, allowing the use of a smaller 400-V rated capacitor at Cbus. Furthermore, the use of a planar core along with the printed circuit board (PCB) based winding in the dc/dc stage allows significant size and loss reduction for the dc/dc stage. A comparison between a capacitor-only solution and FEEC s dc/dc stage can be seen in the Table 1. Table 1. Comparison between capacitor-only and FEEC two-stage solution Capacitor-only FEEC DC/DC stage Energy Storage Required >1.5mF 0.47mF Capacitor Voltage Rating >450V 400V Effectiveness Reduces input voltage and current ripples to the required 3% and 20% Reduces input voltage and current ripples to less than 0.8% and 4.4% Energy Buffering Volume* 20.5 in in 3 *Capacitor-only assumption uses (3) 680uF 500V rated electrolytic capacitors with diameter and height

3 Advantage of wide-bandgap devices Wide-bandgap semiconductors, like Transphorm s TPH3002LD and Cree s C3D1P7060Q employed in the dc/dc stage and GaN Systems GS66516T in the dc/ac stage, now allow for higher power density, greater efficiency, and faster switching than conventional silicon devices. FEEC s high switching frequency of 400 khz in the dc/dc stage and 60 khz in the dc/ac stage reduces the filter size without sacrificing efficiency. Selection of topology and modulation Careful selection of the inverter topology and modulation method proved crucial in minimizing output filter size, achieving high efficiency, and minimizing EMI noise. First, a successful highdensity inverter topology must fully utilize its magnetic components to reduce the harmonic filter size. Furthermore, compared with a 2-level output voltage type bipolar modulation, a 3-level output minimizes the ripple current magnitude seen by the output filter, thus reducing the size of both harmonic and DM filters. Ultimately, it was found the adopted ac switch clamped inverter meets these requirements, has reactive power capability, and minimizes EMI filter size, making it the optimal choice for FEEC s little box design. System-level mechanical optimization In FEEC s little box design, the copper case is also utilized as the heat sink. The dc/ac stage is mounted to the case floor while the dc/dc stage is mounted to the top lid further reducing the volume when compared with separate heat sinks. In addition, CAD software is used to arrange the physical placement of every component and thermal performance, ensuring space is efficiently utilized while keeping temperature low. c) Electromagnetic compliance Topology selection The most successful EMI management strategy is to avoid noise creation at its source. The selected circuit produces a three-level voltage at the inverter output, minimizing DM noise. Symmetrical output inductor design and synchronized switching of the power devices, CM noise is theoretically eliminated. Attenuation of EMI emissions Yet, it is impossible to achieve zero CM noise in real implementations due to parasitic components, and the remaining EMC noise must be attenuated by filter design. Concurrently, leakage current requirements must be considered. A two-stage EMC filter is designed, as seen in Figure 7, which sharply filters high frequency noise while Figure 6. AutoCAD Rendering of FEEC Little Box Figure 7. Two-stage EMC filter shrinking the size of individual passive components. DM noise is managed by the harmonic filter at the inverter s output as well as the leakage inductance of the two common-mode chokes and the capacitor across them. CM noise is handled by two common-mode chokes and two Y-type capacitors between each output terminal and earth ground. Leakage current is limited by the first stage CM choke. FEEC s conductive EMC results alongside FEEC class B requirements can be seen in Figure 8. Leakage current results are displayed in Figure 9. To eliminate radiated emissions, several measures are implemented: 1) shorten the loop areas on the PCB layout, including the main power path, the auxiliary power supply paths and current loops for high frequency ICs; 3) utilized enclosure and PCB ground plane as shield; and 4) added a copper shield over the DSP area. The unit will be tested by our collaborators at National Electromagnetic Effects Research Laboratory in Singapore in the near future.

4 Quasi-Peak FCC Limit Average FCC Limit Output Voltage Output Current Leakage Current Figure 8. FEEC Little Box Average and Peak EMC with FCC Class B Requirements d) Thermal management High-efficiency system design FEEC s main thermal management strategy is to minimize heat generated by the system. This places a special emphasis on efficiency in design: 1) wide-bandgap devices ensure low switching and conduction loss; 2) high switching frequency reduces the current ripple on the output inductor, minimizing both core and conduction loss; and 3) optimal design of magnetic components reduces loss among passive components. Thus, at 75% load condition, the dc/dc stage achieves a peak efficiency of 99.62% and the dc/ac stage achieves a peak efficiency of 98.97%. The overall system efficiency across various power levels can be seen in Figure 10. Thermal management The heat is managed by both the case itself and forced-air cooling. 1) FEEC s little box prototype minimizes volume by having the copper walls of the case double as heat sinks for both the dc/dc and dc/ac stages. This provides a larger heat sink area than even a traditional heat sink and improves access to air flow for direct cooling. 2) Ten 0.1W micro-fans force air across fins on one side wall to cool the box itself, while also increasing air circulation within the box. Openings in the lid on the opposite allow for the heated air to escape upward, taking advantage of natural convection. 3) As power density increases, available surface area for thermal dissipation diminishes. To counteract this, surface area is maximized as volume decreases by keeping one dimension of the enclosure larger than the other two. Figure 12 shows the measured peak temperature and thermal image of the entire box after more than one-hour testing until temperature reaches steady state. Under 30 C ambient temperature condition, the maximum case temperature is 53.6 C. References Figure 9. Leakage Current at Full Power is 25.8mARMS, less than 50mA requirement Figure 10. FEEC System Efficiency Figure 11. Air-flow Design of FEEC Little Box Figure 12. Steady-state temperature profile. 1. J. Holtz, Selbstgefuhrte wechselrichter mit treppenformiger ausgangsspannung fur grose leistung und hohe frequenz, Siemens Forschungsund Entwicklungsberichte, vol. 6, no. 3, pp , H. Schmidt, C. Siedle, and J. Ketterer, DC/AC converter to convert direct electric voltage into alternating voltage or into alternating current, U.S. Patent B2, May J.-S. Lai and C. Liu, Multiphase soft switched DC/DC converter and active control technique for fuel cell ripple current elimination, U.S. Patent #7,518, B. Gu, J. Dominic, and J.-S. Lai, "Modeling and control of a high boost ratio PV module dc-dc converter with double grid line ripple rejection," in Proc. of IEEE COMPEL Workshop, Salt Lake City, Utah, June 2013, pp. 1 4.

5 Technical Approach: Biographic Information Team Name: Future Energy Electronics Center Registration Code: 545-W31m Dr. Jih-Sheng Lai received M.S. and Ph.D. degrees in electrical engineering from the University of Tennessee, Knoxville, in 1985 and In 1989, he joined the Electric Power Research Institute (EPRI) Power Electronics Applications Center (PEAC), From 1993, he worked with the Oak Ridge National Laboratory as the Power Electronics Lead Scientist. He joined Virginia Tech in Currently he is James. S. Tucker Endowed Professor and Director of Future Energy Electronics Center (FEEC). During the academic year of 2015, he is taking the research leave to join Nanyang Technological University in Singapore as a Visiting Professor. He published more than 330 refereed technical papers and 2 books. He received 24 U.S. patents in the area of high power electronics and their applications. He received Technical Achievement Award in Lockheed Martin Award Night and eight best paper awards from International conferences. His student teams won the First Prize Award in Texas Instruments Analog Design Competition in 2011 and the Grand Prize Award from International Future Energy Challenge (IFEC) on power electronics design competition in Dr. Lai is an IEEE Fellow. He chaired the EPRI Power Device and Component Workshop in He was the founding chair of the 2001 IEEE International Future Energy Challenge for Inverter Competition, General Chairs of IEEE Workshop on Computers in Power Electronics (COMPEL 2000), IEEE Applied Power Electronics Conference and Exposition (APEC 2005), 2008 NSF Workshop on Power Electronics for Alternate Energy and Distributed Generation. Lanhua Zhang received his B.S. degree and M.S. degree both in electrical engineering from Shandong University, China, in 2009 and 2012, respectively. Since 2012, he has been a Graduate Research Assistant and Ph.D. student in Future Energy Electronics Center (FEEC), Virginia Tech, Blacksburg, VA. His research interests include soft-switching inverters for renewable energy applications, high-efficient DC/DC converters, high power density EV chargers, and non-linear current control strategies. Xiaonan Zhao received her B.S. of Electrical Engineering from Beijing Jiaotong University in China in She is currently pursuing a M.S. of Electrical Engineering at the Virginia Polytechnic Institute and State University serving as a Graduate Research Assistant at the Future Energy Electronics Center (FEEC). Her areas of interest include renewable energy applications and high-efficient DC-DC converters.

6 Rachael Born received a B.S. of Environmental Physics in 2012 from the College of William of Mary and a B.S. of Electrical Engineering at Virginia Tech in She is currently pursuing a M.S. of Electrical Engineering at the Virginia Polytechnic Institute and State University serving as a Graduate Research Assistant at the Future Energy Electronics Center (FEEC). Her areas of interest include renewable energy applications, additive manufacturing and system design. Chung-Yi Lin was born in Chia-Yi, Taiwan, in He received the B.E. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 2006, where he is currently working toward the Ph.D. degree. His research interests include the design and analysis of the zero-voltage-switching dc dc converters, and power factor correction techniques. He joined and became the assistant Manager in the power department of FLEXTRONICS starting in January Since May 2014, he has been with Virginia Tech Future Energy Electronics Center (FEEC) as a Post Doctoral Fellow. and motor drives. Ming-Chang Chou was born in Tainan, Taiwan, R.O.C., in He received the B.S. and M.S. degree in mechanical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1998 and 2000, respectively. From 2001 to 2004, he was an associate researcher in Mechanical Industrial Research Laboratory, Industrial Technology Research Institute, Hsinchu, Taiwan, R.O.C. and was promoted to be a researcher in He received the Ph.D. degree in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan, R.O.C., in Dr. Chou is currently a project manager in Rhymebus Corporation, Taichung, Taiwan, R.O.C.. His research interests are power electronics Shu-Shuo Chang was born in Taichung City, Taiwan. He received the B.Eng. degree in mechanical engineering from National Chung Hsing University, Taichung, Taiwan, in 2008, the M.S. degree in mechanical engineering from National Cheng Kung University, Tainan, Taiwan, in He has worked as a marine propulsion engineer at Jong Shyn Shipbuilding, Kaohsiung, Taiwan. He is currently an assistant engineer at Rhymebus Co., Taichung, Taiwan. He specializes in FEM analysis; system heat balance analysis; and mechanical design.

7 Kye Yak See (SM 02) received the B. Eng degree (1st Class Hons) from the National University of Singapore in 1986 and the Ph.D degree from Imperial College London in Between 1986 and 1991, he was with Singapore Technologies Electronics as a Senior Engineer. From 1991 to 1994, he held the position of Lead Design Engineer in ASTEC Custom Power, Singapore. After receiving his Ph.D degree in 1997, he joined Nanyang Technological University (NTU) as a faculty member. He is currently an Associate Professor in the School of Electrical and Electronic Engineering, NTU. He also holds concurrent appointment as the Director of Electromagnetic Effects Research Laboratory (EMERL). His research interests are power and signal integrity, power electronics EMC and EMC measurement. He was the founding chair of the IEEE EMC Chapter and currently the chair of the IEEE AES and GRS Joint Chapter in Singapore. He was the Organizing Committee Chairs for the 2006 EMC Zurich Symposium and 2008 Asia Pacific EMC Conference in Singapore. Since January 2012, he has been the Technical Editor of the IEEE EMC Magazine.