MachXO2 Pico Development Kit User s Guide

Transcription

1 MachXO Pico Development Kit July Revision: EB_.9

2 Introduction Thank you for choosing the Lattice Semiconductor MachXO Pico Development Kit. MachXO Pico Development Kit This guide describes how to begin using the MachXO Pico Development Kit, an easy-to-use platform for rapidly prototyping system control designs using MachXO PLDs. Along with the evaluation board and accessories, this kit includes the pre-loaded Pico SoC Demo (Environment Scanning Demonstration Design) that demonstrates board diagnostic functions including ultra-low power, LCD driver, I/O control, current measuring, time stamps and data logging to non-volatile memory using the -bit LatticeMico microcontroller. The contents of this user s guide include demo operation, top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, switches, a complete set of schematics and the bill of materials for the MachXO Pico Evaluation Board. Note: Static electricity can severely shorten the lifespan of electronic components. See the MachXO Pico Development Kit QuickSTART Guide for handling and storage tips. Features The MachXO Pico Development Kit includes: MachXO Pico Evaluation Board The MachXO Pico Evaluation Board features the following on-board components and circuits: MachXO LCMXO-ZE PLD device in a -ball csbga package. The board is designed for density migration, allowing a lower density MachXO device to be assembled on the board. - Part number LCMXO-ZE-P-EVN is populated with the R silicon. Part number LCMXO-ZE- P-EVN is populated with the Standard silicon. The demos have been targeted for a specific version of silicon and are not interchangeable. For more information on the R to Standard migration refer to AN, Designing for Migration from MachXO--R to Standard (Non-R) Devices - Mbit SPI Flash memory Current sensor circuits using Delta-Sigma ADC LCD driven with PWM analog output circuitry Expansion header for JTAG, SPI, I C and PLD I/Os capacitive touch sense buttons Standard USB cable for device programming RS-/USB and JTAG/USB interface RoHS-compliant packaging and process USB or battery powered Pre-loaded Reference Designs and Demo The kit includes a pre-loaded Pico SoC Demo design that integrates several Lattice reference designs including: the LatticeMico microcontroller, master WISHBONE bus controller, soft delta-sigma ADC, SPI master controller, UART peripheral, Embeded Block RAM and additional control functions. USB connector Cable A mini B USB port provides power, a communication and debug port via a USB-to-RS- physical channel and programming interface to the MachXO JTAG port. Battery A coin battery can provides an alternate source of power. QuickSTART Guide Provides information on connecting the MachXO Pico Evaluation Board, installing Windows hardware drivers, and running the Pico SoC Demo. Figure shows the top side of the MachXO Pico Evaluation Board with comments on the specific features that are designed in the board.

3 MachXO Pico Development Kit Figure. MachXO Pico Evaluation Board, Top Side Push-button x GPIO Header LCD Screen Capacitive Touch Sense Buttons MachXO- ZE SPI Flash Memory IC Temperature Sensor USB Interface Socket Coin Battery Slot MachXO Device This board features a MachXO PLD with a.v core supply. The PLD is packaged in a -ball csbga which provides a migration path to devices ranging from LUTs to LUTs. A complete description of this device can be found in the MachXO Family Handbook. Software Requirements You should install the following software before you begin developing designs for the evaluation board: Lattice Diamond. (or higher) ispvm System.9. (or higher) Demonstration Design Lattice provides the Pico SoC Demo design programmed in the board. The design utilizes the MachXO in the context of low power applications. The Pico SoC Demo illustrates the use of the LatticeMico microcontroller, associated peripherals and firmware to provide a low power system featuring voltage/current measurement, data logging to nonvolatile memory, I/O control, embedded block RAM utilization, UART communication, capacitive touch sense buttons and a LCD controller. The LatticeMico executable program initializes the peripherals that are embedded in the SoC design. During initialization, the LatticeMico uploads the user menu on the Terminal of a PC. Users interact with LatticeMico and the board through the Terminal of a PC or through the capacitive touch sense buttons.

4 MachXO Pico Development Kit Figure. Pico SoC Demo Block Diagram MachXO Pico Evaluation Board MachXO-ZE PC UART Capacitive Touch Sense Buttons LatticeMico Microcontroller LCD Soft ADC Master SPI Embedded Block RAM Master I C Analog Signal SPI Flash I C Temp Sensor Power management is handled in two phases by the MachXO Pico Evaluation Board system:. MachXO Function After the reset is de-asserted, LatticeMico initializes the peripherals embedded in the MachXO device and uploads the user menu onto the HyperTerminal window of a PC. Figure. HyperTerminal User Menu. Users interact with LatticeMico microcontroller and the board by selecting the available options in the HyperTerminal menu. The available options are: m This option re-displays the main menu anytime during the demonstration. PICO is displayed on the LCD screen. i This option measures the Icc using a Delta Sigma. The result is displayed to the terminal and the LCD. Board button performs the same function but results are only displayed to the LCD. o This option measures Icco using Delta Sigma. The result is displayed to the terminal and the LCD. Pressing board button performs the same function but results are only displayed to the LCD.

5 MachXO Pico Development Kit s This option reads the device ID of the SPI Flash on the board. The results are displayed to the terminal and the LCD. 't' - This option reads the IC temperature sensor on the board. The result is displayed to the Terminal and to the LCD. Button on the board performs the same function but the result is only displayed on the LCD 'r' This option samples the capacitive touch buttons on the board and displays the data in the terminal. "-9" - These values will echoed to the terminal and displayed on the LCD 'l' - This option will read the Icc, Icco, and Temperature and log it to the SPI flash memory. The WRITE page pointer will increment when 'l' is pressed. The initial value of the page pointer after power up is a. Button on the board performs the same function the LCD will display 'd' - This option will read the data from the SPI Flash device and display to to the Terminal window. The READ page pointer will increment when 'd' is pressed. The intial value of the page pointer after a power up is. 'c' - This option will clear (reset) the WRITE and READ page pointers 'e' - This selection will perform a bulk-erase of the Flash memory in the SPI Flash device and will clear (reset) the WRITE and READ page pointers. Setting up the Board Drivers and Firmware Before you begin, you will need to obtain the necessary hardware drivers for Windows from the Lattice web site.. Browse to and locate the hardware device drivers for the USB interface.. Download the ZIP file to your system and unzip it to a location on your PC. Linux Support: The USB interface drivers for the evaluation board are included in Linux kernel.. or greater, including distributions compatible with Lattice Diamond design software (Red Hat Enterprise v., v. or Novell SUSE Enterprise v.). The Pico SoC Demo is preprogrammed into the MachXO Pico Evaluation Board, however over time it is likely that your board will be modified. To download the demo source files and reprogram the MachXO Pico Evaluation Board:. Download the demo appliction source code from Use.\Environment_Scanning_demo\project\impl\Environment_Scanning_demo_impl.jed to restore the Environment Scanning demonstration design. Connecting to the MachXO Pico Evaluation Board. Connect the evaluation board to your PC using the USB cable provided. The USB connector on the board includes reference designator J. Once the connection is made, a blue LED with reference designator D will illuminate.. If you are prompted Windows may connect to Windows Update, select No, not this time from available options and click Next to proceed with the installation.. Choose the Install from specific location (Advanced) option and click Next.. Select Search for the best driver in these locations and click the Browse button to browse to the Windows driver folder created earlier. Select the CDM.. WHQL Certified folder and click OK.. Click Next. A screen will display as Windows copies the required driver files. Windows will display a message indicating that the installation was successful.

6 Programming the MachXO MachXO Pico Development Kit Using ispvm System software, users can scan and perform JTAG operations, including programming, with the MachXO device. Setting Up Windows HyperTerminal You will use a terminal program to communicate with the evaluation board. The following instructions describe the Windows HyperTerminal program which is found on most Windows PCs. You may use another terminal program but setup will be somewhat different. Windows does not include HyperTerminal. Tera Term has been verified to work with Windows. For Linux, Minicom is a good alternative. Note: This step uses the procedure for Windows XP users. Steps may vary slightly if using another Windows version.. From the Start menu, select Control Panel > System. The System Properties dialog appears.. Select the Hardware tab and click Device Manager. The Device Manager dialog appears. Figure. Device Manager COM Port. Expand the Ports (COM & LPT) entry and note the COM port number for the USB Serial Port.. From the Start menu, select Programs > Accessories > Communications > HyperTerminal. The HyperTerminal application and a Connection Description dialog appear.

7 MachXO Pico Development Kit Figure. New Connection COM Port. Specify a Name and Icon for the new connection. Click OK. The Connect To dialog appears.. Select the COM port identified in Step from the Connect using: list. Click OK. Figure. Selecting the COM Port. The COMn Properties dialog appears where n is the COM port selected from the list.. Select the following Port Settings and click OK. Bits per second: Data bits: Parity: None Stop bits: Flow control: None Figure. COM Port Properties

8 MachXO Pico Development Kit 9. The HyperTerminal window appears.. From the MachXO Pico Evaluation Board, press the reset push-button with reference designator S. The Pico SoC demo main menu appears. Setting Up Linux Minicom Minicom is a terminal program found with most Linux distributions. It can be used to communicate with the MachXO Pico Evaluation Board. To setup Minicom:. Check active serial ports: #dmesg grep tty Note the tty label assigned to the USB port. From a command prompt, start Minicom: #minicom s The configuration menu appears.. Highlight Serial port setup and press Enter. Serial port settings appear.. Press A (Serial Device). Specify the active serial device noted in Step and press Enter.. Press E (Bps/Par/Bits). Specify, None, and press Enter.. Press F (Hardware Flow Control). Specify None and press Enter.. Press Esc. The configuration menu appears.. Select Save setup as dfl. Minicom saves the port setup as the new default. 9. Select Exit. The Minicom interface appears.. From the evaluation board, press the S push-button (GSR). The Pico SoC demo main menu appears. Ordering Information Description Ordering Part Number China RoHS Environment-Friendly Use Period (EFUP) MachXO Pico Development Kit LCMXO-ZE-P-EVN Technical Support Assistance Hotline: --LATTICE (North America) +--- (Outside North America) techsupport@latticesemi.com Internet:

9 MachXO Pico Development Kit Revision History Date Version Change Summary February. Initial release. April. Updated Pico Evaluation Board Top Side diagram, Pico SoC Demo block diagram, HyperTerminal User Manual information, Appendix A and Appendix B. June. Added Appendix C. July. Updated Features list with information on migration from MachXO- -R to Standard (non-r) devices. July. Added limitations section to Appendix C. December. Added Appendix D. February. Updated document with new corporate logo. June. Added Appendix D, Dual Boot Demonstration. Updated Appendix E, Limitations. June. Added MachXO Pico Evaluation Board I C Bus Power Enable diagram to Appendix D. July.9 Appendix D figure title changed from MachXO Pico Evaluation Board I C Bus Power Enable to MachXO Pico Evaluation Board SPI/I C Bus Power Enable. Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 9

10 Appendix A. Schematic Figure. USB V, MachXO Power Rails,.V Battery,.V Rail and Current Monitors MachXO Pico Development Kit +V +V +.V +.VorBat R +.V_USB_CABLE -> +.V Rail +.V_USB D +V_USB BT Q Q Q D IRLMLPbF IRF IRLMLPbF SM/R_ Vbat+ D U V- IN OUT Vbat+ R TAB.k C +V Batt_Cell_Holder R R SM/R_ uf R9 C M.uF R SM/C_ NCP C k SM/C_ CR.uF SM/R_ R k k R k k Battery Clip/ SM/R_ Optional Charger [pg] PWR_ENABLEb D Blue SOT-_checkpins SM/R_ R9 SM/D_ k NSRPTG USB plugged in => +V is High, Q=ON, Q=OFF USB un plugged => +V is Low, Q=OFF, Q=ON C C Core Current +.V +.V or Bat -> +.V Rail +.VorBat +.V U R9 M SM/R_ Q IRLMLPbF TP VIN VOUT TP-TP are mil free Via's R % C Locate TP & TP very close to R C uf % Locate TP & TP very close to R uf C SM/R_ TP TP B uf B MCPT-E/CB TP VCC_CORE To U9 sense for current Thin signal traces Direct path from R to U VCCIO_EXT I/O Current R SM/R_ VCC_IO To U9 sense for current Thin signal traces or non load bearing copper pour Direct path from R to U A A Lattice Semiconductor Applications techsupport@latticesemi.com Phone () - -or- () LATTICE Title USB V, XO Power Rails.V Batt,.V Rail and Current Monitors Size Project Schematic Rev A B MACHXO Pico Board Board Rev E Date: Friday, March, Sheet of +

11 MachXO Pico Development Kit Figure 9. Current Sense Amplifiers, Power Enable Mux PWR_AMP R C LMP.uF.% UA Delta Sig Icc Measurement D D +.VorBat R R A DSInVcc [pg] R R k k R C C.% k.uf.uf.% % +.V % R U DSOutVcc [pg] VCC_CORE S VCC Vrefin S R9 R R C VCCIO_EXT D k pf S D DSVrefVcc [pg].% S D VCC_IO D R k S 9 S SEL % SEL % S S PWR_AMP C STG9QTR C R9 LMP.% UB Delta Sig Icco Measurement [pg] EnAMP R R High = Powered (S) B Low = Disabled (S) DSInVcco [pg] R R k k R C9.% k.uf.% % % R9 DSOutVcco [pg] Vrefin R9 R9 R C k pf DSVrefVcco [pg].% R9 k % % B B Power Supply Enable Mux +.VorBat C.uF PWR_AMP VCC_IO +.VorBat Vrefin U S VCC S PWR_ICSPI D S D A S D A D R9 S R9 Lattice Semiconductor Applications 9 S SEL EnAMP [pg] techsupport@latticesemi.com SEL EnICSPI [pg] Phone () - -or- () LATTICE S Title S High = Powered (S) Current Sense Amplifiers, Power Enable Mux Low = Disabled (S) STG9QTR Size Project Schematic Rev A B MACHXO Pico Board Board Rev E Date: Friday, March, Sheet of

12 MachXO Pico Development Kit Figure. USB to JTAG and I C for the MachXO +.V L ohm ma ohm ma +.V USB_SCL [pg,] C C C9.uF.uF.uF USB_SDA [pg,] +V_USB R C C.k U D VCCFT.uF.uF D R VCC S USB_TCK [pg] R S R D R D S USB_T [pg] D S C C D S USB_TDO [pg].uf.uf +.V U SEL S 9 L FTHL SEL Ferrite_bead S USB_TMS [pg] SM/R_ S USB Connection STG9QTR C ADBUS R nf VREGIN ADBUS J USB_MINI_B ADBUS 9 VREGOUT ADBUS 9 VCC SM/C_ ADBUS ADBUS R FT Controlled D- DM ADBUS High = JTAG D+ DP ADBUS R Low = IC C ACBUS C NC RESET# ACBUS ACBUS R9 SHLD_Debug ACBUS 9 nf.k CASE REF ACBUS R C CASE ACBUS k ACBUS R BDBUS [pg] TYPE_B CASE CASE 9 ACBUS R k EECS R BDBUS [pg] MH EECLK BDBUS MH EEDATA BDBUS 9 R BDBUS [pg] BDBUS BDBUS R BDBUS [pg] +.V OSCI BDBUS BDBUS R BDBUS [pg] X BDBUS BDBUS R BDBUS [pg] OSCO BCBUS BDBUS [pg] R R BCBUS R k C G G C BCBUS BDBUS [pg] R k SM/R_ pf pf MHZ TEST BCBUS k +.V SM/R_ BCBUS U SM/R_ BCBUS B FT High-Speed USB B EECS BCBUS VCC CS EESK BCBUS 9 NC SK EEDATA R FTH PWREN# PWR_ENABLEb [pg].uf C ORG N DOUT [pg] USB_MHZ SUSPEND# M9C-WMNTP R.k SOIC- M9C-WMNTP Manuf:ST Micro Digi-Key Part Number 9-9--ND +.V +.VorBat A VPHY VPLL VCORE VCORE VCORE 9 VCCIO VCCIO VCCIO VCCIO A A Lattice Semiconductor Applications techsupport@latticesemi.com Phone () - -or- () LATTICE Title USB to JTAG and IC for the XO Size Project Schematic Rev A B MACHXO Pico Board Board Rev E Date: Friday, March, Sheet of

13 MachXO Pico Development Kit Figure. MachXO Banks -, LCD, I C Temperature UA A Bank PWR_ICSPI PT9A PTA C9 B PT9B PTB A9 U Char LCD D D A PTA PTC/JTAGENB B9 C LCD_COM_LP LCD LP PTB PTD/PROGRAMN C PROTO_C [pg] LCD_COM_LP COM D,E,G,F LCD LP R R LCD_COM_LP COM DP,C,B,A R B PTA PTA A.k.k LCD_COM_LP COM k C LCD LP PTB PTB C COM D,E,G,F LCD LP [pg] USB_MHZ A Tmp_IC_ALERT PTA/PCLKT_ PTC A LCD-SMKR DP,C,B,A B LCD_9_LP PTB/PCLKC_ PTD B D,E,G,F 9 LCD LP DP,C,B,A [pg,] USB_SCL C PTC/SCL/IO/PCLKT_ PTA C LCD LP [pg,] USB_SDA B PTD/SDA/IO/PCLKC_ PTB A D,E,G,F LCD LP [pg] XO_TDO A TDO PTC/INITN B COL,C,B,A PROTO_B [pg] [pg] XO_T B T PTD/DONE A PROTO_A [pg] [pg] XO_TCK B TCK [pg] XO_TMS A TMS LCMXO--CSBGA LowPass Filter LCD_COM LCD_COM LCD_ LCD_ C C UB R R R R.9k.9k.9k.9k LCD_COM B Bank LCD_ LCD_COM PRA PRA J C LCD_ LCD_COM_LP LCD_COM_LP LCD LP LCD LP PRB PRB J LCD_COM C LCD_ C9 C LCD_COM PRC PRC J C C9 D LCD_.uF.uF PRD PRD K.uF.uF E LCD_9 PRA PR9A K E LCD_ PRB PR9B K LCD_COM LCD_ LCD_ LCD_ E LCD_ PRA PR9C L F LCD_ R R R PRB PR9D M R.9k.9k.9k.9k F PRC PRA M F LCD_COM_LP LCD LP LCD LP LCD LP PRD PRB M G C C C PRA PRC N C G.uF.uF.uF PRB PRD N.uF G PRC/PCLKT_ H PRD/PCLKC_ LCD_COM LCD_ LCD_9 LCD_ B B R R R R LCMXO--CSBGA.9k.9k.9k.9k LCD_COM_LP LCD LP LCD_9_LP LCD LP C C C C.uF.uF.uF.uF Temperature Sensor Slave Addr PWR_ICSPI C PWR_ICSPI _uf U R Tmp_IC_ALERT R VCC ALERT A A [pg,] USB_SCL R SCL ADD Lattice Semiconductor Applications [pg,] USB_SDA SDA techsupport@latticesemi.com Phone () - -or- () LATTICE TMP Title XO Bank -, LCD, IC Temp Size Project Schematic Rev A B MACHXO Pico Board Board Rev E Date: Friday, March, Sheet of

14 MachXO Pico Development Kit Figure. MachXO Banks -, Capacitor Pads, Expansion Header, SPI UC [pg] EnAMP P Bank PROTO_M PBA PBA/PCLKT_ M [pg] EnICSPI N PROTO_N PBB PBB/PCLKC_ N XO_SPI_CS P PBC/CSSPIN PBA P DSVrefVcc [pg] M DSInVcc [pg] +.VorBat PBD PBB M PushBtn VCCIO_EXT D PBC P9 R9 N PBA DSOutVcc [pg] U D P PBB PBD N9 DSOutVcco [pg] Header XO_SPI_CLK XO_SPI_OUT M N N M N P P N PBC/MCLK/CCLK PBD/SO/SPISO/IO PB9C PB9D PB9A/PCLKT_ PB9B/PCLKC_ PBC PBD LCMXO--CSBGA UD PBA PBB PBC M PBD P PBA PBB M9 N M P PBC/SN N PBD/SI/SISPI/IO P DSVrefVcco [pg] DSInVcco [pg] CapBtn CapBtn CapBtn CapBtn XO_SPI_SN XO_SPI_IN [pg] USB_T [pg] USB_TDO [pg] USB_TCK [pg] USB_TMS [pg,] USB_SDA [pg,] USB_SCL [pg] PROTO_B [pg] PROTO_A [pg] PROTO_C XO_SPI_SN XO_SPI_CS XO_SPI_CLK XO_SPI_IN XO_SPI_OUT R R R R R PROTO_K PROTO_K PROTO_M PROTO_N PROTO_B PROTO_B PROTO_C PROTO_C PROTO_C PROTO_D XO_T [pg] XO_TDO [pg] XO_TCK [pg] XO_TMS [pg] R k H Bank PROTO_B PLC PLA/L_GPLLT_FB B H PROTO_B HEADER X PLD PLB/L_GPLLC_FB B C J PROTO_C PLA PLC/L_GPLLT_IN C C J PROTO_C PLB PLD/L_GPLLC_IN C PROTO_C MBit SPI J PLC PLA/PCLKT_ C K PROTO_D (Refer to Appendix D. Limitations) PLD PLB/PCLKC_ D PROTO_K K PWR_ICSPI BDBUS [pg] PROTO_K PL9A/PCLKT_ PLC E K PL9B/PCLKC_ PLD E BDBUS [pg] Package: SOIC (WIDE) U9 R PLA E BDBUS [pg] R L XO_SPI_CS PLB PLB F BDBUS [pg] Vcc S XO_SPI_CLK Reset C R XO_SPI_IN BDBUS [pg] W D R9 M PLC PLC F XO_SPI_OUT BDBUS [pg] Vss Q M PLD PLD F PLA/PCLKT_ G BDBUS [pg] ATDFA-SH-B PLB/PCLKC_ H BDBUS [pg] Capacitive Touch Pads Package: UDFN LCMXO--CSBGA U XO_SPI_CS VCCIO_EXT VCCIO_EXT Vcc S XO_SPI_CLK C Reset C XO_SPI_IN B _uf W D XO_SPI_OUT B Vss Q R R9 k k U U GSR/Wake from Standby ATDFA-MH VCCIO_EXT CapBtn CapBtn CapBtn CapBtn C C.uF CapTouch.uF CapTouch R k PushBtn VCCIO_EXT VCCIO_EXT S C GlobalReset.uF R9 R9 k k A U U A Lattice Semiconductor Applications techsupport@latticesemi.com CapBtn CapBtn PCB Footprint = SMT_SW CapBtn CapBtn Phone () - -or- () LATTICE Part Number:EVQ QKW Title C9 C Panasonic SMD XO Bank -, Cap Pads, Expansion Header, SPI.uF CapTouch.uF CapTouch Size Project Schematic Rev A B MACHXO Pico Board Board Rev E Date: Friday, March, Sheet of

15 MachXO Pico Development Kit Figure. MachXO Power G Board Logos Board Mounting Holes G G Lattice Logo WEEE E-Friendly MH MH MH9 MH D D M_HOLE M_HOLE M_HOLE M_HOLE IW_MNT IW_MNT IW_MNT IW_MNT VCC_CORE VCC_CORE UE VCC_IO C C N VCC NC C P VCC A C C VCC VCCIO C A.uF.uF VCC VCCIO A VCCIO B L VCCIO L G VCCIO H D VCCIO D L VCC_IO P VCCIO N P VCCIO M A VCCIO P B D VCCIO L H C C VCCIO D C C.uF.uF VCCIO G.uF.uF LCMXO--CSBGA B B A A Lattice Semiconductor Applications techsupport@latticesemi.com Phone () - -or- () LATTICE Title XO Power Size Project Schematic Rev A B MACHXO Pico Board Board Rev E Date: Friday, March, Sheet of

16 MachXO Pico Development Kit Appendix B. Bill of Materials Item Quantity Reference Part Footprint Populate Vendor Part Number Description C,C _uf SM/C_ Panasonic ECJ-VBCK.uF surface mount cap C,C,C uf SM/C_ Panasonic ECJ-YBAK uf surface mount cap C,C nf SM/C_ Panasonic ECG ECJ-VBCK nf SMC J USB_MINI_B TYPE_B Hirose UX-MB-ST USBType-BMiniConnector R,R,R,R,R,R,R,R,R,R,R,R,R,R,R,R,R,R,R, R,R,R9,R,R,R, R,R,R9,R,R,R, R9,R9,R9,R9 SM/R_ Panasonic ECG ERJ-GEYRV Resistor. SMD R,R,R,R9,R9 k SM/R_ Vishay/Dale CRCWKFKEA Resistor k SMD R,R,R,R,R,R9,R, R k SM/R_ Vishay/Dale CRCWKFKEA K SMT resistor R9 k SM/R_ Vishay/Dale CRCWKFKEA K SMT resistor 9 U M9C-WMNTP SOIC- STMicroelectronics M9C-WMNTP IC K EEPROM -SOIC U TMP SM/SOT_ TI TMPNA/ IC TEMP SENSOR G SOT-- R9 M SM/R_ PanasonicECG ERJ-GEYJV RES.M/W% R M SM/R_ PanasonicECG ERJ-GEYJV RES.M/W% U ATDFA-MH UDFN Atmel ATDFA-MH IC FLASH MBIT MHZ SOIC MH9,MH,MH,MH M_HOLE IW_MNT M SJ- (BLACK) BUMPON HEMISPHERE.X. BLACK R,R,R,R,R,R k SM/R_ Susumu Co Ltd RGP--B-T RES.K OHM /W.% SMD BT Batt_Cell_Holder BA_Battery_ Holder Linx Technologies Inc BAT-HLD- HOLDER BATTERY MM COIN CR C,C9,C,C,C,C,C.uF SM/C_ TDK Corporation CXREK CAP CER.UF V XR,C,C,C,C,C,C %,C,C,C C,C,C9,C.uF SM/C_ TDK Corporation CXREK CAP CER.UF V XR % 9 C,C9,C,C,C,C, C,C,C9,C,C,C.uF SM/C_ TDK Corporation CXRHK CAP CER PF V XR % C.uF SM/C_ TDK Corporation CXRAK CAP CER.UF V XR C.uF SM/C_ AVX Corporation TAJAKRNJ CAP TANTALUM.UF V % SMD C uf SM/C_ Nichicon TAJAKRNJ CAP TANTALUM UF.V % SMD D Blue SM/D_ Lite-On Inc LTST-C9TBKT LED NM BLUE CLEAR SMD L Ferrite_bead SM/R_ Laird-Signal Integrity Products MIJR- FERRITE A OHM SMD U MCPT-E/CB SOT-A- Microchip Technology MCPT-E/CB IC REG LDO.V MA SOT-A R,R,R k SM/R_ Panasonic - ECG ERJ-GEYJV RES K OHM /W % SMD R,R9,R9,R9 k SM/R_ Panasonic - ECG ERJ-GEYJV RES K OHM /W % SMD R.k SM/R_ Panasonic - ECG ERJ-EKFV RES.K OHM /W % SMD 9 R,R.k SM/R_ Panasonic - ECG ERJ-GEYJV RES.K OHM /W % SMD R9,R,R,R SM/R_ Vishay/Dale TNPW9R9BEEA RES 9.9 OHM /W.% R,R9 SM/R_ Panasonic - ECG ERJ-EKF99V RES 99 OHM /W % SMD

17 MachXO Pico Development Kit Item Quantity Reference Part Footprint Populate Vendor Part Number Description R9 k SM/R_ Panasonic - ECG ERA-AEBV RES K OHM /W.% SMD Q,Q,Q IRLMLPbF SM/SOT_ International Rectifier IRLMLTRPBF MOSFET P-CH V.A SOT- Q IRF SM/SOT_ International Rectifier IRLMLTRPBF MOSFET N-CH V.A SOT- S GlobalReset SMT_SW Panasonic - ECG EVQ-QKW SWITCH LT MM GF H=.MM SMD U NCP SOT- _checkpins STMicroelectronics NCPSTTG IC REG LDO A.V SOT U HEADER X Headerx Samtec Inc TLW---G-D CONN HEADER." POS DL GOLD C9,C.uF SM/C_ TDK Corporation CXRHK CAP CER PF V XR % 9 R,R SM/R_ Vishay/Dale CRCWRFKEA RES. OHM /W % SMD D NSRPTG SM/SOD_9 ON Semiconductor NSRPTG ODE SCHOTTKY V.A SOD-9 R SM/R_ Panasonic - ECG ERJ-GEYJV RES OHM /W % SMD R,R.k SM/R_ Rohm Semiconductor MCREZPJ RES.K OHM /W % SMD R.k SM/R_ Rohm Semiconductor MCREZPJ RES.K OHM /W % SMD U LCMXO--CSBGA CSBGA Lattice LCMXO-- CSBGA U LCD-SMKR LCD- SMKR R,R,R,R,R,R, R,R,R,R,R,R Lumex Opto/Components Inc LCD-SMKR LCMXO-- CSBGA LCD custom order from phil@duerfeldtengineering. com.9k SM/R_ Panasonic - ECG ERJ-EKF9V RES.9K OHM /W % SMD R SM/R_ Panasonic - ECG ERJ-GEYJV RES OHM /W % SMD C,C pf SM/C_ TDK Corporation CCGHJ CAP CER PF V CG % 9 C.uF SM/C_ TDK Corporation CXRJK CAP CER.UF.V XR C.uF SM/C_ TDK Corporation CXRJK CAP CER.UF.V XR L ohm ma FB Murata Electronics North America U FTHL tqfp_p_p xp_hp X MHZ crystal_p_px p BLMAGSND FERRITE CHIP OHM MA Future FTH R USB UART/FIFO TXC CORPORATION M-.MAAJ-T CRYSTAL. MHZ PF SMD U,U,U STG9QTR QFN STMicroelectronics STG9QTR IC SWITCH QUAD SPDT QFN U LMP MSOP STMicroelectronics LMPMM/NOPB IC AMP PREC R-R OUT DUAL -MSOP C,C pf SM/C_ TDK Corporation CXRHK CAP CER PF V XR % U9 ATDFA-SH-B ATDFA- SOIC- G Lattice Logo LOGO_ Atmel ATDFA-SH-B IC FLASH MBIT MHZ SOIC 9 G E-Friendly EFRIENDLY SM G WEEE WEEE_SM TP,TP,TP,TP TP LOGO_ U,U,U,U CapTouch CapTouch

18 Appendix C. SPI Programming MachXO Pico Development Kit In order to support SPI programing of the MachXO device the zero ohm resistors (R, R, R, R9) will have to be removed Once removed, the SPI programming pins can be accessed via the header U (XO_SPI_OUT, XO_SPI_IN, XO_SPI_CLK, XO_SPI_SN) Programming is supported using Diamond Programmer\ispVM or using an external processor

19 Appendix D. Dual Boot Demonstration You can demonstrate MachXO dual boot using the MachXO Pico Evaluation Board. Before you start you will need to do the following: MachXO Pico Development Kit. Create a SVF file to erase only the Configuration Flash and UFM memory. Do NOT erase the Feature Row. a. Use ispvm or Diamond Programmer to create a SVF file with the which erases the device as a baseline. b. Modify your SVF to change the following:! Shift in ISC ERASE(xE) instruction SIR T (E); SDR T (C);! Change from E= to C= no Feature Row c. For more information on the Feature Row, refer to TN, MachXO Programming and Configuration Usage Guide.. Update the MachXO Pico Demo to enable dual boot. a. Using Diamond in the Spreadsheet View, Global Preference tab set MASTER_SPI_PORT=ENABLE.. Power-on the SPI memory on the MachXO Pico Evaluation Board. a. This is a low power board and if something is not used it is powered down. This can done by shorting the south side of C and R9 by soldering or holding a probe on them as they are beside each other. For reference, the north side of the board has the header U. Shorting these components provides sets the mux U select high powering up the SPI device. b. For more information, refer to the board schematics in Appendix A. Schematic on page. Figure. MachXO Pico Evaluation Board SPI/I C Bus Power Enable R9 C R9 U Demonstrating Dual Boot. Program the MachXO device with the modified Pico Demo. a. Select the operation Flash Erase, Program, Verify. b. PICO will display on the LCD showing that it is running.. Program the SPI Flash (SPI-ATDFA) on the board with the modified Pico Demo. 9

20 MachXO Pico Development Kit a. Using ispvm or Diamond Programmer the SPI Flash can be programmed with the SPI Flash Programming option. b. As defined in TN, MachXO Programming and Configuration Usage Guide, the starting address must be x.. Reprogram the MachXO device with the modified Pico Demo as the Feature Row was erased when the SPI was programmed.. Erase the MachXO Flash (and not the Feature Row) using the modified SVF file.. Power cycle and watch dual boot in action as the MachXO loads the image from the SPI into the SRAM. a. PICO will display on the LCD showing that it is running. b. The Flash can be read back, confirming that the SRAM image came from the SPI memory.

21 Appendix E. Limitations MachXO Pico Development Kit Pin A USB_MHz clock should be an input unless R is removed to ensure FT device operation Pin B9 JTAGENB is not connected on the board It is recommended to have a K Ohm pull up on MachXO pin MCLK (signal XO_SPI_CLK)