Eight Channel ±60V, ±1.0A, Ultrasound Pulser Demoboard /V NN +3.3V CPOS LRP GND VPF +5.0V +4.0V. P-Driver VPF VNF. N-Driver -5V GND VNF LRN GND

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1 HV7DB Eight Channel ±V, ±.A, Ultrasound Pulser Demoboard General Description The HV7 is a monolithic eight channel, high-speed, high voltage, ultrasound transmitter RTZ pulser. This integrated, high performance circuit is in a single, 8x8x.9 mm, -lead QFN package. The HV7 can deliver a guaranteed ±.A source and sink current to a capacitive transducer with +/-V peak to peak voltage. It is designed for portable medical ultrasound imaging and ultrasound NDT applications. It can also be used as a high voltage driver for other piezoelectric or capacitive MEMS transducers, or for test systems as a signal source or pulse signal generators. The HV7 s circuitry consists of controller logic circuits, level translators, gate driving buffers and a high current and high voltage MOSFET output stage. The output stages of each channel are designed to provide peak output currents typically over ±.A for pulsing, with up to ±V swings in RTZ mode. The upper limit frequency of the pulser waveform is depending on the load capacitance. This demoboard datasheet describes how to use the HV7DB to generate the basic high voltage pulse waveform as an ultrasound transmitting pulser. The HV7 circuit uses DC coupling from a.v logic input to output Tx~8 internally, therefore the chip needs three sets of voltage supply rails: V LL +.V, V DD +.V and V PP ± to ±V. The V PP and V NN rail voltages can be changed rather quickly, compared to the capacitor gatecoupled driving pulsers. This direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the PCB layout easier. The HV7DB output waveforms can be displayed using an oscilloscope by connecting the scope probe directly to the test points TX~8 and. The soldering jumper can select whether or not to connect the on-board dummy-load, a pf capacitor paralleling with a.kω resistor. The test points can be used to connect the user s transducer to easily evaluate the pulser. Block Diagram +.V +.V +.V + to +V.µF.µF.µF.µF.µF VLL CPOS CPF EXCLK OSC MHz CLK IN PIN V REF +.V +.V LRP P-Driver VPF LRP of 8 Channels R HV OUT JTAG EN WAVE FREQ PHAS Waveform Generator CPLD NIN PIN8 NIN8 CLK RTZ PHAS PWR DAP SUB Logic & Level Translator -V LRN VPF VNF N-Driver VNF +.V DMP -.V LRN CNEG CNF.µF.µF - to -V R.µF Rb TX C pf R R Dummy Load R.k TX R Doc.# DSDB-HV7DB A7

2 The PCB Layout Techniques The large thermal pad at the bottom of the HV7 package is internally connected to the IC s substrate (VSUB). This thermal pad should be connected to V or externally on the PCB. Designers need to pay attention to the connecting traces on the outputs TX~8, specifically the high voltage and high speed traces. In particular, controlled impedance to the ground plane and more trace spacing needs to be applied in this situation. High speed PCB trace design practices that are compatible with about to MHz operating speeds are used for the demoboard PCB layout. The internal circuitry of the HV7 can operate at quite a high frequency, with the primary speed limitation being load capacitance. Because of this high speed and the high transient currents that result when driving capacitive loads, the supply voltage bypass capacitors and the driver to the FET s gate-coupling capacitors should be as close to the pins as possible. The pin should have low inductance feed-through via connections that are connected directly to a solid ground plane. The,,, CPF, CNF, CNEG and CPOS voltage supply and/or bypass capacitor pins can draw fast transient currents of up to ±.A, so they should be provided with a low impedance bypass capacitor at the chip s pins. A ceramic capacitor of. to.µf may be used. Only the and pins to capacitors need to be the high-voltage type. The CPF to and CNF to capacitors maybe low voltage. Minimize the trace length to the ground plane, and insert a ferrite bead in the power supply lead to the capacitor to prevent resonance in the power supply lines. For applications that are sensitive to jitter and noise and using multiple HV7 ICs, insert another ferrite bead between each chip s supply lines. Pay particular attention to minimizing trace lengths and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of the HV7 s high voltage power stages is very low, in some cases it may be desirable to add a small value resistor in series with the output TX~8 to obtain better waveform integrity at the load terminals after long cables. This will, of course, reduce the output voltage slew rate at the terminals of a capacitive load. HV7DB Be aware of the parasitic coupling from the outputs to the input signal terminals of the HV7. This feedback may cause oscillations or spurious waveform shapes on the edges of the signal transitions. Since the input operates with signals down to.v, even small coupling voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Also ensure that the circulating ground return current from a capacitive load cannot react with common inductance to create noise voltages in the input logic circuitry. Testing the Integrated Pulser The HV7 pulser demoboard should be powered up with multiple lab DC power supplies with current limiting functions. The on-board dummy load pf//.kω should be connected to the high voltage pulser output through the solder jumper when using an oscilloscope s high impedance probe to meet the typical loading condition. To evaluate different loading conditions, one may change the values of RC within the current and power limit of the device. In order to drive the user s piezo transducers with a cable, one should match the output load impendence properly to avoid cable and transducer reflections. A 7 to 7Ω coaxial cable is recommended. The coaxial cable end should be soldered to the TX~8 and directly with very short leads. If a user s load is being used, the on-board dummy load should be disconnected by cutting the small shorting copper trace in between the Ω resistors R, R9, R, R8, R, R, R or R pads. They are shorted by factory default. All the on-board test points are designed to work with the high impedance probe of the oscilloscope. Some probes may have limited input voltage. When using the probe on these high voltage test-points, make sure that V PP voltages do not exceed the probe limit. Using the high impendence oscilloscope probe for the on-board test points, it is important to have short ground leads to the circuit board ground plane. If both of the inputs PIN and NIN are high, then the channel out TX will be in Hi-Z. Doc.# DSDB-HV7DB A7

3 HV7DB Doc.# DSDB-HV7DB A7 HV7DB Schematic PAD V CC = +.V V DD = +. to.v V PP / V NN = +/-. to 7V Note: J-,, & 7- pins for test only TP CLK SYNC EXTRG U XC97XL_VQ PIN NIN PIN NIN PIN NIN PIN NIN PIN NIN PIN NIN PIN7 NIN7 PIN8 NIN8 TX TX TX TX TX TX TX7 TX8 R R R R R R VLL VLL CPF CPF MH MH MH MH D7 RED D YLW D GRN R.k D RED D YLW R.k R.k R7.k R8.k TP TP9 TP J EXCLK EX= EN OUT MHz X TP J C8. R.k 9 R TP EXTRG TP8 R k R k C. SW R k C. C. C. C. SW SW SW SW R k R7 k R8 k R9 k R R R R R C. WAV FRE SEL ENA MOD TMS TDI TDO TCK SET LE MC CS EN 9 8 C C C U HV7 C C9 TP C µf C µf TP8 PIN NIN PIN NIN PIN NIN PIN NIN PIN NIN PIN NIN PIN7 NIN7 PIN8 NIN8 J JTAG C. RTZ PHAS PWR C µ C9 µ C8 µ C µ TP TP TP TP TP9 TP8 TP7 TP TP TP TP9 TP8 TP7 TP TP TP9 TP TP TX TX TX TX8 TX TX TX TX7 PAD CPOS CNEG CNF CNF TP R.k W C P V TP R R.k W C9 P V TP9 R TP TP BAV99/SOT_ D BAV99/SOT_ D R.k W C8 P V TP R R.k W C P V TP7 R9 TP TP BAV99/SOT_ D9 BAV99/SOT_ D8 R.k W C9 P V TP R R9.k W C P V TP R8 TP TP BAV99/SOT_ D7 BAV99/SOT_ D R.k W C P V TP R R.k W C P V TP R TP TP BAV99/SOT_ D BAV99/SOT_ D C µf TP C7 µf TP7 C8 µf v C7 µf v TP C µf C µf DA BATDW-7 DB BATDW-7 D7 B- D B- SYNC CNEG CPOS CNF CPF J HEADER R R R8 INF R7 INF R7 INF R R

4 HV7DB HV7DB PCB and Board Layout Actual Board Size: 7.mm x 8.mm Power Connector Description + +.V Logic voltage input for VLL and CPLD. (ma) V, Ground + +.V HV7 positive supply. (ma) CNEG -.V HV7 negative VNEG supply, only when = CPOS +.V HV7 Positive VPOS supply, only when = CNF HV7 VNF supply reference to, ( VNF - ) = +.V, only when = 7 CPF HV7 VPF supply reference to, ( - VPF) = +.V, only when = to -V negative high voltage supply. (-.ma) 9 V, Ground + + to +V positive high voltage supply. (+.ma) Note: J- to 7 are for external power connection of VNEG, VPOS, VNF, VPF, when =. Note, as default the resistors R, R7, R8 and R7 is not installed. Do not need to connect these four pins to any power supply when internal regulators are be used when =. Voltage Supply Power-Up and Operation Sequence + Power on +.V positive logic supply voltage for HV7 s VLL and CPLD + Power on +.V positive supply & + / - & Turn on & LED on WAVE Button Push WAVE button to select waveforms Turn both & LED off Power on / = ± to V positive and negative high voltage supply Note: Power-down in the, to reversing order. Push Button Operations WAV Toggle select pulse B-mode waveforms: None, -cycle, -cycle inverting, -cycle & -cycle inverting FREQ Toggle select B-mode demo frequency of,,.,. &.MHz when X oscillator is MHz PHAS Toggle select B-mode waveform phase polarity Toggle on or off HV7 chip output signal Toggle select on or off HV7 internal voltage-regulators signal Doc.# DSDB-HV7DB A7

5 LED Indicator RTZ RTZ indication, default is on PHAS Phase polarity indication PWR HV7DB V LL.V and CPLD chip V CC power supply indication HV7 chip enable EN signal indication, power on default is off until button is pushed HV7 built-in regulators enable indication, power on default is off until button is pushed Typical Waveforms HV7DB Figure. V PP = +/-V MHz with pf//.kω load and 8-Channel pulsing Figure. V PP = +/-V MHz with pf//.kω load and 8-Channel pulsing Doc.# DSDB-HV7DB A7

6 Typical Waveforms (cont.) HV7DB Figure. V PP = +/-V MHz with pf//.kω load and 8-Channel pulsing Figure.. Rise and Fall time at V PP = +/-V with pf//.kω load Doc.# DSDB-HV7DB A7

7 HV7DB Typical Waveforms (cont.) Figure. V PP = +/-V MHz with pf//.kω load and 8-Channel pulsing Figure. Damping fall time at V PP = +/-V with pf//.kω load Doc.# DSDB-HV7DB A7 7

8 HV7DB Typical Waveforms (cont.) Figure 7. Damping rise time at / = +/-V with pf//.kω load Figure 8. / = +/-V MHz with pf//.kω load of the 8-Channel waveforms shown Doc.# DSDB-HV7DB A7 8

9 HV7DB Typical Waveforms (cont.) Figure 9. HD at V PP = +/-V.MHz with pf//.kω load Doc.# DSDB-HV7DB A7 9

10 Bill of Materials HV7DB Component Description Manufacturer Part Number C - C, C8, C9, C, C, C - C C, C, C, C, C9, C8 - C C, C8, C, C, C, C, C, C7 CAP CER.µF V X7R % TDK C8X7RCK CAP CERC PF V X7R Panasonic ECJ-VBDK CAP CER.µF V X7R TDK C8X7RCM C, C9, C7, C8 CAP CER µf V X7R % TDK CX7RAM D, D7 LED THIN NM RED DIFF 8 SMD Lumex SML-LXT8IW-TR D, D LED THIN 8NM YEL DIFF 8 SMD Lumex SML-LXT8YW-TR D LED THIN NM GRN DIFF 8 SMD Lumex SML-LXT8GW-TR D, D7 DIODE SCHOTTKY V A SMA Diodes Inc. B- D DIODE SCHOTTKY DUAL V SOT- Diodes Inc. BATDW-7 D - D DIODE SWITCH SS DUAL 7V SOT Fairchild BAV99WTG J CONN HEADER POS. VERT GOLD Molex -8- J CONN JACK END LAUNCH PCB GOLD SMA Johnson -7-8 J CONN HEADER POS. VERT GOLD Molex -8- J CONN HEADER POS. VERT GOLD Tyco -- R, R9, R, R8, R, R - R R, R, R, R9, R, R, R, R R - R8, R, R, R Solder Gap (SHORT) NA NA RES.kΩ W % SMD Panasonic ERJ-TNFU RES.kΩ /W % SMD Panasonic ERJ-EKFV R RES 9.9Ω /W % SMD Panasonic ERJ-EKF9R9V R, R, R7, R8, R9 RES.kΩ /W % SMD Panasonic ERJ-EKFV R, R RES.Ω /W % SMD Rohm MCREZPFLR R, R RES.Ω /W % SMD Panasonic ERJ-EKFRV R, R7, R8, R7 NA NA NA R, R, R, R, R SW, SW, SW, SW, SW RES OHM /W % SMD Panasonic ERJ-EKFV SWITCH LT.7MMX.MM GF SMD Panasonic EVQ-PM TP, TP TEST POINT PC MULTI PURPOSE BLK Keystone U IC CPLD 7 MCELL C-TEMP -VQFP Xilinx XC97XL-VQC U IC HV7K-G 8-ch RTZ Supertex Inc. HV7K-G X OSC CLOCK. MHZ.V SMD CTS CBLV-C-.-T does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the (website: http//) All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSDB-HV7DB A7 Bordeaux Drive, Sunnyvale, CA 989 Tel: