System Design Criteria

System Design Criteria GEBE \DDS\Criteria..ppt Aug96

Switching Characteristic: Speed vs Slew Rate input 90% output W SG 9 2+ 9 2/ 10% W U W Propagation delay: Transition time: Voltage swing: W SG W U ULVHWLPHRUW I IDOOWLPH 9 2+ 9 2/ 6OHZUDWH GY GW 9 2+ 9 2/ [ W U RUW I GEBE \DDS\Criteria..ppt Aug96 Noise in digital logic systems are of different nature: - External noise radiated into the system - Power-line noise coupled through the AC and DC power distribution system - Cross talk induced into signal lines from adjacent signal lines - Signal- and supply-current spikes caused by switching several loads - Transmission-line reflection from unterminated transmission lines. A major noise source is the integrated circuit, simply because of its high-speed switching. As can be seen from the formula, a circuit s slew rate corresponds to the transition (rise or fall) time of the output signal. The shorter the rise or fall time, the higher the slew rate. Knowing about the slew rate, is a good way to get a rough estimation on the noise potential of the device in use. However, keep in mind that propagation delay and slew rate are not necessarily proportional. 4-2 2

Switching Characteristic Slew Rate - 5-V Logic 5. 5 V 5. 5 V 5. 0 V Vcc = 5V Load = 500Ohm /50pF 5. 0 V 4. 5 V 4. 0 V 3. 5 V 3. 0 V AC244 AHC244 4. 5 V 4. 0 V 3. 5 V Vin put Vcc = 5V Load = 500Ohm/50pF Voltage 2. 5 V 2. 0 V ABT244 Voltage 3. 0 V 2. 5 V AC244 HC 244 1. 5 V 1. 0 V Vi npu t F244 HC 24 4 2. 0 V 1. 5 V AHC 244 0. 5 V 1. 0 V ABT244 0. 0 V -0.5 V 0. 5 V F244-1.0 V 0. 0 V -1.5 V 0 ns 2 ns 4 ns 6 ns 8 ns 10 ns 12 ns 14 ns 16 ns 18 ns 20 ns Time -0.5 V 0 ns 2 ns 4 ns 6 ns 8 ns 10 ns 12 ns 14 ns 16 ns 18 ns 20 ns Time F ABT HC AHC AC Slew rate (tphl): 1.3 1.0 0.9 0.8 1.8 V/ns F ABT HC AHC AC Slew rate (tplh): 0.9 1.0 0.8 0.7 1.5 V/ns GEBE \DDS\Criteria..ppt Aug96 This and the next page show the propagation delays (t pd), voltage swing (V OH - V OL ) and slew rates (dv/dt) for selected 5V and 3V logic families. F, ABT, HC, AHC and AC are operated from a 5V supply voltage, while LVT, ALVC, LVC, AHC and LV have a 3.3V supply (next page). The data indicate that t pd and dv/dt show common trends (the shorter the propagation delay, the higher the slew rate). However, there is no direct link between the two parameters. In particular, the fastest family is not the one with the highest slew rate. This must be considered, especially when designing high speed systems. As will be discussed later in this section, high slew rates are very unfavourable, as they design into high noise levels generated by the components. The worst technology in this respect is 5V AC. 4-3 3

Switching Characteristic Slew Rate - 3-V Logic 3.5 V 3.0 V ALVC244 Vc c = 3.3V Load = 500Ohm/50pF 4. 0 V 3. 5 V 2.5 V LVC244 3. 0 V Vin put 2.0 V LV T244 2. 5 V ALVC244 Voltage 1.5 V 1.0 V Vinput AHC244 Voltage 2. 0 V 1. 5 V AHC2 44 LV244 0.5 V 1. 0 V LVC2 44 0.0 V 0. 5 V LVT244-0.5 V 0. 0 V L V244 Vcc = 3.3V Load = 500Ohm/50pF -1.0 V 0 ns 2 ns 4 ns 6 ns 8 ns 10 ns 12 ns 14 ns 16 ns 18 ns 20 ns Tim e -0.5 V 0 ns 2 ns 4 ns 6 ns 8 ns 10 ns 12 ns 14 ns 16 ns 18 ns 20 ns Time LVT ALVC LVC AHC LV Slew rate (tphl): 1.2 1.3 0.9 0.5 0.7 V/ns LVT ALVC LVC AHC LV Slew rate (tplh): 1.0 1.2 0.8 0.4 0.5 V/ns GEBE \DDS\Criteria..ppt Aug96 These curves show the propagation delays (t pd), voltage swing (V OH - V OL ) and slew rate (dv/dt) for selected 3V logic families (LVT, ALVC, LVC and LV) and AHC operated at Vcc=3.3V (as specified in the datasheet). In comparison to the 5V families all of the low voltage technologies have somewhat lower signal slew rates. It should be especially noted that ALVC, the fastest of all technologies shown, exhibits a comparably low slew rate. This is due to appropriate circuit design techniques and the SSOP/TSSOP package technology used for these 16- to 20-bit bus interface functions. 4-4 4

Slow Input Signals (1) input output output not in reality! input Slow input signals can cause oscillations both on the output and input side because of induced chip-internal noise. With an input voltage hysteresis, this effect will only occur, if very slow input signals are applied. GEBE \DDS\Criteria..ppt Aug96 An often overlooked problem in system design are floating (or slow) inputs. When using CMOS inputs especially (i.e. with all CMOS and BiCMOS logic devices), leaving an input floating may sometimes lead to very high supply currents, I CC, or to subsequent oscillations on the circuit s output side. The reason for this is that in each state - high or low - one transistor is conducting. The transition, however, is flowing exactly in half way both transistors are leading current. If the voltage at the input rises slowly and if it reaches the value of the threshold voltage, the output then switches rapidly from high to low as a result of the high voltage amplification and discharges the load capacitor. The discharge results in a voltage drop at the internal ground potential of the IC. This causes a reduction of the potential difference between the input and the internal ground potential, which has the effect of reducing the input voltage, and as a result causes the output to switch to the opposite direction. The same thing happens now, but with reversed polarities.this continues periodically, whereby the duration of the period is determined by the delay time of the circuit. As these oscillations mean high energy moving back and forth between the output and the load, they drastically increase the overall power and heat dissipation. Worst case, the circuit may be destroyed after some time. 4-5 5

Slow Input Signals (2) 1. Do nothing - - - feel lucky? 2. Do nothing, if duration of 3-state is < 2µs R 3. Use a pull-up resistor Downside: extra components bus parasitics high power dissipation 4. Use a device with integrated bus hold cell - LVT - LVT16 (Widebus ) - LVCH* - LVCH16* (Widebus) - ALVCH16 (Widebus) - ABTH16* (Widebus) * Selected functions only GEBE \DDS\Criteria..ppt Aug96 A few options are available to the system designer, to address the problem of floating (or slow) inputs. Obviously, one can choose to ignore it and, depending on the load conditions along the floating line, may even be lucky that the increase in power consumption remains uncritical. However, Murphy s famous law unfortunately also applies to electronic design: whatever CAN go wrong, WILL probably go wrong. The problem can be ignored, though, if the duration of 3-states, i.e. the time period(s) during which the line may start to float, is shorter than 2 microseconds. In this case, the line level will only change gradually. In all other cases, there are two options left: one can use a pull-up (or pull-down) resistor to ensure proper signal levels, if all circuits are 3-stated. This is a reliable, but power consuming method. It also changes the line s impedance unfavourably. The other option is to use so-called bus hold cells, to ensure proper signal levels along the line. Separate ICs are being offered by some manufacturers to provide this function. The best method, however, is to use devices with integrated bus hold cells. Most of Texas Instruments LVC, ALVC and LVT devices feature integrated bus hold cells. 4-6 6

Slow Input Signals (3) Recommended Input Slew Rate Limits Series V CC[V] V il,max[v] V ih,min[v] V T[V] T f,max[ns/v] SN74 4.74-5.25 0.8 2.0 1.4 100 SN74LS 4.74-5.25 8.8 2.0 1.0 50 SN74S 4.74-5.25 0.8 2.0 1.4 50 SN74ALS 4.5-5.5 0.8 2.0 1.4 15 SN74AS 4.5-5.5 0.8 2.0 1.4 8 SN74F 4.5-5.5 0.8 2.0 1.4 8 SN74HC 2.0 0.3 1.5 1.0 625 4.5 0.9 3.15 2.25 110 6.0 1.2 4.2 3.0 80 SN74HCT 4.5-5.5 0.8 2.0 1.4 125 SN74AHC 3.3 0.9 2.1 1.5 100 5.5 1.65 3.85 2.75 20 SN74AHCT 4.5-5.5 0.8 2.0 1.4 20 SN74LV 2.7-3.6 0.8 2.0 1.5 100 74AC 3.0 0.9 2.1 1.5 10 4.5 1.35 3.15 2.25 10 5.5 1.65 3.85 2.75 10 74ACT 4.5-5.5 0.8 2.0 1.5 10 SN74LVC 2.7-3.6 0.8 2.0 1.5 10 SN74ALVC 2.3-3.6 0.8 2.0 1.5 10 SN74BCT 4.5-5.5 0.8 2.0 1.5 10 SN74ABT 4.5-5.5 0.8 2.0 1.5 5/10 SN74LVT 2.7-3.6 0.8 2.0 1.5 10 GEBE \DDS\Criteria..ppt Aug96 Above table gives an overview about Texas Instruments logic families with respect to the maximum input transition rise or fall rate. There is a direct correlation between speed and the parameter for rise and fall time. As faster the family, as higher the rise or fall time and as more critical will be the slew rate. 4-7 7

Current Spikes 5V Input voltage 3V 10mA/Div 10mA/Div Current to Vcc terminal 10ns SN74ACT245 Current spikes are caused by Totem pole overlap : Both output transistors are conductive for a short time during switching the output stage Technology ALS F,BCT AS HC/HCT AHC/AHCT LV AC/ACT LVC ALVC ABT LVT 10ns SN74AHC245 Peak current [ma] 10 30 35 20 15 20 50 35 30 25 25 GEBE \DDS\Criteria..ppt Aug96 This foil explains the current peaks which occur always during switching. A characteristic common to all Totem-Pole and 3-State output stages contributes an additional current transient, when the output changes from a logic low to high and vice versa. The internal output circuitry of the devices consists of two alternately conducting transistors. At every transition from logic high - state to logic low - state both output transistors are - indeed for a very short time - conductive. This is called Totem pole overlap. The total supply-current spike is a combination of three major effects: - the difference in high-level and low-level supply current - the charging of load capacitance - and the conduction overlap. The charging of load capacitance in most cases overshadows the other two effects with respect to noise produced on the supply voltage lines by switching current transients. However, to keep the current spike as low as possible, it is important to maintain low impedance of the power lines, use decoupling capacitor (bypass capacitor) at the devices supply pins and keep the area covered by the power traces small. 4-8 8

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Decoupling Guidelines Capacitance can be calculated I = C dv/dt, from the amount of current needed, how long the current is needed, and what change in voltage is allowable. Voltage 3.5 V 3.0 V 2.5 V 2.0 V 1.5 V 1.0 V Vinput ALVC24 Vcc = 3.3V Load = 500Ohm/50pF LVC244 LVT244 AHC244 LV244 0.5 V Choose a capacitor whose resonant frequency is at least as high as the corresponding edge rates of the switching signals, where frequency response @ 1 / (3.5 t rise,fall ). 0.0 V -0.5 V -1.0 V 0 ns 2 ns 4 ns 6 ns 8 ns 10 ns 12 ns 14 ns 16 ns 18 ns 20 ns Time 1 f re s (LVC) = (3.5 2 ns) = 143 MHz Place the capacitors as close to the switching device as possible. In the case of a transceiver place the capacitance between the VCC and Ground planes at the part. In the case of termination place the capacitance from the supply voltage to Ground at the termination resistor. DDS\Criteria GB Aug96 While the slew rate and the corresponding ground bounce noise mainly depend on the technology chosen, a system designer will have to decide on the decoupling method used to prevent voltage drops and ringing on the power supply lines. This is somewhat more critical in 3.3V systems than in 5V environments, where sometimes larger voltage drops are still acceptable. A bypass (decoupling) capacitor stores an electrical charge that is released to the power line, whenever a transient voltage spike occurs. It provides a low impedance supply, thereby minimizing the noise generated by the switching outputs of the device. Bypassing a power line (or plane) from the device internal noise requires capacitors with very small inductances. That is why the multilayer ceramic chip capacitors (MLC) are more favourable than others for bypassing power lines (or planes). They exhibit negligible internal inductance, thereby allowing the charge to flow easily, when needed, without degradation. For TTL and CMOS systems, a good guideline is 0.01 µf per device. For effective decoupling on printed circuit boards the most desireable arrangement is a multilayer board with solid GND and V CC plane. In addition it is highly recommended that the bypass capacitor is placed as close as possible between the power pins of the device. 4-19 19

Noise Margins HC/AHC AC HCT/AHCT ACT LVT ALVC LVC LV ALS/F/AS BCT ABT V oh typ V ih min threshold volt. V max il V ol typ typical 50% 27% 43% 33% worst-case 29% 15% 20% 13% typical noise margin S = V T,typ - V OL V OH - V OL typical noise margin S = V IL,max - V OL V OH - V OL DDS\Criteria GB Aug96 Noise margin is a voltage specification that ensures the static DC immunity of a circuit to adverse operating conditions. The noise margin is defined as the difference between the worst-case input logic level and the worst-case output logic level. The usefulness of noise margins at the system design level is the ability of a device to be resistant to noise spikes at the input. Above comparison shows the noise margin for selected logic families. The 5V CMOS families - HC, AHC and AC - have a typical noise margin of 50% and even in the worst-case condition a remarkable noise margin of 29%. In comparison, the TTL-compatible Bipolar and BiCMOS families have 13% in worst-cast condition, only. But if we have a look at the low-voltage families, all 3.3V devices have an improved noise margin of 20% in worst-case, which makes this families even more attractive for new designs. The improved noise immunity of 5V CMOS and 3.3V families over bipolar and BiCMOS devices is due to the rail-to-rail (Vcc to GND) output voltage swing. This noise immunity makes them ideal for high noise environments. However, keep in mind that TTL-compatible 5V CMOS devices, such as HCT, AHCT and ACT, have similar noise margins to bipolar and BCMOS. 4-20 20

Bipolar / BiCMOS / CMOS Comparison Electromagnetic Interference Bipolar/ BICMOS 3-V logic 5-V CMOS voltage swing 3 V 3 V 5 V slew rate output current dv/dt I X X 0.9 X 1.2 X 1.5 X 1.5-2.0 X relative EMI power (dv/dt) x I X 2 X 2 2.2-3.0X 2 5-V CMOS slew rate and output current are 50% greater than 3-V - CMOS or bipolar, for equal speeds. Thus electromagnetical interference for 5-V - CMOS is more than twice as great. DDS\Criteria GB Aug96 Like line-reflection, crosstalk or simultaneous switching, also noise from Electromagnetic Interference (EMI) depends on the integrated circuits switching characteristic. The three major factors affecting EMI are the output voltage swing, the devices slew rate and the output current. However, all three factors can be addressed to minimized switching noise: - Output Edge Control TM (OEC) reduces high-frequency components (implemented in all new logic families at TI) - lower output voltage swing - this reduces critical slew rate (e.g. use 3.3V logic) - reduce package inductance (SOICs better than DIPs) - minimize output drive (e.g. use AHC instead of AC) As a result from above calculation, the EMI noise from 5V CMOS is more than twice as great as from bipolar or 3.3V devices. 4-21 21

Technology Comparison Ease of Design Bipolar/ BiCMOS 5-V CMOS CMOS compatible 5-V CMOS TTL compatible 3V Logic Noise Margin worst case Noise Energy (du/dt x I) X 2.2 X 1.1X 1.5 X (13%) (29%) (15%) (20%) X 2 2.2-3.0 X 2 2.2-3.0 X 2 ~X 2 Reducing Vcc (e.g. to 3.3 V) will not improve switching noise, but will give a better noise margin. DDS\Criteria GB Aug96 A general technology comparison between bipolar, BiCMOS, 5V CMOS and 3.3V CMOS circuits will only make sense, if looking at both the device-related noise energies and the noise margins that are dictated by the input and output signal level specifications. Confronting these two parameters, one finds that bipolar or BiCMOS circuits show about the same ease of design level as CMOS parts working at CMOS levels (ie with a Vcc/2 input threshold voltage). Looking at the 3.3V technologies you actually see the best ratio in noise energy vs noise margin, which in addition makes 3.3V devices very attractive for new designs. The most critical combination, however, is CMOS process technology and bipolar-like TTL-level specifications. Because of high noise levels of CMOS and the lower noise margins of TTL-level systems sometimes a crucial obstacle is encountered, whilst developing reliable-working systems. 4-22 22

EMI PCB Design Guidelines: Overview Since January 1996, a new EC (European Community) directive regarding electromagnetical compatibility (EMC) came into effect. The EMC regulation affects many aspects of circuit and system design. Electromagnetic Interference (EMI) is switching noise that is radiated or conducted via electric and magnetic field. As manufacturer of electronic components, Texas Instruments are committed to minimize both the emmissions from and susceptibility to electromagnetical interference. DDS\Criteria GB Aug96 The EC (European Community) regulations regarding EMC will affect many aspects of circuit and system design. However, there are many considerations that can be applied generally to reduce both the emission from and susceptibility to EMI. Electromagnetic interference (EMI) often seems like a mysterious phenomenon. EMI can be difficult to control, and even the results of EMI testing can vary from day to day and from test facility to test facility. At times, the act of controlling EMI has been called black magic or voodoo. However, EMI has been researched for many years, and guidelines have been established that can improve the electromagnetical compatibility of a system to which they are applied. Designing for low EMI from the start of a project results in much easier and less expensive solutions than attempting to fix EMI problems, after a design has reached the testing phase of development. Consequently, following a few guidelines for printed circuit board (PCB) design at the beginning of a project can help to minimize the systems EMI while adding little or no cost to the system. This chapter will give some tips and recommondations for low-noise design. 4-23 23

EMI PCB Design Guidelines: RF Sources digital vs analog grounds bypass capacitor power lines voltage regulator through-hole SMD vs through-hole circuit - output - input - power&ground - current spikes - crosstalk multi-layer basic loops line characteristic oscillator DDS\Criteria GB Aug96 Let us start looking at typical digital PCB with a quick look at the most EMI critical areas on the PCB. There are three important contributors of RF noise. The number one problem is noise from the IC I/O pins, simply because the area covered by traces connected to them on the PCB makes large antenna (basic loops!). The second most important contributor is the power supply system, which includes the voltage regulation, the bypassing capacitor and the suppy lines. These components are the source and the sink of all RF energy in the system. The number three noise source is the oscillator circuit, where the oscillator swings rail to rail. In addition to the fundamental frequency harmonics are introduced on the output side. 4-24 24

EMI PCB Design Guidelines: Definition RF-Source: RF-Channel: RF-Sink: RF-Noise: RF-Effects: Trace bound (RF-voltage/current) and radiated interface (RFnoise), e.g. active components like diodes, transistors, integrated circuits, etc. Signal lines; power lines; boards; modules; systems Receiver of RF-noise (e.g. IC input, IC supply-pins) Caused by voltage, current or field effects --> important factors are amplitude and period Reflection; cross talk; current spikes; simultaneous switching; coupling of signals; etc. DDS\Criteria GB Aug96 EMI requires a source, a path and a receiver. In today s electronics, integrated circuits (IC) often supply the source and the printed circuit board, as well as the associated cabelling and wire harness, acts as the conductive and radiating part of the path, otherwise called antenna. The receiver simply can be a IC s input, a sensitive electronic module, such as a radio, or it can be a loop at the PCB, accidently designed to receive electromagnetical noise. EMI generation is a function of RF-source, RF-channel and RF-sink. All three components are involved in EMI generation in a system, as they source, transmit and feed the current required in switching. The two major factors affecting RF energy is the amplitude and period of the switching signal: Switching frequency, duty cycle, edge rate, noise content and voltage levels. Noise is generated and coupled out through many different possible mechanisms: line reflection, crosstalk, current spikes, simultaneous switching, etc. 4-25 25

EMI PCB Design Guidelines: Frequency Spectrum of Digital Signals Sinus T Triangle T Typical digital T Square wave T Spectrum Comparison 1.2 Linear 0 Logarithmic Peak Voltage [normalized] 1 0.8 0.6 0.4 0.2 0 Sinus Triangle typ. Digital Signal Square-Wave Peak Voltage db -10-20 -30-40 -50 Sinus Digital Signal Square-Wave Tria ng le 1 2 3 4 5 6 7 8 9 Frequency [n/fo ] -60 0 5 10 15 20 Frequency [n/fo] DDS\Criteria GB Aug96 To get a better understanding of EMI, it is important to know the frequency spectrum of the waveform used in digital systems. The upper curves represent some basic signal waveforms which could be found in today s electronic systems. In digital systems, however, the trapezoidal (square) signal dominates. Beside the sinus waveform, all others include beside the fundamental frequency also harmonics of the fundamental frequency. The fundamental frequency and its harmonics, as well as any noise (ringing) on the signal, will influence the frequency envelope in which EMI generation may be expected. The lower curve illustrates the theoretical spectrum lines of the upper signals. The sinus curve consists of only one spectrum line, whereas the square wave includes a lot of high frequency harmonics. The right-hand figure illustrates the logarithmic spectral content in db. 4-26 26

EMI PCB Design Guidelines: Frequency Spectrum of Digital Signals: LVC245 3.3V DIR A8 Vcc G B8 3.3V 47 nf 120 Ω 1 MHz Duty Cycle 50% LVC245 each 50 pf 51 Ω Analyser GND B1 Rising Edge Frequency Spectrum Falling Edge DDS\Criteria GB Aug96 Above slide illustrates a lab measurement of output spectral content for SN74LVC245. The measurement setup represents a typical bus line with about 150 Ohm resistance and 47 pf capacitance. The spectrum of the digital signal was measured with a spectrum analyser at the end of the artificial bus line. The shape of the spectrum envelope shows good conformity to the theory. At this point you should not forget that the spectrum is given in db (20 db are equal to factor 10!) The figure on the right-hand side shows the output signal of the SN74LVC245. The slew rate with this test condition is about 1.5V/ns and the rising and falling edges are very symmetrical. 4-27

EMI PCB Design Guidelines: IC-I/O Pin Noise The number one problem is RF-noise from the IC - I/O pins signal/power traces connected to the pins on the PCB make a large antenna Noise from a pin is a function of the chip and package minimize output voltage swing reduce package inductance smooth output waveform edge Îe.g. 3.3V logic Î SOICs are better than through-hole devices Î use devices with Output Edge Control TM minimize capazitive loading Î reduces current loading per part eliminate switching noise Î use bypass capacitor, advanced packages, avoid undefined inputs voltages minimize output drive Î e.g. use AHC instead AC DDS\Criteria GB Aug96 We are going to be concerned with the RF noise from the device. That noise is generated internally to the device and is coupled out through many different possible mechanisms. The noise will be present on all outputs, inputs, and power and ground, at all times. Basically, every pin on the device could be a problem. The most critical pins are the IC I/O pins, simply because the area covered by traces connected to them on the PCB makes a large antenna. The noise from clock switching internally to the IC, simultaneous switching, internal crosstalk or current spikes, appears as noise spikes on outputs, inputs as well as power/ground pins. On the chip and package level several design improvements have improved signal quality. Additional circuitries like Output Edge Control TM (OEC), Power-On- Demand (POD), Bus Hold (BH) and package improvements like split ground lead frame, (thin) small-outline packages, Widebus TM packages and flow-through pinout, help to minimize device generated noise. 4-28 28

EMI PCB Design Guidelines: Basic Loops Every signal sent out from the IC to another chip returns on the return path back to the IC (e.g. via ground) it travels in a loop back to where it originates loops are antennas which radiate RF energy shield cable loops bypassing loops connector loops V µp signal loops power supply voltage regulator ambient field loops oscillator loops DDS\Criteria GB Aug96 The amount of radiation produced by an electronic system is to a large extent proportional to the efficiency of its radiating antennas - or basic loops. Antennas or loops on a PCB include all traces, components, component leads, connectors and wiring harnesses. Every edge transition that is sent out from the µp to another chip, is actually a current puls. It goes to the receiving device and actually exits through that device s ground pin. It then returns, via ground traces, back to the ground pin of the µp. It travels in a loop back to where it originates. Loop exits everywhere. Any noise voltage and its associated current will travel the path(s) of lowest impedance back to the place where it was generated. A loop can be a signal and its return path, the bypassing loop between power and ground and the active device inside the µp, the oscillator cristal as well as the loops from power supply or voltage regulator to bypassing cabs. Other more difficult loops are actually ambient field loops. For example, the cristal itself radiates and can be coupled into a wire running nearby. Then the wire contains noise that is going to try to get back to the cristal loop. That may mean a very long convoluted path, which of course serves as another antenna for the cristal noise. The understanding what loops are is a very powerful concept, because it allows to track all signals on the board, avoid unknown return path (flying leads) and migrate noise propagation by controlling the shape and impedance of the return path. 4-29 29

EMI PCB Design Guidelines: Antenna radiates RF noise Loops and dipols are antennas. Their radiating efficiency increases up to 1/4 wavelength of the frequency of interest at Ö 1MHz, λ/4=75 meters *) Ö 300MHz, λ/4=25 cm *) Normaly, trace length becomes important when it is greater than Ö λ/10: FCC Limits Ö λ/20: Automotive Ö λ/40: Mil Std *) vacuum; effective length of the antenna is determind by µ r and ε r (PCB ε r =5) E 1 = k I A sin ϑ r DDS\Criteria GB Aug96 Loop areas can be the most serious EMI threat. A loop can transmit as well as receive electromagnetic energy. Thus, the loop areas associated with a PCB directly affect the emissions and immunity of the system. Loops and dipols are antennas. As the size of a loop increases, so does the efficiency of the loop as a radiator. Their radiating efficiency increases up to 1/4 wavelength of the frequency of interest. Geometrically, that means, in case of a loop, that the larger the laid out area of the loop, the stronger the radiation. This is true up until one or both legs of a loop reach 1/4 wavelength. Thus to minimize radiated and received EMI, loops must be made as small as possible. 4-30 30

EMI PCB Design Guidelines: Power & Grounds (1) Power supply system is often the most important contributor of RF noise (Current spike) Ground&Power should have as low an inductance as possible - 2-layer board: length to width ratio should not exceed 3:1 (bypass capacitor) - power and ground should be run directly over each other (Z ; looparea) A 2-layer board can achieve 95% of the effectiveness of a multilayer board, if you: - route the ground underneath power - grid the power and ground - route return path directly under/parallel the signal trace (gridding; ground plane) - build a solid plane for ground under the IC DDS\Criteria GB Aug96 Proper power routing is of fundamental importance to achieve electromagnetic compatibility. The only non-dc current that should flow in the power lines of the PCB is the current for the bypassing capacitor. High frequency current used inside the IC should come from the bypass capacitor, not the power supply! Since a ground is really a current return path in most cases, the goal of any trace carrying RF energy is to provide the lowest impedance current path possible without generating additional noise. A ground (power) plane will best accomplish this task. However, also a ground grid for digital circuitry can provide low-impedance signal return paths on a two-layer board and does not require the additional cost of a ground plane. Power should be routed over (under) or next to the ground, whenever possible. The power lines typically contain the most high-frequency noise in a digital system. Therefore routing power directly over ground results in a path with low inductance and minimized radiating loop area. Routing power and ground next to each other is the next best alternative. Additionally, series filters, such as ferrites or inductors, often prove helpful for reducing noise on power supply routes. A π configuration can be used on the V CC pin. Also, the ferrite should be located very close to the pin of the IC, in order to keep the noise off the PCB trace. A solid ground area under the IC becomes a ground island for the RF noise made by the IC. It provides a low inductance path and minimized radiating loop area. The ground should be connected to IC ground and the bypassing capacitor ground. 4-31 31

EMI - PCB Design Guidelines: Power & Grounds (2) Multilayer board A: Poor - buried trace cuts ground plane into two parts B: Better - buried trace around the perimeter; best is no trace at all in the ground plane C: Poor - Slot cuts up ground plane, focuses slot antenna radiation into that connection D: Better - Ground plane extends between 100 mil centers DDS\Criteria GB Aug96 The closest approximation to having a ground plane in a 2 layer board comes from gridding the ground. The following guidelines are meant to maintain the advantages gained with a ground plane or ground gridding: - Pay upmost attention to how the holes and cutouts on planes are done. They break up the plane and therefore cause increases in loop areas. - Avoid buried traces in the ground plane. If you have to use them, put them in the upper side of PCB. See A and B in above figure. - When making through-holes for sockets or connectors in the plane, place a small trace between each pin. Breaking up a plane with a row of holes is much, much better than having a long slot. See C and D in above figure. - When splitting the ground plane up to make, say a digital and power ground, make sure that the signals connected to the IC are still located entirely over the digital ground. Extending signals over the power ground hurt, because the power ground does not work to reduce the loop area for digital noise signals. 4-32 32

EMI - PCB Design Guidelines: Power & Grounds (3) Power Distribution power digital lines analog signal digital lines analog fair * fair poor fair poor poor poor poor fair poor fair poor *short traces DDS\Criteria GB Aug96 In a mixed-signal environment digital and analog parts should be separated from each other and connected only at a low-impedance ground node. This configuration will reduce coupling of digital noise onto sensitive analog circuitry. Digital grounds should be designed to return high frequencies through a low impedance path, and analog grounds should normally be designed to return low frequency current or DC to its origin through a low-resistance path. For digital signals, ground plane or alternatively ground grid can provide lowimpedance signal return path for high-frequency noise. Contrary to the star point scheme, ground grid (plane) is best in order to reduced RF noise and overall costs. For analog circuitry a star-point grounding scheme is often better, in order to avoid the presence of ground loops. The star point (parallel connection) or the multi-point (series connection) provides the cleanest current return path for analog signals. Star point connection is best, in order to avoid ground loops, but more expending to design on PCB. Multi-point is less desireable, but easier to design. Thus, a star point should be used for the most sensitive analog signals, and multipoint can be used for less sensitive analog devices. Star point grounding is also preferred for noisy or high-power circuitry. 4-33 33

EMI - PCB Design Guidelines: Board Zoning Place high-speed IC close to power supply, with slower components located further away, and analog components even further still; Place oscillator tank loops away from analog circuits, low-speed signals and connectors; Build a gridded or solid ground between the IC, volt. reg and Vcc input, and tie the shield in at that point; Locate the IC next to the volt. reg and the volt. reg next to where Vcc comes on the board; Don t design in cable assemblies that fold over oscillators or high-speed devices. DDS\Criteria GB Aug96 Board zoning (or floor-planning) a PCB is the first step towards designing EMC. Board zoning consists of creating zones on the PCB for analog, digital and noisy components and providing proper space for grounding. Also, devices should be arranged to minimize routing distances of EMI-critical signals, such as clocks, power, cabling and control signals. High-speed ICs are placed close to the power supply, with slower components located further away, and analog components even further still. In this fashion the high-speed logic has less the chance to pollute other signal traces. Of special note, oscillator tank loops should be placed away from analog circuits, low speed signals and connectors. 4-34 34

EMI - PCB Design Guidelines: Cable & Connectors At the system level RF noise is radiated via cables interconnecting the PCBs RF energy becomes critical if return path has high RF impedance - reduce RF impedance in the ground wire - use several ground wires Crosstalk in cables is the same as in PCBs - therefore run clocking or other high-speed wires twisted with their own separate return As for number of returns: - best is tu run 1 ground return for each signal in the cable, as twisted pair - never run less than 1 ground for every 9 signal lines - cables over 30 cm long should be 1/4 ground lines - whenever possible, use a solid metal bracket soldered between the two boards DDS\Criteria GB Aug96 The problem at the system level becomes the radiation due to cables interconnecting the PCB with any off board support function or other processor or display and keypad PCBs. Since there is usually only one ground wire between boards, this one inductive wire has to return all of the RF energy carried into the second PCB by the other (signal) wires. If there is any impedance in the one ground wire (e.g. connector), a portion of the RF energy will not return to the IC s PCB via the ground wire, but rather through a radiated path. It will radiate off the second board and couple back to the first, but during that process that radiation can add noise in other locations in the system. The key corrective action is to insure the conducted path for the return has a very low RF impedance. For low speed data transmission it is common practice to have at least 1 ground for every 9 signal lines in a cable or harness. The number is moving towards 1:5 with higher speeds. The best is to run 1 ground return for each signal line in cable, as twisted pair. Whenever possible, there should be a solid metal bracket, used as a mechanical brace, soldered between the two boards that serves both as a mounting brackets and as a robust RF ground return. 4-35 35