Audio Frequency Analyzer Hardware Description by Brandon Smith 4/29/03 Western Washington University Electronics Engineering Technology 1
Table of Contents List of Figures 3 List of Tables 3 Introduction 4 Circuit Descriptions Analog Front End 4 Microcontroller 5 LED Rear End 6 Power / Utility Circuits 8 Parts Lists System Parts List 10 Primary PCB Parts List 11 Display PCB Parts List 13 2
List of Figures Figure 1: System Diagram for Audio Frequency Analyzer 4 Figure 2: 9S12 Memory Map (Normal Single Chip Mode) 6 Figure 3: LED Bar Graph Layout 7 List of Tables Table 1: LM1117 Load/Regulation Test 8 Table 2: 9S12 Power Pins and Capacitors 8 Table 3: System Schematic Parts List 10 Table 4: Primary PCB Schematic Parts List 11 Table 5: Display PCB Schematic Parts List 13 3
Introduction The Audio Frequency Analyzer (AFA) is a home entertainment device that displays the signal strength of a stereo signal at selected frequencies. The product makes use of a Digital Signal Processing (DSP) algorithm to accomplish this task. The AFA itself is mounted in a box compatible with typical home entertainment centers. It is designed to be stacked among other home audio equipment, such as CD players, radio tuners, and stereo receivers. The user watches the signal strength of the audio signal on a LED bar graph mounted in the front of the product. The user is also responsible for operating the ON/OFF switch located on the front of the product, and applying a stereo signal and power line to the back of the product. This document will describe the hardware necessary to implement the AFA. The primary portions of the AFA, and a conceptual view of how the system operates, is shown in Figure 1. The AFA has four primary blocks of hardware, which include the Analog Front End, Microcontroller, LED Rear End, and Power/Utility Circuits. Analog Front End The Analog Front End (AFE) conditions the audio signal for sampling by the microcontroller through its ATD port. The functions of the AFE include combining the stereo signal into a single audio signal, sending it through a low-pass filter to eliminate aliasing errors, and biasing the audio signal at 2.5V. Once this has been done, the signal is sent directly to the microcontroller block. All parts mentioned in the description of the AFE are located on the Primary PCB Schematic (page evildead). The user provides the audio signal through a 3.5mm female stereo jack, J2, located at the back of the product. J2 must be located on the back edge of its PCB to align with the back of the product. From the stereo jack, the audio ground is routed into the analog ground line. The left and right signals are sent through coupling capacitors (C1,2) to the MAX274 (U1). 4
The MAX274 accomplishes the summing, filtering, and biasing functions required of the AFE. It comprises a single 24-pin DIP that is separated into four 2 nd -order active filters. Each filter is the equivalent of four op-amps, two of which with permanent feedback capacitors. Leads are brought out to allow the filters to be programmed with external resistors. Each filter requires up to four programming resistors, although one can be omitted and reduce the filter to a single pole. To program the MAX274, Maxim IC has provided a computer program that allows the engineer to graphically determine the response of the IC. In the AFE, the MAX274 is programmed for a Chebychev pass band and a cutoff frequency of 14 khz. The signal is suppressed 50 db by 23.3 khz. The Chebychev response was chosen for its extra-sharp roll off at the cutoff frequency, preserving as much power at 14 khz as possible. The phase relationship that Chebychev filters create is not important, since a phase difference of even 180 0 at over 14 khz is not visible to the human eye. An important stipulation for the MAX274 is the type of resistors used to program the IC. Carbon resistors are acceptable, although metal film resistors are recommended by Maxim. Maxim states that the operation of the filters cannot be guaranteed if wire-wound resistors are used. Resistors R1-17 are used to program the MAX274. R1 and R2 are the parallel combination of the input resistor, used to sum the left and right audio signals at the input to the MAX274. When operated from a single 5V supply, the IC s ground is actually at 2.5V. Therefore, the MAX274 accomplishes a 2.5VDC bias internally. The signal seen at the output of the MAX274 is routed directly to an ATD channel on the microcontroller. The supply current drawn by the MAX274 is specified at a maximum of 60mA (30mA into V- and V+ each), with a typical current specified at a total of 40mA. Microcontroller The microcontroller used for the AFA is Motorola s MC9S12DP256 (U2). This microcontroller is configured to operate at a bus speed of 24 MHz, and uses the ATD and serial communications ports. The 9S12 is located on the Primary PCB, in company with the AFE and power conditioning circuits. The 9S12 is a square surface-mount package with 112 pins (package designated LQFP by Motorola). The audio signal from the AFE is received by the microcontroller through AN00 (ATD Module 0, pin 0). The rest of the ATD pins are tied low to reduce power consumption. All other unused pins are left unconnected. The 9S12 s power and utility circuits are described in the Power/Utility Circuits section below. The microcontroller will sample AN00 at 37.3 khz, which more than fulfills the Nyquist criteria for the highest frequency of interest (14.0 khz). The I/O resources used on the 9S12 include ATD Module 0 and SPI Module 0. The BDM circuit requires the following pins: RESET_L (42), BKGD (23), PE4/ECLK (39), PE5/MODA (38), and PE6/MODB (37). The TEST (48) pin is tied to ground. 5
The memory resources on the 9S12 include 12k bytes of erasable EEPROM, 12k bytes of RAM, and up to 256k bytes of paged Flash ROM. The erasable EEPROM will not be required, and program code will be kept in Flash ROM starting at $4000. The memory map can be seen in Figure 2. The DSP algorithm requires a host of variables that will be kept in RAM. The 9S12 operates at a maximum bus frequency of 25 MHz, which can be generated by the 9S12 s internal Phase-Locked Loop (PLL) circuit. The PLL s frequency generator is governed by a control register with pre-set divide/multiply options. In effect, the 9S12 accepts the signal of an external crystal and multiplies it depending on the setting of the PLL control registers. With the selected 16 MHz crystal, the PLL s best multiplying factor will bring the bus speed up to 24 MHz, which is the speed set for the 9S12 in this product. The microcontroller will operate on the audio signal and generate information to send to the display, located on the LED Rear End. This is done with SPI0, and uses the pins SS0_L (96), SCK0 (95), and MOSI0 (94). A return data line from the LED driver is not required. The LED driver accepts a maximum data frequency of 10 MHz. The 9S12 must divide its SPI transmission rate to come within this specification, and the best frequency divisor results in a data rate of 6.25 MHz. The LED driver also requires 16-bit word transmissions. Previous HC12 microcontrollers required software and hardware changes to accomplish large-word transmissions. The hardware requirement was that a general-purpose output pin would be used to manually control the chipselect line. The 9S12 is capable of producing large-word transmissions without external rewiring. The 3-wire SPI transmission, along with +5V and the digital ground line, are sent into a 5-wire plug (P1), which connects with a ribbon cable (J2,3 on System Schematic) to the LED Rear End. The 9S12 is specified for a maximum of 65mA into its V DD power pins, plus current sourced by I/O pins (25mA max each). LED Rear End The LED Rear End is situated on its own PCB for ease of display purposes. Please see the Display PCB Schematic attached to this document for part numbers. The devices mounted on 6
this PCB are limited to a single connecting plug (P1), the LED driver (U1), two capacitors (C1,2), a single resistor (R1), and forty LEDs (LED1-40). This reduced package allows the PCB to be designed and placed in a position to display its LED bar graphs. The SPI transmission out of P1 connects to the LED Driver, which is Maxim s MAX7221. This IC is a 24-pin DIP that is suited to drive 8-segment LED digit displays. The driver operates with two sets of lines Segment lines and Digit lines. Segment lines source current and are labeled SEG DP, A, B, C, D, E, F, and G. Digit lines sink current and are labeled DIG0, 1, 2, 3, 4, 5, 6, and 7. The LED array is composed of green LEDs measuring 3mm in diameter and with a forward voltage drop of 2.0-2.2V at 20mA. They are arranged in five eight-lamp bar graphs, with each bar graph sunk by a single Digit line. Each LED has a specific coordinate of Segment and Digit lines, allowing discrete control of the lamps. The driver will turn on lamps based on a pulsed rotation through the Digit lines. With this method, power consumption is reduced, and the activated lamps are pulsed too fast for the human eye to notice. The LEDs must be arranged as they are shown on the Display PCB Schematic. Each LED bar graph is connected to a single Digit line, with the LED array following the scheme shown in Figure 3. The MAX7221 SPI transmission protocol separates the 16-bit word into two parts an eight-bit address word and an eight-bit data word. The address word activates either the Digit or control registers located inside the IC, while the data words contain the information to be sent to each register. For example, to turn on the LED connected to SEGB, DIG3, the address word would contain the address to the DIG3 register (0x04), and the data word would be 0x20. The resulting transmission would be 0x0420. Intensity control is accomplished by a master current-limiting resistor (R1) connected to ISET (18), and by an intensity control register. The register allows software to scale the intensity from 1/16 to 15/16 of its maximum value. Other control registers include a shutdown mode, which the MAX7221 enters on power-on. The IC requires 250 usec to leave shutdown mode, but can receive information to its registers during that time. No external hardware is required to manage the shutdown state it is controlled only by software. A scan control register allows software to prevent specified Digit lines from being scanned, thereby conserving power for unused Digit lines. Another register allows software to test the display by turning on all LEDs. 7
The MAX7221 draws a typical supply current of 330mA when driving sixty-four LEDs and operates on the +5V power supply and digital ground. Power/Utility Circuits The power and utility circuits are defined as the circuits that provide power to the AFA, and circuits that do not carry intelligence signals. In this case, they are limited to circuits that support the microprocessor. All electronic devices in the AFA operate from 0 to 5V. Power is supplied by an unregulated 9VDC, 1A wall transformer that connects to a 2.1mm center-pin power jack (J1 on System Diagram Schematic). The power circuit is completed by a single-pole single-throw switch (SW1), mounted on the front of the product. The power lines then connect to plug P1, which connects to a jack (J3 on Primary PCB Schematic) mounted on the Primary PCB. A linear low-dropout regulator, National s LM1117T-5.0 (U5), provides the system s +5V. It requires C7 and C8 for stability and regulation. The regulator was placed under a load/regulation test, with the results tabulated in Table 1. The regulator s maximum rated current supply is 800mA. The regulator, in a 3-pin TO-220 package, requires a small heat sink kit. The complete product, at rest, draws between 80 and 85mA. With all LEDs on and an audio signal running through the Analog Front End, the system draws slightly less than 300 ma. A single +5V line is used by all devices on the Primary PCB. Two ground lines are also used one analog ground and one digital ground. This separation is intended to reduce noise coupling between digital and analog devices. The analog ground line is only used by the Analog Front End s MAX274 and incoming audio ground. The digital ground line applies to everything else. The two ground lines meet at the voltage regulator. When used off a single +5V supply, the MAX274 requires a special power conditioning circuit. A finely tuned voltage divider, created from R18,19 and C3,4,5,6, creates a center voltage of 2.5V. Therefore, from the 5V point of view, GND becomes the IC s V-, 2.5V becomes the IC s ground, and 5V becomes the IC s V+. This power supply circuit was recommended by Maxim. For best operation, R18,19 and C3,4,5,6 must be as close to the MAX274 as possible. The power circuits for the microcontroller include capacitors arranged all around the IC. Table 2 shows the 9S12 s power pin groups and the capacitors that bias them. Other power requirements for the 9S12 include a twopole filter tied to +5V for XFC (44) to power the on-chip PLL. This filter is made of R21 and C20,21. Power (+5V and digital ground) is sent to the Display 8
PCB through the 5-wire cable that also carries the SPI transmission from the 9S12. This supply is conditioned by C1 and C2 on the Display PCB Schematic. Utility circuits in the AFA are limited to a couple support circuits for the microcontroller. The crystal oscillator (X1), produced by Fox Electronics, is specified at 16 MHz with a frequency tolerance of 30ppm. The crystal is biased with capacitors C18 and C19. The microcontroller requires a BDM connection for programming. The connecting pins (J1) are arranged so that the standard 6-pin BDM ribbon cable can be placed over one end of the pin array, and the signals ECLK, GND, MODA and MODB are accessible on the remaining pins. The BDM line requires power, ground, BKGD, and RESET_L. These lines are supported by resistors R24-26 as required by BDM standards. A low-voltage reset circuit is tied to the 9S12 s reset line. The reset IC is Maxim s MAX6348UR46-T (U3), which comes in a 3-pin surface mount package and has a voltage threshold of 4.630V. The output line is tied high with R20. 9
Table 3: System Schematic Parts List 10
Table 4: Primary PCB Schematic Parts List 11
Table 4: Primary PCB Schematic Parts List cont. 12
Table 5: Display PCB Schematic Parts List 13