Programming Xilinx SPARTAN 3 Board (Simulation through Implementation) January 2007 Prepared by: Oluwayomi Adamo Class: Project IV University of North Texas
FPGA Physical Description 4 5 1 15 3 12 14 13 6 2 8 11 10 9 7 1. VGA (HD-15) Monitor Port 2. 9-pin (DB-9) 3. Power Connector 4. A1 Expansion Port 5. A2 Expansion Port 6. B1 Expansion Port 7. PS/2 Port 8. Seven Segment Displays 9. Switches (8) 10. Buttons (4) 11. LEDs (8) 12. Power LED 13. Spartan 3 FPGA Core 14. Program LED (Lit when the FPGA is programmed) 15. JTAG Port (used to program the FPGA)
Programming Xilinx Board (Spartan 3) Tutorial Using ISE 8.1i Tutorial prepared by Oluwayomi Adamo Introduction This tutorial shows you how to program Spartan 3 FPGA board using Xilinx ISE 8.1i. As an example, a half adder circuit will be implemented on the Spartan 3 board. The tutorial begins by showing you how to create a new project and how to describe the digital circuit in VHDL. After the circuit s functionality has been verified, it is then downloaded to the Spartan 3 board for implementation. You are encouraged to try out the examples before embarking on any exercise. Creating a new Project and Source Start the Xilinx ISE 8.1i project navigator by double clicking the Xilinx ISE 8.1i icon on your desktop. Xilinx ISE 8.1i.lnk Click on File and select New Project
Select a project location and type the name you would like to call your project HalfAdder : Click Next Select the device family, device, package, and speed grade as shown below:
Click Next Click New Source Select VHDL Module in the New Source Wizard window:
Click Next Specify the inputs and outputs of your design (HalfAdder). This is used to generate a template for your VHDL code. Click Next
Click Finish if you are satisfied your specifications shown in the summary page Click Next
Click Next Verify the information on the Project Summary window: Click Finish. Double-click on HalfAdder-Behavioral(HalfAdder.vhd) tab in the Sources pane.
Include an enable input in your entity and it should be 1 bit wide. Complete the architectural part of your VHDL code.
Simulating your code Click on the + sign beside synthesize XST and double click on check syntax. If your code does not have an error, the message Process Check Syntax completed successfully will be displayed.
Double-click on Create New Source in the Process pane in the left of the window. Click on VHDL Test Bench and specify the file name for the test bench. Click Next.
Click on the Source with which to associate the test bench. Verify the summary of your test bench and click Finish. Click Finish if you are satisfied your specifications shown in the summary page.
At the tb: process portion of the test bench, specify the test cases you will like to verify.
Click on the drop down button at the Sources pane window in the left of the window and click on behavioral simulation. Click on the + sign beside ModelSim Simulator. Double click on Simulate Behavioral Model.
Click on the wave tab and undock to view the waveform. Verify the correctness of your waveform.
Congratulation, you have verified your design. It is time to implement on FPGA board.
Implementation Specify the pins you would like the inputs and outputs to be connected to. Double-click on Assign Package Pins in the Process pane in the left of the window. Note: You may be asked to save your VHDL code. Your design will be checked for syntax error. If you have any error, make sure you fix them before proceeding. Click Yes.
Click Yes. The Pace editor is loaded. You can select Package View tab at the bottom of the right pane. The package view gives a better view of the physical FPGA package).
Type in the desired pin names for each signal in the Design Object List at the left in the Loc column Click File and Save. Click File and Exit. Note: The following dialog may appear when saving the file: Click on Don t show this dialog again.
Click Ok. View the UCF file by double-clicking Edit Constraints (Text) in the project Navigator window.
Programming the Board In the Project Navigator window, double-click on HalfAdder-Behavioral (HalfAdder) tab in the Sources pane.
Right-click on Generate Programming File in the Processes pane. Select Properties. In the Process Properties windows, Select Startup Options tab. Change FPGA Start-UP Clock to JTAG Clock
Click Apply. Click Ok. In the Processes window, click on the + sign by Generate programming file. Double-click on Configure Device (impact). This opens the impact tool and a wizard for creating a new configuration.
Click Finish.
Assign New Configuration File window opens. Select the name of your select the.bit file (HalfAdder.bit). Click Open. click Bypass.
You will now be at the main impact window: Right-click on the FPGA ( xc3s200 ). select Program.
Make sure that Verify is not checked. Click Apply. Click Ok. The FPGA is now being programmed as shown: