Challenges in the deployment of Ethernet for Automotive Infotainment Systems 25 September 2013 Thomas Gmeinder (XMOS) Christian Sörensen (Intel)
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Agenda System overview Automotive requirements Evaluation project overview standards implementation clock recovery Automotive adaptions results Conclusions Slide 3
System overview Slide 4
Automotive Requirements Early audio /video synchronization across multiple network endpoints (Lip-sync) Switching between talker streams Many audio channels Cost reduction Low latency Flexibility in network topology, media stream routing Slide 5
Evaluation project overview Evaluate the challenges of an automotive system Goal: a usage model of the standard, which fulfills the automotive requirements We followed the recommendations of the AVnu Automotive TWG (automotive profile) Evaluation system based on: XMOS Endpoint Kit Intel Atom processor running Tizen Intel I210 Ethernet controller, Open Slide 6
Evaluation system diagram Head Unit Endpoint L0 Amplifier Endpoint T1 L1 Xtal T0 Switch Clock Slaves Clock Master T2 L2 RSE Endpoint Slide 7
Evaluation system diagram Head Unit Endpoint L0 Amplifier Endpoint Stream 1 8ch T1 L1 Xtal Clock Master T0 2ch Stream 0 Switch Clock Slaves T2 L2 RSE Endpoint Slide 8
standards implementation 802.1Qav 802.1AS (PTP) IEEE 1722 802.1Qat (SRP) * Head Unit Endpoint XMOS Endpoint T1 L1 L0 Xtal T0 Switch Clock Slaves Clock Master * StaRc during startup, dynamic to switch streams Slide 9
clock distribution Identify source and destination audio clock domains throughout the system Identify points where resampling and/or hardware clock recovery is required Optimization steps: Minimize amount of resampling Minimize instances of clock recovery circuits Optimization results: Use one audio master clock throughout system Resample to audio master clock as close to source as possible Slide 10
Example audio clock domains Slide 11
Clock distribution concept RR: /Video synchronization across multiple multiple network endpoints (Lip-sync) Slide 12
Amplifier endpoint network MulRcore microcontroller T L PTP Time Present. Time Actual Time Clock ery TDM audio signals Clock Slave Slide 13
Clock recovery control loop XMOS MMCU" " IllustraRng the Error e(t) : Slide 14
PTP clock synchronization Measured between Intel I210 and XMOS EP 802.1AS (gptp) Synchronization Jitter : +/- 30ns Intel Disclaimer: SoXware and workloads used in performance tests may have been oprmized for performance only on Intel microprocessors. Performance tests are measured using specific computer systems, components, soxware, operarons and funcrons. Any change to any of those factors may cause the results to vary. You should consult other informaron and performance tests to assist you in fully evaluarng your contemplated purchases, including the performance of that product when combined with other products. Slide 15
Startup acceleration Automotive profile of SRP: Static configuration of SRP parameters to accelerate startup Preconfigured SRP Still utilizes SRP for dynamic stream switching in a deterministic and safe manner PTP: No BMCA Use cached parameters at startup Accelerated sync messages RR: Early Slide 16
Low latency requirements Hands free phone: VDA specification for car hands-free terminals: 50ms delay from GSM System Output to Drum Reference Point (DRP) processing: Noise/echo cancellation In-car passenger communication Class A Traffic: Default 2 ms Class B Traffic: Default 50 ms Result: Low latency class A is required RR: Low Latency Slide 17
Dynamic stream switching Head Unit Endpoint L0 Amplifier Endpoint Stream 1 8ch Listener Leave T1 L1 Xtal Clock Master T0 2ch Stream 0 Switch Clock Slaves T2 L2 RSE Endpoint Slide 18
Dynamic stream switching Head Unit Endpoint L0 Amplifier Endpoint Stream 1 8ch T1 L1 Xtal T0 Switch Talker AdverRse Clock Slaves Clock Master Talker AdverRse T2 L2 RSE Endpoint Slide 19
Dynamic stream switching Head Unit Endpoint L0 Amplifier Endpoint Stream 1 8ch Listener Join T1 L1 Xtal T0 Switch Clock Slaves Clock Master T2 L2 RSE Endpoint Slide 20
Dynamic stream switching Head Unit Endpoint L0 Amplifier Endpoint Stream 1 8ch T1 L1 Xtal T0 Switch Clock Slaves Clock Master RR: Stream 2 - Switching between Media Talker Streams - Flexibility in Network Topology and Media Stream routing. RSE Endpoint 6ch T2 L2 Slide 21
Hardware requirements clock support Adjustable oscillator for media clock Accurate time-stamping PTP Packets in the Mac Samples in the Interface (Input) Processing IEEE 1722 packets at a high frequency 8000 per Stream: amp receives 48000 per second Handle multiple timing critical tasks that interact Slide 22
Improved network utilization Bandwidth required for 40 channels on 6 streams: Format Required Bandwidth Suitable? ** 61883-6 89.1 Mbit/s No AVTP SAF 24bit* 71 Mbit/s OK AVTP SAF 16bit* 55.3 Mbit/s Yes * AVTP SAF as specified in P1722a-D4.pdf ** Bandwidth Limit is 75MBit on 100Mbit link Improvements: SAF 16bit relaxes bandwidth requirement by 38% Multiplexed streams improve network utilization further Enables use of 100Mbit BroadR-Reach! RR: - Many Channels - Cost Reduction Slide 23
Conclusions can meet automotive requirements with a carefully implemented automotive profile AVnu TWG currently working on standardization. Clock synchronization and deterministic timing solves the lip-sync problem Good QoS for high-end infotainment is provided by traffic shaping, clock synchronization and low latency IEEE 802.1Qat (SRP) is useful for controlling the dynamic switching between different Talker streams in a deterministic and safe manner Slide 24
Thank you! Slide 25