FEATURES DESCRIPTION TimerBox: Resettabe, Low Frequency Osciator n Period Range: 1ms to 9.5 Hours n Configured with 1 to 3 Resistors n <1.5% Maximum Frequency Error n Output Reset Function n.5 to 5.5 Singe Suppy Operation n 55μA to 8μA Suppy Current (ms to 9.5hr Cock Period) n 5μs Start-Up Time n CMOS Output Driver Sources/Sinks ma n 55 C to 15 C Operating Temperature Range n Avaiabe in Low Profie (1mm) SOT-3 (ThinSOT ) and mm 3mm DFN Packages APPLICATIONS n Heartbeat Timers n Watchdog Timers n Intervaometers n Periodic Wake-Up Ca n High ibration, High Acceeration Environments n Portabe and Battery-Powered Equipment L, LT, LTC, LTM, Linear Technoogy, TimerBox and the Linear ogo are registered trademarks and ThinSOT is a trademark of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. The LTC 6991 is a siicon osciator with a programmabe period range of 1.4ms to 9.54 hours (9.1μHz to 977Hz), specificay intended for ong duration timing events. The is part of the TimerBox famiy of versatie siicon timing devices. A singe resistor, R, programs the s interna master osciator frequency. The output cock period is determined by this master osciator and an interna frequency divider, N, programmabe to eight settings from 1 to 1. t = N R 5kΩ 1.4ms, N = 1,8,64,..., 1 In norma operation, the osciates with a 5% duty cyce. A reset function is provided to truncate the puse (reducing the duty cyce). The reset pin can aso be used to prevent the output from osciating. The and pins can be configured for active-ow or active-high operation using a poarity function. POL BIT PIN PUT STATE Osciating 1 (reset) 1 1 (reset) 1 1 Osciating For easy configuration of the, downoad the TimerBox Designer too at www.inear.com/timerbox. TYPICAL APPLICATION Low Frequency Puse Generator Cock Period Range over Eight Divider Settings 1Hr 1Hr R PW.6k C PW 47pF R 715k t PULSE R PW PW 1μs 1M 39k 5.1μF 1μs PULSE WIDTH 6 SECONDS 6991 TA1a CLOCK PERIOD (LOG SCALE) 1Min 1Min 1Sec 1Sec 1ms 1ms 1ms.65 1.5 1.875 PIN OLTAGE, ().5 6991 TA1b 1
ABSOLUTE MAXIMUM RATINGS (Note 1) Suppy otage ( ) to...6 Maximum otage on Any Pin... (.3) PIN ( +.3) Operating Temperature Range (Note ) C... 4 C to 85 C I... 4 C to 85 C H... 4 C to 15 C MP... 55 C to 15 C Specified Temperature Range (Note 3) C... C to 7 C I... 4 C to 85 C H... 4 C to 15 C MP... 55 C to 15 C Junction Temperature... 15 C Storage Temperature Range... 65 C to 15 C Lead Temperature (Sodering, 1 sec) S6 Package...3 C PIN CONFIGURATION TOP IEW 1 3 7 6 5 4 1 3 TOP IEW 6 5 4 DCB PACKAGE 6-LEAD (mm 3mm) PLASTIC DFN T JMAX = 15 C, θ JA = 64 C/W, θ JC = 1.6 C/W EXPOSED PAD (PIN 7) CONNECTED TO, PCB CONNECTION OPTIONAL S6 PACKAGE 6-LEAD PLASTIC TSOT-3 T JMAX = 15 C, θ JA = 19 C/W, θ JC = 51 C/W ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE CDCB#TRMPBF CDCB#TRPBF LDWZ 6-Lead (mm 3mm) Pastic DFN C to 7 C IDCB#TRMPBF IDCB#TRPBF LDWZ 6-Lead (mm 3mm) Pastic DFN 4 C to 85 C HDCB#TRMPBF HDCB#TRPBF LDWZ 6-Lead (mm 3mm) Pastic DFN 4 C to 15 C CS6#TRMPBF CS6#TRPBF LTDWY 6-Lead Pastic TSOT-3 C to 7 C IS6#TRMPBF IS6#TRPBF LTDWY 6-Lead Pastic TSOT-3 4 C to 85 C HS6#TRMPBF HS6#TRPBF LTDWY 6-Lead Pastic TSOT-3 4 C to 15 C MPS6#TRMPBF MPS6#TRPBF LTDWY 6-Lead Pastic TSOT-3 55 C to 15 C TRM = 5 pieces. *Temperature grades are identified by a abe on the shipping container. Consut LTC Marketing for parts specified with wider operating temperature ranges. Consut LTC Marketing for information on ead based finish parts. For more information on ead free part marking, go to: http://www.inear.com/eadfree/ For more information on tape and ree specifications, go to: http://www.inear.com/tapeandree/
ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 5 C. Test conditions are =.5 to 5.5, =, CODE = to 15 (N = 1 to 1 ), R = 5k to 8k, R LOAD = 5k, C LOAD = 5pF uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t Output Cock Period 1.4m 34,36 Seconds f Output Frequency 9.1μ 977 Hz Δf Frequency Accuracy (Note 4) 9.1μHz f 977Hz ±.8 ±1.5 % ±. % Δf /ΔT Frequency Drift Over Temperature ±.5 %/ C Δf /Δ Frequency Drift Over Suppy = 4.5 to 5.5 =.5 to 4.5 Long-Term Frequency Stabiity (Note 11) 9 ppm/ khr Period Jitter (Note 1) N = 1 N = 8.3.6 15 7.55.16 %/ %/ ppm RMS ppm RMS BW Frequency Moduation Bandwidth.4 f Hz t S Frequency Change Setting Time (Note 9) 1 Cyce Anaog Inputs otage at Pin.97 1. 1.3 Δ /ΔT Drift Over Temperature ±75 μ/ C R Frequency-Setting Resistor 5 8 kω Pin otage Δ /Δ Pin aid Code Range (Note 5) Deviation from Idea ±1.5 % / = (CODE +.5)/16 Pin Input Current ±1 na Power Suppy Operating Suppy otage Range.5 5.5 Power-On Reset otage 1.95 I S Suppy Current R L =, R = 5k = 5.5 =.5 R L =, R = 1k = 5.5 =.5 R L =, R = 8k = 5.5 =.5 135 15 1 8 65 55 17 135 13 15 1 85 μa μa μa μa μa μa 3
ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 5 C. Test conditions are =.5 to 5.5, =, CODE = to 15 (N = 1 to 1 ), R = 5k to 8k, R LOAD =, C LOAD = 5pF uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digita I/O Pin Input Capacitance.5 pf Pin Input Current = to ±1 na IH High Leve Pin Input otage (Note 6).7 IL Low Leve Pin Input otage (Note 6).3 I (MAX) Output Output Current =.7 to 5.5 ± ma OH High Leve Output otage (Note 7) = 5.5 I = 1mA I = 16mA = 3.3 I = 1mA I = 1mA =.5 I = 1mA I = 8mA OL Low Leve Output otage (Note 7) = 5.5 I = 1mA I = 16mA = 3.3 I = 1mA I = 1mA =.5 I = 1mA I = 8mA t Reset Propagation Deay = 5.5 = 3.3 =.5 t WIDTH Minimum Input Puse Width = 3.3 5 ns t r Output Rise Time (Note 8) = 5.5 = 3.3 =.5 t f Output Fa Time (Note 8) = 5.5 = 3.3 =.5 5.45 4.84 3.4.75.17 1.58 5.48 5.15 3.7.99.1 1.88..6.3..3.6 16 4 4 1.1 1.7.7 1. 1.6.4.4.54.5.46.7.54 ns ns ns ns ns ns ns ns ns Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note : The C is guaranteed functiona over the operating temperature range of 4 C to 85 C. Note 3: The C is guaranteed to meet specified performance from C to 7 C. The C is designed, characterized and expected to meet specified performance from 4 C to 85 C but it is not tested or QA samped at these temperatures. The I is guaranteed to meet specified performance from 4 C to 85 C. The H is guaranteed to meet specified performance from 4 C to 15 C. The MP is guaranteed to meet specified performance from 55 C to 15 C. Note 4: Frequency accuracy is defined as the deviation from the f equation, assuming R is used to program the frequency. Note 5: See Operation section, Tabe 1 and Figure for a fu expanation of how the pin votage seects the vaue of CODE. Note 6: The pin has hysteresis to accommodate sow rising or faing signas. The threshod votages are proportiona to. Typica vaues can be estimated at any suppy votage using (RISING).55 + 185m and (FALLING).48 155m. 4 Note 7: To conform to the Logic IC Standard, current out of a pin is arbitrariy given a negative vaue. Note 8: Output rise and fa times are measured between the 1% and the 9% power suppy eves with 5pF output oad. These specifications are based on characterization. Note 9: Setting time is the amount of time required for the output to sette within ±1% of the fina frequency after a.5 or change in I. Note 1: Jitter is the ratio of the deviation of the period to the mean of the period. This specification is based on characterization and is not 1% tested. Note 11: Long-term drift of siicon osciators is primariy due to the movement of ions and impurities within the siicon and is tested at 3 C under otherwise nomina operating conditions. Long-term drift is specified as ppm/ khr due to the typicay noninear nature of the drift. To cacuate drift for a set time period, transate that time into thousands of hours, take the square root and mutipy by the typica drift number. For instance, a year is 8.77kHr and woud yied a drift of 66ppm at 9ppm/ khr. Drift without power appied to the device may be approximated as 1/1th of the drift with power, or 9ppm/ khr for a 9ppm/ khr device.
TYPICAL PERFORMANCE CHARACTERISTICS = 3.3, R = k, T A = 5 C uness otherwise noted. ERROR (%) 3 1 1 Frequency Error vs Temperature Frequency Error vs Temperature Frequency Error vs Temperature GUARANTEED MAX OER TEMPERATURE R = 5k 3 PARTS ERROR (%) 3 1 1 GUARANTEED MAX OER TEMPERATURE R = k 3 PARTS ERROR (%) 3 1 1 GUARANTEED MAX OER TEMPERATURE R = 8k 3 PARTS GUARANTEED MIN OER TEMPERATURE GUARANTEED MIN OER TEMPERATURE GUARANTEED MIN OER TEMPERATURE 3 5 5 5 5 75 1 15 TEMPERATURE ( C) 3 5 5 5 5 75 1 15 TEMPERATURE ( C) 3 5 5 5 5 75 1 15 TEMPERATURE ( C) 6991 G1 6991 G 6991 G3 ERROR (%) 3 1 1 3 Frequency Error vs R Frequency Drift vs Suppy otage Typica Distribution GUARANTEED MAX OER TEMPERATURE 3 PARTS GUARANTEED MIN OER TEMPERATURE 4 6 8 R (kω) 6991 G4 DRIFT (%).5.4.3..1.1..3.4.5 REFERENCED TO = 4.5 R = 5k R = k R = 8k 3 4 5 6 SUPPLY OLTAGE () 6991 G5 NUMBER OF UNITS 5 15 1 5.98 LOTS DFN AND SOT-3 174 UNITS.988.996 1.4 1.1 1. () 6991 G6 (m) 1..8.6.4...4.6.8 1. Drift vs I Drift vs Suppy vs Temperature 5 REFERENCED TO I = 1μA 1 15 I (μa) DRIFT (m) 1..8.6.4...4.6.8 1. 3 REFERENCED TO = 4 4 5 6 SUPPLY () () 1. 1.15 1.1 1.5 1..995.99.985.98 5 3 PARTS 5 5 5 75 1 15 TEMPERATURE ( C) 699 G7 6991 G8 6991 G9 5
TYPICAL PERFORMANCE CHARACTERISTICS = 3.3, R = k, T A = 5 C uness otherwise noted. POWER SUPPLY CURRENT (μa) 15 15 1 75 5 5 Suppy Current vs Suppy otage R = 5k R = 1k R = k R = 8k POWER SUPPLY CURRENT (μa) Suppy Current vs Temperature 15 15 5, R = 1k 1.5, R = 1k 75 5, R = 8k 5.5, R = 8k 5 POWER SUPPLY CURRENT (μa) 5 15 1 5 Suppy Current vs Pin otage R = 8k 5 FALLING 3.3 FALLING 5 RISING 3.3 RISING 3 4 5 6 SUPPLY OLTAGE () 5 5 5 5 75 1 15 TEMPERATURE ( C)..4.6.8 1. / (/) 6991 G1 6991 G11 6991 G1 15 Suppy Current vs R Typica I Current Limit vs 1 PIN SHORTED TO 3.5 Threshod otage vs Suppy otage POWER SUPPLY CURRENT (μa) 15 1 75 5 5 = 5 = 3.3 =.5 I (μa) 8 6 4 PIN OLTAGE () 3..5. 1.5 1..5 POSITIE-GOING NEGATIE-GOING 4 6 8 R (kω) 6991 G13 3 4 5 6 SUPPLY OLTAGE () 6991 G15 3 4 5 6 SUPPLY OLTAGE () 6991 G14 PROPAGATION DELAY (ns) 6 5 45 4 35 3 5 15 1 5 Reset Propagation Deay (t ) vs Suppy otage C LOAD = 5pF 3 4 5 6 SUPPLY OLTAGE () 6991 G16 RISE/FALL TIME (ns) 3..5. 1.5 1..5 Rise and Fa Time vs Suppy otage C LOAD = 5pF t RISE t FALL 3 4 5 6 SUPPLY OLTAGE () 6991 G17 DELTA FREQUENCY (ppm) 15 1 5 5 1 15 Typica Frequency Error vs Time (Long-Term Drift) 65 UNITS SOT-3 AND DFN PARTS T A = 3 C 4 8 1 16 4 8 TIME (h) 6991 G17a
TYPICAL PERFORMANCE CHARACTERISTICS = 3.3, R = k, T A = 5 C uness otherwise noted. PUT RESISTANCE (Ω) 5 45 4 35 3 5 15 1 5 Output Resistance vs Suppy Current Typica Start-Up with POL = 1 PUT SOURCING CURRENT PUT SINKING CURRENT 1/ 1/ 5μs 1μs (t MASTER ) WIDE INITIAL PULSE 3 4 5 6 SUPPLY OLTAGE () 6991 G =.5 CODE = 15 R = 5k 5μs/ 6991 G19 PIN FUNCTIONS (DCB/S6) (Pin 1/Pin 5): Suppy otage (.5 to 5.5). This suppy shoud be kept free from noise and rippe. It shoud be bypassed directy to the pin with a.1μf capacitor. (Pin /Pin 4): Programmabe Divider and Poarity Input. A referenced A/D converter monitors the pin votage ( ) to determine a 4-bit resut (CODE). may be generated by a resistor divider between and. Use 1% resistors to ensure an accurate resut. The pin and resistors shoud be shieded from the pin or any other traces that have fast edges. Limit the capacitance on the pin to ess than 1pF so that settes quicky. The MSB of CODE (POL) determines the poarity of the and pins. If POL =, is active-high, and forces ow. If POL = 1, is active-ow and forces high. (Pin 3/Pin 3): Frequency-Setting Input. The votage on the pin ( ) is reguated to 1 above. The amount of current sourced from the pin (I ) programs the master osciator frequency. The I current range is 1.5μA to μa. The output osciation wi stop if I drops beow approximatey 5nA. A resistor connected between and is the most accurate way to set the frequency. For best performance, use a precision meta or thin fim resistor of.5% or better toerance and 5ppm/ C or better temperature coefficient. For ower accuracy appications an inexpensive 1% thick fim resistor may be used. Limit the capacitance on the pin to ess than 1pF to minimize jitter and ensure stabiity. Capacitance ess than 1pF maintains the stabiity of the feedback circuit reguating the votage. R 6991 PF C1.1μF (Pin 4/Pin 1): Output Reset. The behavior of the pin is dependent on the poarity bit (POL). The POL bit is configured via the CODE setting. When POL =, setting high forces ow and setting ow aows the output to osciate. When POL = 1, is active ow. In that case, setting ow forces high and setting high aows the output to osciate. 7
+ PIN FUNCTIONS (DCB/S6) (Pin 5/Pin ): Ground. Tie to a ow inductance ground pane for best performance. (Pin 6/Pin 6): Osciator Output. The pin swings from to with an output resistance of approximatey 3Ω. When driving an LED or other ow impedance oad a series output resistor shoud be used to imit source/ sink current to ma. BLOCK DIAGRAM (S6 package pin numbers shown) 4 5 4-BIT A/D CONERTER DIGITAL FILTER MASTER OSCILLATOR t MASTER = 1μs = 5kΩ I MCLK FIXED IDER 14 POL BIT PROGRAMMABLE IDER 1, 8, 64, 51 496, 15, 18, 1 D R Q PUT POLARITY 6 t HALT OSCILLATOR IF I < 5nA POR INPUT POLARITY I = 1 3 + 1 1 6991 BD I R 8
OPERATION The is buit around a master osciator with a 1MHz maximum frequency. The osciator is controed by the pin current (I ) and votage ( ), with a 1MHz 5k conversion factor that is accurate to ±.8% under typica conditions. f MASTER = 1 t MASTER = 1MHz 5kΩ I A feedback oop maintains at 1 ±3m, eaving I as the primary means of controing the output frequency. The simpest way to generate I is to connect a resistor (R ) between and, such that I = /R. The master osciator equation reduces to: f MASTER = 1 1MHz 5kΩ = t MASTER R From this equation, it is cear that drift wi not affect the output frequency when using a singe program resistor (R ). Error sources are imited to R toerance and the inherent frequency accuracy Δf of the. R may range from 5k to 8k (equivaent to I between 1.5μA and μa). Before reaching the pin, the osciator frequency passes through a fixed 14 divider. The aso incudes a programmabe frequency divider which can further divide the frequency by 1, 8, 64, 51, 496, 15, 18 or 1. The divider ratio N is set by a resistor divider attached to the pin. f = 1MHz 5kΩ 14 N I, or t = 1 f = N 5kΩ I 1.4ms with R in pace of /I the equation reduces to: t = N R 5kΩ 1.4ms CODE The pin connects to an interna, referenced 4-bit A/D converter that determines the CODE vaue. CODE programs two settings on the : 1. CODE determines the output frequency divider setting, N.. CODE determines the poarity of the and pins, via the POL bit. may be generated by a resistor divider between and as shown in Figure 1. 6991 F1.5 TO 5.5 Figure 1. Simpe Technique for Setting CODE Tabe 1 offers recommended 1% resistor vaues that accuratey produce the correct votage division as we as the corresponding N and POL vaues for the recommended resistor pairs. Other vaues may be used as ong as: 1. The / ratio is accurate to ±1.5% (incuding resistor toerances and temperature effects). The driving impedance ( ) does not exceed 5kΩ. If the votage is generated by other means (i.e., the output of a DAC) it must track the suppy votage. The ast coumn in Tabe 1 shows the idea ratio of to the suppy votage, which can aso be cacuated as: CODE+.5 = + 16 ±1.5% For exampe, if the suppy is 3.3 and the desired CODE is 4, =.81 3.3 = 98m ± 5m. Figure iustrates the information in Tabe 1, showing that N is symmetric around the CODE midpoint. 9
OPERATION Tabe 1. CODE Programming CODE POL N RECOMMENDED t (kω) (kω) / 1 1.4ms to 16.384ms Open Short.315 ±.15 1 8 8.19ms to 131ms 976 1.9375 ±.15 64 65.5ms to 1.5sec 976 18.1565 ±.15 3 51 54ms to 8.39sec 1 8.1875 ±.15 4 4,96 4.19sec to 67.1sec 1 39.815 ±.15 5 3,768 33.6sec to 537sec 1 53.34375 ±.15 6 6,144 68sec to 4,95sec 1 681.465 ±.15 7,97,15,147sec to 34,36sec 1 887.46875 ±.15 8 1,97,15,147sec to 34,36sec 887 1.5315 ±.15 9 1 6,144 68sec to 4,95sec 681 1.59375 ±.15 1 1 3,768 33.6sec to 537sec 53 1.6565 ±.15 11 1 4,96 4.19sec to 67.1sec 39 1.71875 ±.15 1 1 51 54ms to 8.39sec 8 1.7815 ±.15 13 1 64 65.5ms to 1.5sec 18 976.84375 ±.15 14 1 8 8.19ms to 131ms 1 976.965 ±.15 15 1 1 1.4ms to 16.384ms Short Open.96875 ±.15 POL BIT = POL BIT = 1 1 7 8 1 6 9 1 5 1 t (SECONDS) 1 1.1.1 1 3 4 11 1 13 14 15.1.5 + INCREASING 6991 F Figure. Frequency Range and POL Bit vs CODE 1
OPERATION Pin and Poarity (POL) Bit The pin contros the state of the s output as seen on the pin. The active/inactive votage eves depend on the POL bit setting. Tabe. Output States POL BIT PIN PUT STATE Osciating 1 (reset) 1 1 (reset) 1 1 Osciating Each period of the s interna osciator cocks the output state atch (see Bock Diagram). The reset pin () can reset or hod off the output atch. The active state of the reset pin is determined by the poarity function (POL). Simiary, the output atch is foowed by a buffer that can invert the output. The output poarity is aso controed by the POL bit. If POL =, the reset pin is active high and the output atch is not inverted. Therefore, puing the pin high wi reset the output atch and force the pin ow. Puing ow wi aow the output to osciate, with the next rising edge dependent on the interna osciator. If POL = 1, the reset pin is active ow and the output atch is inverted. Therefore, puing the pin ow wi reset the output atch and force the pin high. Puing high wi aow the output to osciate, with the next faing edge dependent on the interna osciator. Note that the master osciator frequency and phase are not affected by the pin; The continues to osciate, internay, even when is active. Whie the reset function can bock an output puse, its exact pacement in time can ony be changed by power cycing the. t WIDTH t INTERNAL OSCILLATOR t 6991 F3 Figure 3. Timing Diagram (POL = ) t t INTERNAL OSCILLATOR 6991 F4 Figure 4. Timing Diagram (POL = 1) 11
OPERATION Changing CODE After Start-Up Foowing start-up, the A/D converter wi continue monitoring for changes. The wi respond to CODE changes in ess than one cyce. t CODE < 5 t MASTER < t The output may have an inaccurate puse width during the frequency transition. But the transition wi be gitch-free and no high or ow puse can be shorter than the master cock period. A digita fiter is used to guarantee the CODE has setted to a new vaue before making changes to the output. Start-Up Time When power is first appied, the power-on reset (POR) circuit wi initiate the start-up time, t START. The pin is hed ow during this time. The typica vaue for t START ranges from.5ms to 8ms depending on the master osciator frequency (independent of N ): t START(TYP) = 5 t MASTER During start-up, the pin A/D converter must determine the correct CODE before the output is enabed. The start-up time may increase if the suppy or pin votages are not stabe. For this reason, it is recommended to minimize the capacitance on the pin so it wi propery track. Less than 1pF wi not affect performance. Start-Up Behavior When first powered up, the output is hed ow. If the poarity is set for non-inversion (POL = ) and the output is enabed ( = ) at the end of the start-up time, wi begin osciating. If the output is being reset ( = 1) at the end of the start-up time, the first puse wi be skipped. Subsequent puses wi aso be skipped unti =. In inverted operation (POL = 1), the start-up sequence is simiar. However, the does not know the correct CODE setting when first powered up, so the output defauts ow. At the end of t START, the vaue of CODE is recognized and goes high (inactive) because POL = 1. If = 1 (inactive) then wi quicky fa after a singe t MASTER cyce. If = at the end of the start-up time, the output is hed in reset and remains high. Figures 7 to 1 detai the four possibe start-up sequences. m/ 1/ 1/ 1/ 5μs = 3.3 R = k 1ms/ 6991 F5 =.5 CODE = R = 5k 5μs/ 6991 F6 Figure 5. CODE Change from 1 to Figure 6. Typica Start-Up 1
OPERATION t START t 6991 F7 Figure 7. Start-Up Timing Diagram ( =, POL = ) t START PUT DISABLED FOR INTEGER MULTIPLE OF t 6991 F8 Figure 8. Start-Up Timing Diagram ( = 1, POL = ) 6991 F9 t START t MASTER PUT DISABLED FOR INTEGER MULTIPLE OF t Figure 9. Start-Up Timing Diagram ( =, POL = 1) 6991 F1 t START t t MASTER Figure 1. Start-Up Timing Diagram ( = 1, POL = 1) 13
APPLICATIONS INFORMATION Basic Operation The simpest and most accurate method to program the is to use a singe resistor, R, between the and pins. The design procedure is a 3-step process. First seect the POL bit setting and N vaue, then cacuate the vaue for the R resistor. Aternativey, Linear Technoogy offers the easy to use TimerBox Designer too to quicky design any based circuit. Downoad the free TimerBox Designer software at www.inear.com/timerbox. Step 1: Seect the POL Bit Setting The can operate in norma (active-high) or inverted (active-ow) modes, depending on the setting of the POL bit. The best choice depends on the the appication. Step : Seect the N Frequency Divider aue As expained earier, the votage on the pin sets the CODE which determines both the POL bit and the N vaue. For a given output cock period, N shoud be seected to be within the foowing range. t 16.384ms N t 1.4ms (1) To minimize suppy current, choose the owest N vaue (generay recommended). Aternativey, use Tabe 1 as a guide to seect the best N vaue for the given appication. Exampe: Design a 1Hz osciator with minimum power consumption and active-high reset input. Step 1: Seect the POL Bit Setting For noninverted (active-high) functionaity, choose POL =. Step : Seect the N Frequency Divider aue Choose an N vaue that meets the requirements of Equation (1), using t = 1ms: 61.4 N 976.6 Potentia settings for N incude 64 and 51. N = 64 is the best choice, as it minimizes suppy current by using a arge R resistor. POL = and N = 64 requires CODE =. Using Tabe 1, choose = 976k and = 18k vaues to program CODE =. Step 3: Seect R Cacuate the correct vaue for R using Equation (). R = 5k 1.4ms 1ms = 763k 64 Since 763k is not avaiabe as a standard 1% resistor, substitute 768k if a.7% frequency shift is acceptabe. Otherwise, seect a parae or series pair of resistors such as 576k + 187k to attain a more precise resistance. The competed design is shown in Figure 11. With POL aready chosen, this competes the seection of CODE. Use Tabe 1 to seect the proper resistor divider or / ratio to appy to the pin..5 TO 5.5 Step 3: Cacuate and Seect R The fina step is to cacuate the correct vaue for R using the foowing equation. R 763k 976k CODE = 18k R = 5k 1.4ms t N () 6991 F11 Figure 11. 1Hz Osciator Seect the standard resistor vaue cosest to the cacuated vaue. 14
APPLICATIONS INFORMATION as Wake-Up Timer The output atch reset function provided by the pin aows the to enabe a arger system at reguar intervas. The on-time can be controed by the system. This aows the system to shut itsef down immediatey after performing its tasks, reducing power consumption. Figure 1 shows an exampe using back boxes for a switching reguator and the system being duty-cyced. In some cases, an RC fiter may be necessary at the input to fiter start-up gitches from the system as it is powered on. If the is enabing a switching reguator that can operate on suppies greater than 5.5, it wi be necessary to imit the suppy votage provided to the. If the output is not heaviy oaded, and if a arge R resistor is used, the suppy current wi not be much arger than 1μA, so a simpe reguator circuit can be constructed using a Zener diode. 3 TO R SUPPLY 4.99k 1N4733A 5.1 1M R 681k 665k IN t REG 357 SECONDS SWITCHING REGULATOR SHDN.1μF C FILT.1μF R FILT 1k DONE SYSTEM 6991 F1 THE SYSTEM CAN EXTEND t ON AS LONG AS NEEDED (UP TO 5% OF t ) t ON t ON t ON REG DONE/ t t t Figure 1. Powering Up a System Once an Hour 15
APPLICATIONS INFORMATION Sef-Resetting Circuits The pin has hysteresis to accommodate sow-changing input votages. Furthermore, the trip points are proportiona to the suppy votage (see Note 6 and the Threshod otage vs Suppy otage curve in Typica Performance Characteristics). This aows an RC time constant at the input to generate a deay that is neary independent of the suppy votage. A simpe appication of this technique aows the output to reset itsef, producing a we-controed puse once each cyce. Figures 13a and 13b show circuits that produce approximatey 1μs puses once a minute. The ony difference is in the POL bit setting, which contros whether the puse is positive or negative. otage Controed Frequency With one additiona resistor, the output frequency can be manipuated by an externa votage. As shown in Figure 14, votage CTRL sources/sinks a current through R CO to vary the I current, which in turn moduates the output frequency as described in Equation (3). f 16 1MHz 5kΩ R = 1+ 14 N R R CO CO CTRL (3) Digita Frequency Contro The contro votage can be generated by a DAC (digitato-anaog converter), resuting in a digitay-controed frequency. Many DACs aow for the use of an externa reference. If such a DAC is used to provide the CTRL votage, the dependency can be eiminated by buffering and using it as the DAC s reference votage, as shown in Figure 15. The DAC s output votage now tracks any variation and eiminates it as an error source. The pin cannot be tied directy to the reference input of the DAC because the current drawn by the DAC s REF input woud affect the frequency. I Extremes (Master Osciator Frequency Extremes) When operating with I outside of the recommended 1.5μA to μa range, the master osciator operates outside of the 6.5kHz to 1MHz range in which it is most accurate. R PW.6k C PW 47pF R 715k 1μs PULSE WIDTH 6 SECONDS.5 TO 5.5 1M 39k (RISING) t PULSE = R PW C PW In 1 t PULSE.6kΩ 47pF In(1.61) t PULSE 1μs 6991 F13a.1μF Figure 13a. Sef-Resetting Circuit (CODE = 4) R PW.6k C PW 47pF R 715k.9μs PULSE WIDTH 6 SECONDS.5 TO 5.5 39k 1M (FALLING) t PULSE = R PW C PW In t PULSE.6kΩ 47pF In(.43) t PULSE.9μs 6991 F13b.1μF Figure 13b. Sef-Resetting Circuit (CODE = 11) CTRL R CO R C1.1μF Figure 14. otage-controed Osciator 6991 F14
APPLICATIONS INFORMATION μp.1μf D IN CLK CS/LD CC LTC1659 REF.1μF 1/ LTC678 R CO + R C1.1μF 6991 F15 f 1MHz 5kΩ = R 1 + CO D IN 14 N R CO R 496 D IN = TO 495 Figure 15. Digitay-Controed Osciator The osciator can sti function with reduced accuracy for I < 1.5μA. At approximatey 5nA, the osciator output wi be frozen in its current state. The output coud hat in a high or ow state. This avoids introducing short puses when frequency moduating a very ow frequency output. At the other extreme, it is not recommended to operate the master osciator beyond MHz because the accuracy of the pin ADC wi suffer. Frequency Moduation and Setting Time The wi respond to changes in I up to a 3dB bandwidth of.4 f. Foowing a or.5 step change in I, the output frequency takes ess than one cyce to sette to within 1% of the fina vaue. Power Suppy Current The power suppy current varies with frequency, suppy votage and output oading. It can be estimated under any condition using the foowing equation. This equation ignores C LOAD (vaid for C LOAD < 1nF) and assumes the output has 5% duty cyce. I S(TYP) f MASTER 7.8pF + + 4kΩ + R LOAD + 1.8 I + 5μA Suppy Bypassing and PCB Layout Guideines The is a.% accurate siicon osciator when used in the appropriate manner. The part is simpe to use and by foowing a few rues, the expected performance is easiy achieved. Adequate suppy bypassing and proper PCB ayout are important to ensure this. Figure 18 shows exampe PCB ayouts for both the TSOT-3 and DFN packages using 63 sized passive components. The ayouts assume a two ayer board with a ground pane ayer beneath and around the. These ayouts are a guide and need not be foowed exacty. 17
APPLICATIONS INFORMATION C1.1μF R C1 C1 R R 6991 F18 DFN PACKAGE Figure 18. Suppy Bypassing and PCB Layout TSOT-3 PACKAGE 1. Connect the bypass capacitor, C1, directy to the and pins using a ow inductance path. The connection from C1 to the pin is easiy done directy on the top ayer. For the DFN package, C1 s connection to is aso simpy done on the top ayer. For the TSOT-3, can be routed through the C1 pads to aow a good C1 connection. If the PCB design rues do not aow that, C1 s connection can be accompished through mutipe vias to the ground pane. Mutipe vias for both the pin connection to the ground pane and the C1 connection to the ground pane are recommended to minimize the inductance. Capacitor C1 shoud be a.1μf ceramic capacitor.. Pace a passive components on the top side of the board. This minimizes trace inductance. 3. Pace R as cose as possibe to the pin and make a direct, short connection. The pin is a current summing node and currents injected into this pin directy moduate the operating frequency. Having a short connection minimizes the exposure to signa pickup. 4. Connect R directy to the pin. Using a ong path or vias to the ground pane wi not have a significant affect on accuracy, but a direct, short connection is recommended and easy to appy. 5. Use a ground trace to shied the pin. This provides another ayer of protection from radiated signas. 6. Pace and cose to the pin. A direct, short connection to the pin minimizes the externa signa couping. 18
TYPICAL APPLICATIONS 5 Second On/Off Timed Reay Driver 1.1μF RUN RELAY ENABLE RE R3 118k D1 1N4148 R4 15k 5 1M 39k 6991 TA L NO Q1 N19A C.1μF C 1 COTO 1 RELAY 91-1-1 1.5ms Radio Contro Servo Reference Puse Generator 5 R7 1k ms FRAME RATE GENERATOR ms PERIOD 1.5ms REFERENCE PULSE RE = OPEN RUN = R6 11k 5 R4 976k R5 1k C1.1μF R3 146k TRIG LTC6993-1 5 1.5ms PULSE 1M 8k C.1μF 6991 TA3 Cycing (1 Seconds On/Off) Symmetrica Power Suppies 15 IN R6 k M Si4435DY 15 1 5k 1k M3 Si941 37k R8 1M R9 39k 5 C1.1μF R3 5k M4 Si4435DY 1k 15 IN 15 M1 Si941 F6991 TA4 19
TYPICAL APPLICATIONS Isoated AC Load Fasher 5.1μF OPEN = OFF = ON R3 5 R4 1k U 1 6 15Ω 1 MOC341M 6 3 R 37k 4 1 SECONDS ON/OFF 1M 39k 5 ZERO CROSSING 4 R5 5.94k R6 1k U3 NTE564 4W LAMP R7 1Ω C.μF 6991 TA5 HOT 117 AC NEUTRAL AC ISOLATION BARRIER = 75 Interva (Wiper) Timer 5 5s 15s 3s 1m m 4m s + OFF 66.5k TRIG LTC6993-1 PUT s 8k 18k 18.k 5s 15s 3s 1m m 4m s OFF.1μF 1M 383k s.1μf 1M 681k t INTERAL SECONDS TO 4 MINUTES 6991 TA6 18k 8k 113k 133k 5s 15s 3s 1m m 4m s OFF
PACKAGE DESCRIPTION Pease refer to http://www.inear.com/designtoos/packaging/ for the most recent package drawings. DCB Package 6-Lead Pastic DFN (mm 3mm) (Reference LTC DWG # 5-8-1715 Rev A).7.5 1.65.5 3.55.5 ( SIDES).15.5 PACKAGE LINE.5.5.5 BSC 1.35.5 ( SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS..1 ( SIDES) R =.115 TYP R =.5 TYP 4 6.4.1 3..1 ( SIDES) 1.65.1 ( SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6). REF.75.5..5 PIN 1 NOTCH R. OR.5 45 CHAMFER (DCB6) DFN 45 3 1.5.5.5 BSC 1.35.1 ( SIDES) BOTTOM IEW EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE LINE M-9 ARIATION OF (TBD). DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 1
PACKAGE DESCRIPTION Pease refer to http://www.inear.com/designtoos/packaging/ for the most recent package drawings. S6 Package 6-Lead Pastic TSOT-3 (Reference LTC DWG # 5-8-1636).6 MAX.95 REF.9 BSC (NOTE 4) 1. REF 3.85 MAX.6 REF 1.4 MIN.8 BSC 1.5 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAY PER IPC CALCULATOR.95 BSC.3.45 6 PLCS (NOTE 3).8.9. BSC DATUM A 1. MAX.1.1.3.5 REF.9. (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIE OF PLATING 4. DIMENSIONS ARE EXCLUSIE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED.54mm 6. JEDEC PACKAGE REFERENCE IS MO-193 1.9 BSC S6 TSOT-3 3 RE B
REISION HISTORY RE DATE DESCRIPTION PAGE NUMBER A 7/11 Updated Description, Typica Appication, and Order Information sections Added additiona information to Δf /Δ and incuded Note 11 in Eectrica Characteristics section Added Typica Frequency Error vs Time curve to Typica Performance Characteristics section Added text to Basic Operation paragraph in Appications Information section 1, 3, 4 6 14 B 1/1 Added MP grade 1,, 4 Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 3
TYPICAL APPLICATION Intervaometer for Time-Lapse Photography 8SEC TO 64SEC R S1 1M R PW 1k C PW 33μF R S3 95.3k R S M ACTIATES SHUTTER AT 8SEC TO 8.5MIN INTERALS A 33k SHUTTER B 1M 1μF SLOW RANGE 1.1MIN TO 8.5 MIN 13k 6991 TA7 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1799 1MHz to 33MHz ThinSOT Siicon Osciator Wide Frequency Range LTC69 1MHz to MHz ThinSOT Siicon Osciator Low Power, Wide Frequency Range LTC696/LTC697 1kHz to 1MHz or 4kHz ThinSOT Siicon Osciators Micropower, I SUPPLY = 35μA at 4kHz LTC693 Fixed Frequency Osciator, 3.768kHz to 8.19MHz.9% Accuracy, 11μs Start-Up Time, 15μA at 3kHz LTC699 TimerBox: otage-controed Siicon Osciator Fixed-Frequency or otage-controed Operation LTC699 TimerBox: otage-controed Puse Width Moduator (PWM) Simpe PWM with Wide Frequency Range LTC6993 TimerBox: Monostabe Puse Generator (One Shot) Resistor Programmabe Puse Width of 1μs to 34sec LTC6994 TimerBox: Deay Bock/Debouncer Deays Rising, Faing or Both Edges 1μs to 34sec 4 LT 11 RE B PRINTED IN USA Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA 9535-7417 (48) 43-19 FAX: (48) 434-57 www.inear.com LINEAR TECHNOLOGY CORPORATION 1