Simulator for Intel x86/x64

Simulator for Intel x86/x64 TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents... TRACE32 Instruction Set Simulators... Simulator for Intel x86/x64... 1 TRACE32 Simulator License... 3 Quick Start of the Simulator... 4 Peripheral Simulation... 6 Troubleshooting... 6 FAQ 6 Emulation Modes... 7 SYStem.CONFIG Configure debugger according to target topology 7 SYStem.CPU CPU type 7 SYStem.CpuAccess Run-time memory access (intrusive) 7 SYStem.LOCK Lock and tristate the debug port 8 SYStem.MemAccess Real-time memory access (non-intrusive) 8 SYStem.Mode Establish the communication with the simulator 9 General SYStem Settings and Restrictions... 10 SYStem.Option REL Relocation register 10 SYStem.Option MEMoryMODEL Define memory model 10 Memory Classes... 13 Support... 14 Available Tools 14 Compilers 17 Realtime Operation System 17 3rd Party Tool Integrations 18 Products... 19 Product Information 19 Order Information 19 Simulator for Intel x86/x64 1

Simulator for Intel x86/x64 Version 24-May-2016 All general commands are described in the IDE Reference Guide (ide_ref.pdf) and General Commands Reference. Simulator for Intel x86/x64 2

TRACE32 Simulator License [build 68859 - DVD 02/2016] The extensive use of the TRACE32 Instruction Set Simulator requires a TRACE32 Simulator License. For more information, see www.lauterbach.com/sim_license.html. Simulator for Intel x86/x64 3 TRACE32 Simulator License

Quick Start of the Simulator To start the simulator, proceed as follows: 1. Select the device prompt for the ICD Debugger and reset the system. B:: RESet The device prompt B:: is normally already selected in the command line. If this is not the case, enter B:: to set the correct device prompt. The RESet command is only necessary if you do not start directly after booting the TRACE32 development tool. 2. Specify the CPU specific settings. SYStem.CPU <cpu_name> The default values of all other option are set in such a way that it should be possible to work without modification. Please consider that this is probably not the best configuration for your target. Simulator for Intel x86/x64 4 Quick Start of the Simulator

3. Enter debug mode. SYStem.Up This command resets the CPU and enters debug mode. After this command is executed it is possible to access memory and registers. 4. Load the program. Data.LOAD.format <filename> ; load program and symbols The format of the Data.LOAD command depends on the file format generated by the compiler. Refer to Supported Compilers to find the command that is necessary for your compiler. A detailed description of the Data.LOAD command and all available options is given in the reference guide. 5. Start-up Example A typical start sequence is shown below. This sequence can be written to a PRACTICE script file (*.cmm) and executed with the command DO <filename>. B:: WinCLEAR SYStem.CPU <cpu_name> SYStem.Up Data.LOAD.format <filename> Register.Set pc main PER.view ; Select the ICD device prompt ; Clear all windows ; Select CPU type ; Reset the target and enter ; debug mode ; Load the application ; Set the PC to function main ; Show clearly arranged peripherals ; in window *) Data.List ; Open source code window *) Register /SpotLight ; Open register window *) Frame.view /Locals /Caller Var.Watch %Spotlight flags ast ; Open the stack frame with ; local variables *) ; Open watch window for ; variables *) *) These commands open windows on the screen. The window position can be specified with the WinPOS command. Simulator for Intel x86/x64 5 Quick Start of the Simulator

Peripheral Simulation For more information, see API for TRACE32 Instruction Set Simulator (simulator_api.pdf). Troubleshooting FAQ No information available Simulator for Intel x86/x64 6 Peripheral Simulation

Emulation Modes SYStem.CONFIG Configure debugger according to target topology The SYStem.CONFIG commands have no effect on the simulator. They are only provided to allow the user to run PRACTICE scripts written for the debugger within the simulator without modifications. SYStem.CPU CPU type Format: SYStem.CPU <mode> <mode>: I8086 I80186 I80186EA I80186EB I80186EC AM186EM AM186ES AM186ER AM186ED AM186CC Selects the processor type. SYStem.CpuAccess Run-time memory access (intrusive) Format: SYStem.CpuAccess Enable Denied Nonstop Default: Denied. Enable Allow intrusive run-time memory access. Since a non-intrusive run-time memory access (SYStem.MemoryAccess CPU) is available for all TRACE32 instruction set simulators, there is no need for an intrusive run-time memory access. Simulator for Intel x86/x64 7 Emulation Modes

Denied Nonstop Lock intrusive run-time memory access. Lock all features of the debugger, that affect the run-time behavior. Nonstop reduces the functionality of the debugger to: run-time access to memory and variables trace display The debugger inhibits the following: to stop the program execution all features of the debugger that are intrusive (e.g. action Spot for breakpoints, performance analysis via StopAndGo mode, conditional breakpoints etc.) SYStem.LOCK Lock and tristate the debug port Format: SYStem.LOCK [ON OFF] Default: OFF. If the system is locked, no access to the debug port will be performed by the debugger. While locked, the debug connector of the debugger is tristated. The main intention of the lock command is to give debug access to another tool. The command has no effect for the simulator. SYStem.MemAccess Real-time memory access (non-intrusive). Format: SYStem.MemAccess CPU Denied<cpu_specific> SYStem.ACCESS (deprecated) CPU Denied Real-time memory access during program execution to target is enabled. Real-time memory access during program execution to target is disabled. Default: Denied. Simulator for Intel x86/x64 8 Emulation Modes

SYStem.Mode Establish the communication with the simulator Format: SYStem.Mode <mode> <mode>: Down NoDebug Go Up Default: Down. Selects the target operating mode. Down NoDebug Go Up The CPU is in reset. Debug mode is not active. Default state and state after fatal errors. The CPU is running. Debug mode is not active. Debug port is tristate. In this mode the target should behave as if the debugger is not connected. The CPU is running. Debug mode is active. After this command the CPU can be stopped with the break command or if any break condition occurs. The CPU is not in reset but halted. Debug mode is active. In this mode the CPU can be started and stopped. This is the most typical way to activate debugging. If the mode Go is selected, this mode will be entered, but the control button in the SYStem window jumps to the mode Up. Simulator for Intel x86/x64 9 Emulation Modes

General SYStem Settings and Restrictions SYStem.Option REL Relocation register Format: SYStem.Option REL <value> IREL option must be set to the same value the user program write to the REL register. The adjusted I/O base address can be read back with the functions IOBASE() and IOBASE.ADDRESS(). They return the offset or the complete address (offset and access mode) for the I/O area. SYStem.Option MEMoryMODEL Define memory model Format: SYStem.OptionMEMoryMODEL <model> <model>: LARGE FLAT LDT SingleLDT ProtectedFLAT Default: LARGE (Multi-Segment Model). Selects the memory model TRACE32 uses for code and data accesses. The memory model describes how the CS (code segment), DS (data segment), SS (stack segment), ES, FS and GS segment registers are currently used by the processor. The command SYStem.Option.MMUSPACES ON will override the setting of SYStem.Option.MEMoryMODEL with the memory model MMUSPACES. Simulator for Intel x86/x64 10 General SYStem Settings and Restrictions

The selection of the memory model affects the following areas: The way TRACE32 augments program or data addresses with information from the segment descriptors. Information augmented is the segment selector, offset, limit and access width. The TRACE32 address format The way TRACE32 handles segments when the debugger address translation is enabled (TRANSlation.ON). LARGE This is the default memory model. It is enabled after reset. This memory model is used if the application makes use of the six segment registers (CS, DS, ES, FS, GS, SS) and the global descriptor table (GDT) and/or the local descriptor table (LDT). TRACE32 supports GDT and LDT descriptor table walks in this memory model. if a TRACE32 address contains a segment descriptor and the specified segment descriptor is not present in any of the six segments CS, DS, ES, FS, GS or SS, TRACE32 will perform a descriptor table walk through the GDT or the LDT to extract the descriptor information and apply it to the address. Access classes of program and data addresses will be augmented with information from the CS and DS segments. Segment translation is used in TRACE32 address translation. TRACE32 addresses display the segment selector to the left of the address offset. The segment selector indicates the GDT or LDT segment descriptor which is used for the address. Example address: NP:0x0018:0x0003F000 LDT This memory model should be selected if a LDT is present and the debugger uses multiple entries from it. TRACE32 addresses contain a LDTR segment selector specifying the LDT entry which applies to an address. Access classes of program and data addresses will be augmented with the information specified by the LDTR segment selector. Segment translation is used in TRACE32 address translation. TRACE32 addresses display three numeric elements: The 16-bit LDTR segment selector used pointing to the LDT for the address The 16-bit CS (for program addresses) or DS (for data addresses) segment selector, extracted from the LDT The 16-bit address offset Example address: NP:0x0004:0x0018:0x8000 Simulator for Intel x86/x64 11 General SYStem Settings and Restrictions

SingleLDT This memory model should be selected if a LDT is present but the debugger works with only one single LDT entry. The LDT is not used to differentiate addresses. Access classes of program and data addresses will be augmented with information from the CS (for program addresses) or DS (for data addresses) segment. Segment translation is used in TRACE32 address translation. TRACE32 addresses display the segment selector to the left of the address offset. Example address: NP:0x001C:0x0003F000 ProtectedFLAT This memory model is used if the segment translation and limit checks of the CS and the DS registers are required, but the segment register contents are kept constant. Consequently, TRACE32 addresses contain no segment descriptor because no descriptor table walk is used to reload the segment registers. Access classes of addresses are not augmented with segment information. TRACE32 addresses display only the access class and the address offset. Example address: NP:0xC0003F000 Segment translation is used in TRACE32 address translation for limit checking. Accesses to program addresses use the CS segment, accesses to data addresses use the DS segment. FLAT This memory model is used if segmentation plays no role for an application and memory management makes use of paging only. Segments are ignored, no segment translation is performed. Accesses to program and data addresses are treated the same. Example address: NP:0xC0003F000 (MMUSPACES) This memory model can only be enabled with the command SYStem.Option.MMUSPACES ON. Memory model MMUSPACES is used if TRACE32 works with a kernel awareness and memory space identifiers (spaceids) are used in addresses to identify process specific address spaces. Segments are ignored, no segment translation is performed. TRACE32 addresses display a 16-bit memory space identifier to the left of the address offset. Example address: NP:0x29A:0xC0003F000 Simulator for Intel x86/x64 12 General SYStem Settings and Restrictions

Memory Classes Memory Class D P IO Description Data Program I/O C E A Memory access by CPU Emulation memory access Absolute (physical) memory access Simulator for Intel x86/x64 13 Memory Classes

Support Available Tools CPU ICE FIRE ICD DEBUG ICD MONITOR ICD TRACE POWER INTEGRATOR INSTRUCTION SIMULATOR 230 YES YES 330 YES YES 8086 YES YES YES 8088 YES YES YES 80C186EA YES YES YES 80C186EB YES YES YES 80C186EC YES YES YES 80C186XL YES YES YES 80C188EA YES YES YES 80C188EB YES YES YES 80C188EC YES YES YES 80C188XL YES YES YES AM186CC YES YES YES AM186CH YES YES YES AM186CU YES YES YES AM186ED YES YES YES AM186EM YES YES YES AM186EMLV YES YES YES AM186ER YES YES YES AM186ES YES YES YES AM186ESLV YES YES YES AM188EM YES YES YES AM188EMLV YES YES YES AM188ER YES YES YES AM188ES YES YES YES AM188ESLV YES YES YES C27XX YES YES CE2600 YES YES CE4200 YES YES CE5300 YES YES COREI3 YES YES COREI3-2NDGEN YES YES COREI3-3RDGEN YES YES COREI3-4THGEN YES YES Simulator for Intel x86/x64 14 Support

CPU COREI5 YES YES COREI5-2NDGEN YES YES COREI5-3RDGEN YES YES COREI5-4THGEN YES YES COREI7 YES YES COREI7-2NDGEN YES YES COREI7-3RDGEN YES YES COREI7-4THGEN YES YES D2500 YES YES D2550 YES YES D2700 YES YES D410 YES YES D425 YES YES D510 YES YES D525 YES YES E382X YES YES E620 YES YES E620T YES YES E640 YES YES E640T YES YES E645C YES YES E645CT YES YES E660 YES YES E660T YES YES E665C YES YES E665CT YES YES E680 YES YES E680T YES YES N2600 YES YES N270 YES YES N280 YES YES N2800 YES YES N450 YES YES N455 YES YES N470 YES YES N475 YES YES N550 YES YES N570 YES YES QUARKX1000 YES YES V20 YES YES YES V30 YES YES YES Simulator for Intel x86/x64 15 Support ICE FIRE ICD DEBUG ICD MONITOR ICD TRACE POWER INTEGRATOR INSTRUCTION SIMULATOR

CPU V40 YES YES YES V50 YES YES YES Z2420 YES YES Z2460 YES YES Z2480 YES YES Z2520 YES YES Z2560 YES YES Z2580 YES YES Z2720 YES YES Z2760 YES YES Z2780 YES YES Z37XX YES YES Z500 YES YES Z510 YES YES Z510P YES YES Z510PT YES YES Z515 YES YES Z520 YES YES Z520PT YES YES Z530 YES YES Z530P YES YES Z540 YES YES Z550 YES YES Z560 YES YES Z600 YES YES Z615 YES YES Z625 YES YES Z650 YES YES Z670 YES YES ICE FIRE ICD DEBUG ICD MONITOR ICD TRACE POWER INTEGRATOR INSTRUCTION SIMULATOR Simulator for Intel x86/x64 16 Support

Compilers Language Compiler Company Option Comment ASM AXLS HP HP Source level debugging C BORLANDC Borland Software Corporation EOMF-86 with Paradigm LOCATE C ORGANON CAD-UL EOMF-86 Banking support ElectronicServices GmbH C IC86 Intel Corporation OMF-86 C MCC86 Mentor Graphics EOMF-86 incl. Microtec ext. Corporation C MSC/MSVC-16BIT Microsoft Corporation EOMF-86 with Paradigm LOCATE C MSC/MSVC Microsoft Corporation EXE/TD with Paradigm LOCATE C ICC86 TASKING OMF-86 C ICC86 TASKING IEEE C++ BORLANDC Borland Software EXE/TD Corporation C++ MSVC-16BIT Microsoft Corporation EXE/CV MODULA LOGITECH-M2 Terra Datentechnik MAP/REF PASCAL TEK-PASCAL Tektronix TEK PLM PL/M86 Intel Corporation OMF-86 reads src or list file Realtime Operation System Name Company Comment ChorusOS Oracle Corporation Nucleus PLUS Mentor Graphics Corporation psos+ Wind River Systems 2.1 to 2.5, 3.0 RTXC 3.2 Quadros Systems Inc. VxWorks Wind River Systems 5.x and 6.x Simulator for Intel x86/x64 17 Support

3rd Party Tool Integrations CPU Tool Company Host ALL ADENEO Adeneo Embedded ALL X-TOOLS / X32 blue river software GmbH Windows ALL CODEWRIGHT Borland Software Windows Corporation ALL CODE CONFIDENCE Code Confidence Ltd Windows TOOLS ALL CODE CONFIDENCE Code Confidence Ltd Linux TOOLS ALL EASYCODE EASYCODE GmbH Windows ALL ECLIPSE Eclipse Foundation, Inc Windows ALL RHAPSODY IN MICROC IBM Corp. Windows ALL RHAPSODY IN C++ IBM Corp. Windows ALL CHRONVIEW Inchron GmbH Windows ALL LDRA TOOL SUITE LDRA Technology, Inc. Windows ALL UML DEBUGGER LieberLieber Software Windows GmbH ALL ATTOL TOOLS MicroMax Inc. Windows ALL VISUAL BASIC Microsoft Corporation Windows INTERFACE ALL LABVIEW NATIONAL Windows INSTRUMENTS Corporation ALL CODE::BLOCKS Open Source - ALL C++TEST Parasoft Windows ALL RAPITIME Rapita Systems Ltd. Windows ALL DA-C RistanCASE Windows ALL TRACEANALYZER Symtavision GmbH Windows ALL SIMULINK The MathWorks Inc. Windows ALL TA INSPECTOR Timing Architects GmbH Windows ALL UNDODB Undo Software Linux ALL VECTORCAST UNIT Vector Software Windows TESTING ALL VECTORCAST CODE Vector Software Windows COVERAGE ALL WINDOWS CE PLATF. BUILDER Windows Windows Simulator for Intel x86/x64 18 Support

Products Product Information OrderNo Code LA-8813 SIM-86 Text TRACE32 Instruction Set Simulator for 0x86 TRACE32 Instruction Set Simulator for 0x86 family Order Information Order No. Code Text LA-8813 SIM-86 TRACE32 Instruction Set Simulator for 0x86 Simulator for Intel x86/x64 19 Products