19-1811; Rev 2; 4/9 EVALUATION KIT AVAILABLE Dual-Output Step-Down General Description The dual, step-down DC-DC converter generates both the main (+3.3V at over 2A) and core (+1.8V at up to 1.5A) supplies for a complete power solution for PDAs, subnotebooks, and other hand-held devices. The main output is adjustable from +1.25V to +5.5V. The core output is adjustable from 1V to 5V. Both switching converters operate at up to 1.25MHz for small external components and use synchronous rectifiers to achieve efficiencies up to 95%. Operation with up to 1% duty cycle provides the lowest possible dropout voltage to extend useful battery life. The accepts inputs from +2.7V up to +28V, allowing use with many popular battery configurations as well as AC-DC wall adapters. Digital soft-start reduces battery current surges at power-up. Both the main and core converters have separate shutdown inputs. The comes in a small 16-pin QSOP package. The evaluation kit is available to help reduce design time. Applications Hand-Held Computers PDAs Internet Access Tablets POS Terminals Subnotebooks Features Dual, High-Efficiency, Synchronous Rectified Step-Down Converter Main Power Adjustable from +1.25V to +5.5V Over 2A Load Current Up to 95% Efficiency Core Power Adjustable from 1V to 5V Internal Switches Up to 1.5A Load Current Up to 92% Efficiency 1% (max) Duty Cycle Up to 1.25MHz Switching Frequency Input Voltage Range from +2.7V to +28V 17μA Quiescent Current 5μA Shutdown Current Digital Soft-Start Independent Shutdown Inputs Ordering Information PART TEMP RANGE PIN-PACKAGE EEE -4 C to +85 C 16 QSOP Typical Operating Circuit IN 2.7V TO 5.5V (28V IN CASCADE) TOP VIEW SHDNM SHDNC PGND NDRV CVL IN 1 2 3 4 5 6 Pin Configuration ON ON OFF OFF SHDNM SHDNC CVL REF PGND GND IN CVH INC PDRV NDRV CS+ 16 15 14 13 12 11 LXC INC GND FBC CS- CS+ CS- FBM LXC CORE 1.8V 1.5A MAIN 3.3V OVER 2A PDRV CVH 7 8 1 9 FBM REF FBC 16 QSOP Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
ABSOLUTE MAXIMUM RATINGS IN, SHDNM, CVH to GND...-.3V to +3V IN to CVH, PDRV...-.3V to +6V PDRV to GND...(V CVH -.3V) to (V IN +.3V) PGND to GND...-.3V to +.3V All Other Pins to GND...-.3V to +6V Core Output Short Circuit...Continuous Continuous Power Dissipation 16-Pin QSOP (derate 7.1mW/ C above +7 C)...571mW Operating Temperature...-4 C to +85 C Storage Temperature...-65 C to +15 C Lead Temperature (soldering, 1s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V IN = +12V, V MAIN = V INC = V CS- = V CS+ = +3.3V, V CORE = +1.8V, Circuit of Figure 4, T A = C to +85 C, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Voltage V IN 2.7 28 V Input Quiescent Supply Current I IN V FBM = +1.5V, V FBC = +1.5V, V SHDNM = V SHDNC = +3.3V 15 3 µa CS- Quiescent Supply Current I CS - V FBM = +1.5V, V FBC = +1.5V, V SHDNM = V SHDNC = +3.3V 11 22 µa Core Regulator Quiescent Supply Current I INC V FBM = +1.5V, V FBC = +1.5V, V SHDNM = V SHDNC = +3.3V 6 12 µa IN Shutdown Supply Current SHDNM = SHDNC = GND 5 3 µa MAIN REGULATOR Main Output Voltage Adjust Range 1.25 5.5 V FBM Regulation Threshold V FBM V ( C S + - C S - ) = to + 6m V, V IN = + 2.7V to + 28V 1.21 1.25 1.29 V FBM Input Current I FBM V FBM = +1.3V -.1.1 µa Current-Limit Threshold V CLM V CS+ - V CS- 6 8 1 mv Minimum Current-Limit Threshold V MIN V CS+ - V CS- 6 15 24 mv Valley Current Threshold V VALLEY V CS+ - V CS- 4 5 6 mv Zero Current Threshold V ZERO V CS+ - V CS- 15 mv PDRV, NDRV Gate Drive Resistance V CS- = +3.3V, I LOAD = 5mA 2 4.4 Ω CS- to CVL Switch Resistance I CVL = 5mA 4.5 8 Ω PDRV, NDRV Dead Time 5 ns Maximum Duty Cycle 1 % Minimum On-Time 2 4 65 ns Minimum Off-Time 2 4 65 ns 2
ELECTRICAL CHARACTERISTICS (continued) (V IN = +12V, V MAIN = V INC = V CS- = V CS+ = +3.3V, V CORE = +1.8V, Circuit of Figure 4, T A = C to +85 C, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Maximum Duty Cycle 1 % Minimum On-Time 2 65 ns Minimum Off-Time 2 65 ns CORE REGULATOR Input Voltage Range V INC 2.6 5.5 V INC Undervoltage Lockout Core Output Voltage Adjust Range V INC rising 2.39 2.55 V INC falling 2.29 2.45 1. 5. V Maximum Core Load Current (Note 1) 1 A FBC Regulation Threshold V FBC V INC = +2.5V to +5.5V, I OUTC = to 2mA.97 1.3 V FBC Input Current I FBC V FBC = +1.3V -.1.1 µa Dropout Voltage (INC to LXC) I OUTC = 4mA.2 V LXC Leakage Current I LXC V INC = +5.5V, V LXC = to +5.5V -1 1 µa LXC P-Channel, N-Channel On-Resistance V.5 Ω LXC P-Channel Current Limit 12 35 ma LXC P-Channel Minimum Current 1 4 ma LXC N-Channel Valley Current 88 245 ma LXC N-Channel Zero-Crossing Current 35 175 ma Maximum Duty Cycle 1 % Minimum On-Time 15 67 ns Minimum Off-Time 15 67 ns REFERENCE Reference Voltage V REF 1.22 1.27 V Reference Load Regulation I REF = to 5µA 1 mv Reference Line Regulation V CS- = +2.5V to +5.5V, I REF = 5µA 5 mv Reference Sink Current I REF 1 µa CVL, CVH REGULATORS CVL Output Voltage V CVL I CVL = 5mA, V IN = +2.7V, V CS- = V 2.6 3.1 V V IN = +4V, I CVH = 25mA V IN - 2.8 CVH Output Voltage V CVH V IN = +12V, I CVH = 5mA V IN - 3.7 V CVL Undervoltage Lockout V CVL rising 2.4 2.55 V CVL falling 2.3 2.45 V 3
ELECTRICAL CHARACTERISTICS (continued) (V IN = +12V, V MAIN = V INC = V CS- = V CS+ = +3.3V, V CORE = +1.8V, Circuit of Figure 4, T A = C to +85 C, unless otherwise noted. Typical values are at T A = +25 C.) LOGIC INPUTS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SHDNM, SHDNC Input Low Voltage SHDNM, SHDNC Input High Voltage SHDNM, SHDNC Input Low Current.4 V 2. V SHDNM = SHDNC = GND -1 1 µa SHDNC Input High Current V SHDNC = +5.5V 5 µa SHDNM Input High Current V SHDNM = +5V 2 V SHDNM = +28V 15 3 µa ELECTRICAL CHARACTERISTICS (V IN = +12V, V MAIN = V INC = V CS- = V CS+ = +3.3V, V CORE = +1.8V, Circuit of Figure 4, T A -4 C to +85 C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Input Voltage V IN 2.7 28 V Input Quiescent Supply Current I IN V FBM = +1.5V, V FBC = +1.5V, V SHDNM = V SHDNC = +3.3V CS- Quiescent Supply Current I CS- V FBM = +1.5V, V FBC = +1.5V, V SHDNM = V SHDNC = +3.3V Core Regulator Quiescent Supply Current I INC V FBM = +1.5V, V FBC = +1.5V, V SHDNM = V SHDNC = +3.3V 3 µa 22 µa 12 µa IN Shutdown Supply Current SHDNM = SHDNC = GND 3 µa MAIN REGULATOR Main Output Voltage Adjust Range 1.25 5.5 V FBM Regulation Threshold V FBM V ( C S + - C S - ) = to + 6m V, V I N = + 2.7V to + 28V 1.21 1.29 V FBM Input Current I FBM V FBM = +1.3V -.1.1 µa Current-Limit Threshold V CL V CS+ - V CS- 6 1 mv M i ni m um C ur r ent- Li m i t Thr eshol d V CS+ - V CS- 6 24 mv Valley Current Threshold V CS+ - V CS- 4 6 mv Zero Current Threshold V CS+ - V CS- 15 mv PDRV, NDRV Gate Drive Resistance V CS- = +3.3V 4.4 Ω CS- to CVL Switch Resistance I CVL = 5mA 8 Ω 4
ELECTRICAL CHARACTERISTICS (continued) (V IN = +12V, V MAIN = V INC = V CS- = V CS+ = +3.3V, V CORE = +1.8V, Circuit of Figure 4, T A -4 C to +85 C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Maximum Duty Cycle 1 % Minimum On-Time 2 65 ns Minimum Off-Time 2 65 ns CORE REGULATOR Input Voltage Range V INC 2.6 5.5 V INC Undervoltage Lockout Core Output Voltage Adjust Range V INC rising 2.39 2.55 V INC falling 2.29 2.45 1. 5. V Maximum Core Load Current (Note 1) 1 A FBC Regulation Threshold V FBC V INC = +2.5V to +5.5V, I OUTC = to 2mA.97 1.3 V FBC Input Current I FBC V FBC = +1.3V -.1.1 µa Dropout Voltage (INC to LXC) I OUTC = 4mA.2 V LXC Leakage Current I LXC V INC = +5.5V, V LXC = to +5.5V -1 1 µa LXC P-Channel, N-Channel On-Resistance V.5 Ω LXC P-Channel Current Limit 12 35 ma LXC P-Channel Minimum Current 1 4 ma LXC N-Channel Valley Current 88 245 ma LXC N-Channel Zero-Crossing Current 35 175 ma Maximum Duty Cycle 1 % Minimum On-Time 15 67 ns Minimum Off-Time 15 67 ns REFERENCE Reference Voltage V REF 1.22 1.27 V Reference Load Regulation I REF = to 5µA 1 mv Reference Line Regulation V CS- = +2.5V to +5.5V, I REF = 5µA 5 mv Reference Sink Current I REF 1 µa CVL, CVH REGULATORS CVL Output Voltage V CVL I CVL = 5mA, V IN = +2.7V, V CS- = V 2.6 3.1 V V IN = +4V, I CVH = 25mA V IN - 2.8 CVH Output Voltage V CVH V IN = +12V, I CVH = 5mA V IN - 3.7 V CVL Undervoltage Lockout V CVL rising 2.4 2.55 V CVL falling 2.3 2.45 V 5
ELECTRICAL CHARACTERISTICS (continued) (V IN = +12V, V MAIN = V INC = V CS- = V CS+ = +3.3V, V CORE = +1.8V, Circuit of Figure 4, T A -4 C to +85 C, unless otherwise noted.) (Note 2) LOGIC INPUTS PARAMETER SYMBOL CONDITIONS MIN MAX UNITS SHDNM, SHDNC Input Low Voltage SHDNM, SHDNC Input High Voltage.4 V 2. V SHDNM, SHDNC Input Low Current SHDNM = SHDNC = GND -1 1 µa SHDNC Input High Current V SHDNC = +5.5V 5 µa SHDNM Input High Current V SHDNM = +28V 3 µa Note 1: This parameter is guaranteed based on the LXC P-channel current limit and the LXC N-channel valley current. Note 2: Specifications to -4 C are guaranteed by design and not production tested. Typical Operating Characteristics (Circuit of Figure 1, V MAIN = +3.3V, V CORE = +1.8V, T A = +25 C, unless otherwise noted.) EFFICIENCY (%) 1 9 8 7 6 5 4 3 2 1 MAIN OUTPUT EFFICIENCY vs. LOAD V IN = +3.3V V IN = +12V V IN = +15V V IN = +18V V IN = +5V toc1 EFFICIENCY (%) 1 9 8 7 6 5 4 3 2 1 CORE OUTPUT EFFICIENCY vs. LOAD V INC = +2.7V V INC = +3.3V V INC = +5V toc2 VREF ACCURACY (%) 2. 1.5 1..5 -.5-1. -1.5 V REF ACCURACY vs. TEMPERATURE toc3 1 1 1 1 1, LOAD (ma) 1 1 1 1 LOAD (ma) -2. -4-15 1 35 6 85 TEMPERATURE ( C) 6
Typical Operating Characteristics (continued) (Circuit of Figure 1, V MAIN = +3.3V, V CORE = +1.8V, T A = +25 C, unless otherwise noted.) VREF ACCURACY (%) -.2 -.4 -.6 -.8-1. -1.2-1.4-1.6-1.8-2. REFERENCE LOAD REGULATION 1 2 3 4 5 6 7 8 I REF (µa) toc4 MAIN SWITCHING WAVEFORMS, LIGHT LOAD (1mA) 1µs/div toc5 LX 5V/div I LM 5mA/div V MAIN (AC-COUPLED) 2mV/div MAIN SWITCHING WAVEFORMS, HEAVY LOAD (1A) toc6 LX 5V/div CORE SWITCHING WAVEFORMS, LIGHT LOAD (5mA) toc7 LX 5V/div 1mA 5mA I LM 5mA/div 2mA I LC 2mA/div 1µs/div V MAIN (AC-COUPLED) 2mV/div 1µs/div V CORE (AC-COUPLED) 2mV/div CORE SWITCHING WAVEFORMS, HEAVY LOAD (5mA) toc8 4V LXC 2V/div V CORE (AC-COUPLED) 2mV/div MAIN LINE-TRANSIENT RESPONSE (5V TO 12V) toc9 12V 5V V IN 5mA I LC 25mA/div V MAIN 5mV/div 2µs/div 1µs/div 7
Typical Operating Characteristics (continued) (Circuit of Figure 1, V MAIN = +3.3V, V CORE = +1.8V, T A = +25 C, unless otherwise noted.) CORE LINE-TRANSIENT RESPONSE (3.3V TO 5V) toc1 5V V INC 1V/div 3.3V MAIN LOAD TRANSIENT (LOAD FROM 1mA to 1A, V IN = 5V) toc11 1mA 1A I MAIN V CORE 5mV/div V MAIN 5mV/div 1µs/div 2µs/div MAIN LOAD TRANSIENT (IN DROPOUT LOAD FROM 5mA TO 5mA) toc12 4mA I MAIN 2mA TURN-ON RESPONSE (CIRCUIT OF FIGURE 4), NO LOAD toc13 5V SHDNM 3V VMAIN 2V V CORE 1V 2µs/div V MAIN 5mV/div 1µs/div 4mA I IN 2mA ma 8
PIN NAME FUNCTION 1 SHDNM 2 SHDNC 3 PGND 4 NDRV 5 CVL 6 IN Power Supply Input 7 PDRV 8 CVH Pin Description Shutdown for Main Regulator. A low voltage on SHDNM shuts off the main output. For normal operation, connect SHDNM to IN. Shutdown for Core Regulator. A low voltage on SHDNC shuts off the core output. For normal operation, connect SHDNC to CVL. Power Ground. Ground for NDRV and core output synchronous rectifier. Connect all grounds together close to the IC. N-Channel Drive Output. Drives the main output synchronous rectifier MOSFET. NDRV swings between CVL and PGND. Low-Side Regulator Bypass. CVL is the output of an internal LDO regulator. This is the internal power supply for the device control circuitry as well as the N-channel driver. Bypass CVL with a 1.µF or greater capacitor to GND. When CS- is above the CVL switchover threshold (2.47V), CVL is powered from the main output. P-Channel Drive Output. Drives the main output high-side MOSFET switch. PDRV swings between IN and CVH. The voltage at CVH is regulated at V IN - 4.3V unless the input voltage is less than 5.5V. High-Side Drive Bypass. CVH is the output of an internal LDO regulator with respect to V IN. This is the low-side of the P-channel driver output. Bypass with a 1.µF capacitor or greater to IN. When the input voltage is less than +5.5V, CVH is switched to PGND. 9 REF Reference Voltage Output. Bypass REF to GND with a.22µf or greater capacitor. 1 FBM 11 CS+ Main Output Feedback. Connect FBM to a resistive voltage-divider to set main output voltage between +1.25V to +5.5V. Main Regulator High-Side Current-Sense Input. Connect the sense resistor between CS+ and CS-. This voltage is used to set the current limit and to turn off the synchronous rectifier when the inductor current approaches zero. 12 CS- Main Regulator Low-Side Current-Sense Input. Connect CS- to the main output. 13 FBC 14 GND Analog Ground Core Output Feedback. Connect FBC to a resistive voltage-divider to set core output between +1.V to +5.V. 15 INC Core Supply Input 16 LXC Core Converter Switching Node 9
ON ON C2 1µF C3.22µF 1 OFF 2 OFF 5 9 3 14 SHDNM SHDNC CVL REF PGND GND IN 2.7V TO 5.5V 6 IN 8 CVH INC PDRV NDRV CS+ CS- FBM LXC C1 1µF 15 M1 7 4 11 12 1 16 M2 L C 5.4µH L M 5µH R4 C6 1µF R1 33mΩ CORE C5 1.8V 22µF 1.5A R2 R3 MAIN 3.3V 2A C4 47µF FBC 13 R5 Figure 1. Typical Application Circuit (Low Input Voltage) Detailed Description The dual step-down DC-DC converter is designed to power PDA, palmtop, and subnotebook computers. Normally, these devices need two separate power supplies one for the processor and another higher voltage supply for the peripheral circuitry. The provides an adjustable +1.25V to +5.5V main output designed to power the peripheral circuitry of PDAs and similar devices. The main output delivers over 2A output current. The lower voltage core converter has an adjustable +1.V to +5.V output, providing up to 1.5A output current. Both regulators utilize a proprietary regulation scheme, allowing PWM operation at medium to heavy loads, and automatically switch to pulse skipping at light loads for improved efficiency. Figure 1 is the typical application circuit. Operating Modes for the Step-Down Converters When delivering low output currents, the operates in discontinuous conduction mode. Current through the inductor starts at zero, rises above the minimum current limit, then ramps down to zero during each cycle (see Typical Operating Characteristics). The switch waveform may exhibit ringing, which occurs at the resonant frequency of the inductor and stray capacitance, due to the residual energy trapped in the core when the rectifier MOSFET turns off. This does not degrade the circuit performance. When delivering medium-to-high output currents, the operates in PWM continuous-conduction mode. In this mode, current always flows through the inductor and never ramps to zero. The control circuit adjusts the switch duty cycle to maintain regulation without exceeding the peak switching current set by the current-sense resistor. 1% Duty Cycle and Dropout The operates with a duty cycle up to 1%. This feature extends the input voltage range by turning the MOSFET on continuously when the supply voltage approaches the output voltage. This services the load when conventional switching regulators with less than 1% duty cycle would fail. Dropout voltage is defined as the difference between the input and output voltages when the input is low enough for the output to drop out of regulation. Dropout depends on the MOS- FET drain-to-source on-resistance, current-sense resistor, and inductor series resistance, and is proportional to the load current: Dropout voltage = IOUT [RDS(ON) + RSENSE + RINDUCTOR] 1
CS+ CS- V MIN V VALLEY FB V REF TOFFMIN TONMIN S Q R PON PON V IN PSW V O V CLM S Q NON NSW R V ZERO NONOVERLAP PROTECTION Figure 2. Simplified Control System Block Diagram Regulation Control Scheme The has a unique operating scheme that allows PWM operation at medium and high current, with automatic switching to pulse-skipping mode at lower currents to improve light-load efficiency. Figure 2 shows a simplified block diagram. Under medium- and heavy-load operation, the inductor current is continuous and the part operates in PWM mode. In this mode, the switching frequency is set by either the minimum on-time or the minimum off-time, depending on the duty cycle. The duty cycle is approximately the output voltage divided by the input voltage. If the duty cycle is less than 5%, the minimum on-time controls the frequency; and the frequency is approximately f 2.5MHz D, where D is the duty cycle. If the duty cycle is greater than 5%, the minimum off-time sets the frequency; and the frequency is approximately f 2.5MHz (1 - D). In both cases, the voltage is regulated by the error comparator. For low duty cycles (<5%), the P-channel MOSFET turns on for the minimum on-time, causing fixed-on-time operation. During the P-channel MOSFET on-time, the output voltage rises. Once the P-channel MOSFET turns off, the voltage drops to the regulation threshold, at which time another cycle is initiated. For high duty cycles (>5%), the P-channel MOSFET remains off for the minimum off-time, causing fixed offtime operation. In this case, the P-channel MOSFET remains on until the output voltage rises to the regulation threshold. Then the P-channel MOSFET turns off for the minimum off-time, initiating another cycle. By switching between fixed on-time and fixed off-time operation, the can operate at high input-output ratios, yet still operate up to 1% duty cycle for low dropout. Note that when operating in fixed on-time, the minimum output voltage is regulated; but in fixed off-time operation, the maximum output voltage is regulated. Thus, as the input voltage drops below approximately twice the output voltage, a decrease in line regulation can be expected. The drop in voltage is approximately VDROP V RIPPLE. At light output loads, the inductor current is discontinuous, causing the to operate at lower frequencies, reducing the MOSFET gate drive and switching losses. In discontinuous mode, under most circumstances, the on-time will be a fixed minimum of 4ns. The features four separate current-limit threshold detectors and a watchdog timer for each of its step-down converters. In addition to the more common peak current detector and zero crossing detector, each converter also provides a valley current detector (IVALLEY) and a minimum current detector (I MIN ). I VALLEY is used to force the inductor current to drop to a lower level after hitting peak current before allowing the P- channel MOSFET to turn on. This is a safeguard against inductor current significantly overshooting above the peak current when the inductor discharges too slowly when VOUT/L is small. I MIN is useful in ensuring that a minimum current is built up in the inductor before turning off the P-channel MOSFET. This helps the inductor to charge the output near dropout when di/dt is small (because (V IN - VOUT) / L is small) to avoid multiple 11
CVL SHDNM SHDNC REF REF CS- CS+ SOFT- START CVL FBM CS- CS+ MAIN BUCK FB ON ON CORE BUCK FB FBC CVH IN PDRV CVH NDRV PGND INC LXC PGNDC GND MAIN OUT sumption by limiting the amount of injected gate charge (see Internal Linear Regulators). The main current limit is sensed through a small sense resistor at the converter output (see Setting the Current Limit). Driving SHDNM low puts the main converter in a low-power shutdown mode. The core regulator is still functional when the main converter is in shutdown. Core Step-Down Converter The core step-down converter produces a +1.V to +5.V output from a +2.6V to +5.5V input. The low-voltage input allows the use of internal power MOSFETs, taking advantage of their low R DS(ON), improving efficiency and reducing board space. Like the main converter, the core regulator makes use of an N-channel MOSFET synchronous rectifier, improving efficiency and eliminating the need for an external Schottky diode. Current sensing is internal to the device, eliminating the need for an external sense resistor. The maximum and minimum current limits are sensed through the P-channel MOSFET, while the valley current and zero crossing current are sensed through the N-channel MOSFET. The core output voltage is measured at FBC through a resistive voltagedivider. This divider can be adjusted to set the output voltage level (see Setting the Output Voltages). The core input can be supplied from the main regulator or an external supply that does not exceed +5.5V (see High- Voltage Configuration and Low-Voltage Configuration). The core converter can be shut down independent of the main converter by driving SHDNC low. If the main converter output is supplying power to the core and is shut down, SHDNM controls both outputs. Figure 3 is a simplified block diagram. Figure 3. Simplified Block Diagram pulses and low efficiency. This feature, however, is disabled during dropout and light-load conditions where the inductor current may take too long to reach the IMIN value. A watchdog timer overrides I MIN after the P- channel MOSFET has been on for longer than about 1µs. Main Step-Down Converter The main step-down converter features adjustable +1.25V to +5.5V output, delivering over 2A from a +2.7V to +28V input (see Setting the Output Voltages). The use of external MOSFETs and a current-sense resistor maximizes design flexibility. The offers a synchronous rectifier MOSFET driver that improves efficiency by eliminating losses through a diode. The two MOSFET drive outputs, PDRV and NDRV, control these external MOSFETs. The output swing of these outputs is limited to reduce power con- Internal Linear Regulators There are two linear regulators internal to the. A high-voltage linear regulator accepts inputs up to +28V, reducing it to +2.8V at CVL to provide power to the. Once the voltage at CS- reaches +2.47V, CVL is switched to CS, allowing it to be driven from the main converter, improving efficiency. CVL supplies the internal bias to the IC and power for the NDRV gate driver. The CVH regulator provides the low-side voltage for the main regulator s PDRV output. The voltage at CVH is regulated at 4.3V below V IN to limit the voltage swing on PDRV, reducing gate charge and improving efficiency (Figure 3). Reference The has an accurate internally trimmed +1.25V reference at REF. REF can source no more than 5µA. Bypass REF to GND with a.22µf capacitor. 12
ON ON 1 OFF 2 OFF SHDNM SHDNC IN 2.7V TO 28V 6 IN 8 CVH PDRV NDRV C1 1µF 7 4 M1 L M 1µH C6 1µF R1 21mΩ R2 MAIN 3.3V 2A C4 47µF C2 1µF C3.22µF 5 9 3 14 CVL REF PGND GND CS+ CS- INC FBM LXC 11 12 15 1 16 M2 L C 5.4µH R4 CORE C5 1.8V 22µF 1.5A R3 FBC 13 R5 Figure 4. High Input Voltage Cascaded Configuration Design Procedure Low-Voltage Configuration To improve efficiency and conserve board space, the core regulator operates from low input voltages, taking advantage of internal low-voltage, low-on-resistance MOSFETs. When the input voltage remains below 5.5V, run the core converter directly from the input by connecting INC to IN (Figure 1). This configuration takes advantage of the core s low-voltage design and improves efficiency. High-Voltage Configuration For input voltages greater than 5.5V, cascade the main and core converters by connecting INC to the main output voltage. In this configuration (Figure 4), the core converter is powered from the main output. Ensure that the main output can simultaneously supply its load and the core input current. In this configuration, the main output voltage must be set above the 2.6V minimum input voltage of the core converter. Setting the Output Voltages The main output voltage may be set from +1.25V and +5.5V with two external resistors connected as a voltage-divider to FBM (Figure 1). Resistor values can be calculated by the following equation: R2 = R3 [(V OUTM / V FBM ) - 1] where V FBM = +1.25V. Choose R3 to be 4kΩ or less. The core regulator output is adjustable from +1.V to +5.V through two external resistors connected as a voltage-divider to FBC (Figure 1). Resistor values can be calculated through the following equation: R4 = R5 [(VOUTC / VFBC) - 1] where V FBC = +1.V. Choose R5 to be 3kΩ or less. Setting the Current Limit The main regulator current limit is set externally through a small current-sense resistor, R1 (Figure 1). The value of R1 can be calculated by the following equation: V R1 = CLM 13. IOUT ( ) where VCLM = 8mV is the current-sense threshold, and IOUT is the current delivered to the output. The core converter current limit is set internally and cannot be modified. 13
Careful layout of the current-sense signal traces is imperative. Place R1 as close to the as possible. The two traces should have matching length and width, be as far as possible from noisy switching signals, and be close together to improve noise rejection. These traces should be used for current-sense signal routing only and should not carry any load current. Refer to the Evaluation Kit for layout examples. Inductor Selection The essential parameters for inductor selection are inductance and current rating. The operates with a wide range of inductance values. Calculate the inductance value for either core or main, L MIN : L MIN = (V IN - V OUT ) T ONMIN / I RIPPLE where T ONMIN is typically 4ns, and I RIPPLE is the continuous conduction ripple current. In continuous conduction, IRIPPLE should be chosen to be 3% of the maximum load current. With high inductor values, the begins continuous-conduction operation at a lower fraction of full load (see Detailed Description). The inductor s saturation current must be greater than the peak switching current to prevent core saturation. Saturation occurs when the inductor s magnetic flux density reaches the maximum level the core can support, and inductance starts to fall. The inductor heating current rating must be greater than the maximum load current to prevent overheating. For optimum efficiency, the inductor series resistance should be less than the current-sense resistance. Capacitor Selection Choose output filter capacitors to service the output ripple current with acceptable voltage ripple. ESR in the output capacitor is a major contributor to output ripple. For the main converter, low-esr capacitors such as polymer, ceramic, or even tantalum are recommended. For the core converter, choosing a low-esr tantalum capacitor with enough ESR to generate about 1% ripple voltage across the output is helpful in ensuring stability. Voltage ripple is the sum of contributions from ESR and the capacitor value: For ceramic capacitors, the ripple is mostly due to the capacitance. The ripple due to the capacitance is approximately: V RIPPLE,C L I RIPPLE 2 / 2C OUT V OUT where V OUT is the average output voltage. From this equation, estimate the output capacitor values for given voltage ripple as follows: C OUT = 1/2 L I RIPPLE 2 / (V RIPPLE, COUT V OUT) This equation is suitable for initial capacitor selection. Final values should be set by testing a prototype or evaluation kit. When using tantalum capacitors, use good soldering practices to prevent excessive heat from damaging the devices and increasing their ESR. Also, ensure that the tantalum capacitors surge-current ratings exceed the startup inrush and peak switching currents. The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple at IN, caused by the circuit s switching. Use a low-esr capacitor. Two smaller-value low-esr capacitors can be connected in parallel if necessary. Choose input capacitors with working voltage ratings higher than the maximum input voltage. Typically 4µF of input capacitance for every 1A of load current is sufficient. More capacitance may improve battery life and noise immunity. Place a surface-mount ceramic capacitor at IN very close to the source of the high-side P-channel MOSFET. This capacitor bypasses the, minimizing the effects of spikes and ringing on the s operation. Bypass REF with.22µf or greater. Place this capacitor within.2in (5mm) of the IC, next to REF, with a direct trace to GND. MOSFET Selection The drives an external enhancement-mode P-channel MOSFET and a synchronous-rectifier N- channel MOSFET. When selecting the MOSFETs, important parameters to consider are on-resistance (R DS(ON) ), maximum drain-to-source voltage (V DS(MAX) ), maximum gate-to-source voltage (V GS(MAX) ), and minimum threshold voltage (V TH(MIN) ). V RIPPLE V RIPPLE, ESR + V RIPPLE, C For tantalum capacitors, the ripple is determined mostly by the ESR. Voltage ripple due to ESR is: V RIPPLE, ESR R ESR I RIPPLE 14
PROCESS: BiCMOS Chip Information Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 16 QSOP E16-5 21-55 15
REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED 2 4/9 Corrected R1 resistor value in Figure 4 and other style errors 1, 3, 5, 13, 14 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA 9486 48-737-76 29 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.