Royal Military College of Canada

Microelectronics Lab Cadence Tutorials Layout Design and Simulation (Using Virtuoso / Diva / Analog Artist) Department of Electrical & Computer Engineering Royal Military College of Canada Cadence University Alliance Program Member [Version (1) for Cadence.1999a - Date: July, 1999] Developed by: Mark Hileeto Prof. D. Al-Khalili Important: Please read the following disclaimer Information is provided as is without warranty or guarantee of any kind. No attempt has been made to examine this information with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data until you re confident you can implement any of it s procedures in your environment. Copyright 1999, Royal Military College of Canada, Kingston, Ontario. Permission to duplicate and distribute this document is herewith granted for sole educational purpose without any commercial advantage, provided this copyright message is accompanied in all the duplicates distributed, and with prior permission from the Royal Military College of Canada, Department of Electrical and Computer Engineering. All rights reserved. Cadence is a trademark of Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134

!! "# $%& ' ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( Layout Design & Simulation (Using Virtuoso / Diva / Analog Artist) Table of Contents: 1.0 Introduction & the Schematic Design...1 1.1 Create the Library...3 1.2 Create the Schematic & Symbol Cellviews...3 1.3 Create the TestFixture...3 2.0 Set-up for Simulation...4 3.0 Simulation Waveform Display...5 4.0 Inverter Layout Design Example...6 4.1 Starting up...6 4.1.1 Design Idea...6 4.1.2 Create Layout Cellview...7 4.1.3 Virtuoso Layout Editor and the LSW...8 4.1.4 The Virtuoso Layout Editor...8 4.1.5 The Layer Selection Window (LSW)...9 4.1.6 Setting the Layer Visibility...9 4.2 The Final Layout...10 4.3 The NMOS...11 4.3.1 Introduction & Options Setup...11 4.3.2 Drawing the N-Diffusion (N-Island)...11 4.3.3 The Gate Poly...12 4.3.4 Making Active Contacts and Covering them with Metal-1...13 4.3.5 Refining by following the Design Rules...13 4.3.6 Implement the Design Rules - the Ruler...14 4.3.7 Implement the Design Rules - Selecting Objects...15 4.3.8 Checking Design Rules and Fixing Errors...17 4.4 The PMOS...19 4.5 The Inverter Layout...20 4.5.1 Placing the PMOS and NMOS Cells...20 4.5.2 Listing the Cells in the Inverter Cellview...20 4.5.3 Changing Display Level...21 4.5.4 Flattening the sub-cells...22 4.5.5 Using Path Stitching...22 4.5.6 Miscellaneous design steps and Final Layout...23 4.5.7 Creating Pins...24 4.6 Performing a DRC on the Inverter Layout...27 5.0 Extracting Connectivity from the Layout...28 5.1 The Extracted Cell View...29 (1/2)

6.0 Layout Versus Schematic...31 6.1 Summary of the Cell Views...33 7.0 Simulating the Extracted Cell View...34 8.0 Introduction...37 9.0 Buffer Layout Design...37 9.1 Creating a new Layout Cellview...37 9.2 Flattening the Connect Cell...38 10.0 Perform DRC...40 11.0 Extract the Parasitics...41 12.0 Create the Buffer Schematic and Symbol Views...42 13.0 Layout Versus Schematic (LVS)...43 14.0 Creating the testfixture...43 15.0 Buffer Circuit Pre-Extract Simulation...44 15.1 Waveform Display & Delay Calculation...45 15.2 Load Capacitance Vs. Delay Plot...46 16.0 Buffer Circuit Post-Layout Simulation...49 16.1 Print/Plot Options...50 (2/2)

The Final Layout of the Inverter (W/L)n,p=(1.2/0.6) The figure below represents the final layout that we ll be designing throughout this section. All the necessary Design Layer Rules are illustrated for your convenience. 9A n=0.8* 4D n=0.6* 1A n=2.2 21E n=1 22A n=0.6 9B n=0.8 1D1 n=1.5 9B n=0.8 8F n=0.2 4H n=0.4* 21E n=1 1D1 n=1.5 9C n=0.2 9A n=0.8* 4C n=0.8 8D n=0.6 1F1 n=2 8A n=0.8sq 21E/22E n=1.0 21A n=0.6 8E n=0.2 4A n=0.6 Legend: Rule# Min. Spacing (µm) n FIGURE 1. The Final Layout (showing CMC modified rules in * ) * This CMOS14TB design rule was modified by CMC. See CMOSIS5 Design Rules Modification document. To access from the CIW, select: CMOSIS5 => CMOSIS5 documentation => Design Rules.

RMC - VLSI Lab: Cadence Tutorial Layout Design and Post-Layout Simulation (Using Virtuoso / Diva / Analog Artist) Example(1): Inverter Layout 1.0 Introduction & the Schematic Design In the Analog Flow tutorial, we introduced simulation of an active circuit with an external load capacitance. These simulation results are actually not very accurate, since we did not consider the parasitics (intrinsic and routing capacitances and resistances). In this tutorial, we ll develop the physical Mask Layout of the design. We ll then extract the parasitic effects using the Extract utility, then incorporate these into the design, and perform resimulation (Post-Layout simulation). Design Specifications Schematic Capture Create Symbol Simulation: Pre-Extraction Layout Design Design Rule Check (DRC) Parasitics Extraction Layout Vs. Schematic (LVS) Post-Layout Simulation FIGURE 1. Design Flow. Introduction & the Schematic Design (1/50)

Using the knowledge gained from the Schematic Entry & Analog Simulation Flow tutorial, follow the steps outlined next in the sections to design the Inverter circuit shown in the illustrated figure below. These steps have been repeated in this tutorial again for your convenience. The text illustrations next to the instances are for you to pick the proper instances and properties only. There s no need to include them in your schematic. FIGURE 2. Inverter Schematic. Introduction & the Schematic Design (2/50)

1.1 Create the Library 1. From the CIW, select File => New => Library... 2. In the New Library form, under Directory, double-click on the Mylibs. 3. Fill out the form as follows: Name: mylib_inverter Select Attach to an existing techfile (since we ll be creating mask layout). Click OK. In the Attach Design Library to Technology file form, under Technology Library, select cmosis5, then click OK. 1.2 Create the Schematic & Symbol Cellviews 1. From the CIW, select File => New => Cellview... 2. Fill out the Create New File form as follows: Library Name: mylib_inverter Cell Name: my_inverter Tool: Composer-Schematic Click OK. Create the schematic shown in the previous figure. Create the Symbol Cellview from the Schematic Cellview. Check and Save both cellviews. 1.3 Create the TestFixture Using the knowledge gained from the Analog Flow tutorial, create the testfixture shown in the figure next, with the cellview fields set as indicated below. You may use the Nand2 testfixture generated in the Analog Flow tutorial, and modify it to your inverter design. Library Name: mylib_inverter Cell Name: my_inverter_test View Name: Schematic Introduction & the Schematic Design (3/50)

Use the figure below to create the testfixture. FIGURE 3. Inverter TestFixture. 2.0 Set-up for Simulation Start Analog Artist. Ensure it is set-up properly to simulate active circuits, as explained in the Analog Flow tutorial, and referring to the following figure. FIGURE 4. Analog Artist window. Set-up for Simulation (4/50)

3.0 Simulation Waveform Display Perform a Parametric Analysis, using a value of Cout: 0 -> 0.15p F, and total of 3 steps, the output waveforms are as shown below. Note: From a transistor Instance properties, you can read the expressions used to calculate the values of AD, PD, AS, PS (MOS Drain and Source Area and Perimeter). The output waveform is shown below. Note the delay of approx. 1.2 nsec. between the Input & Output signals, as displayed from Marker A, B data at the bottom of the window. FIGURE 5. Inverter Output Waveforms. We ll next introduce designing the Mask Layout for this simple Inverter. You can exit Analog Artist and Waveform at this time, but keep the CIW active. Simulation Waveform Display (5/50)

4.0 Inverter Layout Design Example 4.1 Starting up 4.1.1 Design Idea To draw the mask layout of a circuit, two main items are necessary at the beginning: 1.A circuit schematic 2.A signal flow diagram 1. Circuit schematic Any physical layout will correspond to a circuit schematic. It is important that the schematic of a functionally correct circuit is present and the layout is drawn according to the schematic (and not the other way around). The schematic will contain exact connection diagram and individual device properties. Two example inverter schematics can be seen below. While both schematics are identical, the one on the right is drawn in a way to resemble the final layout. FIGURE 6. Schematics Vs. Layout Orientations. In this example the NMOS transistor and the PMOS transistor have identical dimensions W=1.2u and L=0.6u Inverter Layout Design Example (6/50)

2. Signal flow diagram A layout can be drawn in a number of different ways. The most important factor determining the actual layout is the signal flow. The layout will almost in all cases be a part of a larger structure or the basic building element of an array of identical blocks. In modern fabrication technologies, more than one physical layer can be used to transfer signals. For example with the fabrication technology used throughout this manual, a total of 4 layers (poly, Metal-1, Metal-2, Metal-3) can be used. The general flow of the signal connections as well as their layers need to be pre-determined. The following is an sample flow diagram used for the example layout: In: Metal-1 P N Vdd! Vss! Out: Metal-1 FIGURE 7. Signal Flow Diagram. In this flow diagram, it has been decided that all signals are on the same layer (blue, Metal-1) and that all signals will travel horizontally. Note that the signal flow diagram is just a concept that you can visualize for a particular circuit, or a simple sketch that you can scribble on the back of an envelope. The actual mask layout will roughly follow this concept. 4.1.2 Create Layout Cellview 1. Form the CIW, select File => New => Cellview... then fill out the form as follows: Library Name: mylib_inverter Cell Name: my_inverter Tool: Virtuoso Click OK. Inverter Layout Design Example (7/50)

4.1.3 Virtuoso Layout Editor and the LSW Two design windows will pop-up after you have entered the design name, as shown in the figure below. FIGURE 8. The LSW & the Virtuoso Layout Editor. 4.1.4 The Virtuoso Layout Editor Virtuoso is the main layout editor of Cadence design tools. There is a small button bar on the left side of the editor. Commonly used functions can be accessed by pressing these buttons. There is an information line at the top of the window. This information line, (from left to right) contains the X and Y coordinates of the cursor, number of selected objects, the travelled distance in X and Y, the total distance and the command currently in use. This information can be very handy while editing. At the bottom of the window, another line shows what function the mouse buttons have at any given moment. Note that these functions will change according to the command you are currently executing. Most of the commands in Virtuoso will start a mode, the default mode is selection, as long as you do not choose a new mode you will remain in that mode. To quit from any mode and return to the default selection mode, the ESC key can be used. Inverter Layout Design Example (8/50)

Browse through the various menus to familiarize yourself with them. 4.1.5 The Layer Selection Window (LSW) The Layer Selection Window (LSW), lets the user select different layers of the mask layout. Virtuoso will always use the layer selected in the LSW for editing. The LSW can also be used to determine which layers will be visible and which layers will be selectable. To select a layer, simply click on the desired layer within the LSW. 4.1.6 Setting the Layer Visibility The Layer Selection Window (LSW) lets you: Choose the layer on which you can draw objects (called the drawing layer or the entry layer) Set which layers are selectable Set layer visibility There are several ways to change the LSW to make layers selectable, visible, and valid. 1. To toggle layer visibility, click the middle-mouse button on a layer. 2. Note the 4 little squares above the various layers: AV: All Visible - Select to set all layers to be visible. You need to redraw next. NV: Non Visible - Opposite to the above. AS: All Selectable - To set all layers to be selectable. This would allow an operation that you d be invoking next to affect all layers (e.g. a delete operation). You need to redraw next. NS: Non Selectable - Opposite to the above. Inverter Layout Design Example (9/50)

4.2 The Final Layout The figure below represents the final layout that we ll be designing throughout this section. All the necessary Design Layer Rules are illustrated for your convenience. 9A n=0.8* 4D n=0.6* 1A n=2.2 21E n=1 22A n=0.6 9B n=0.8 1D1 n=1.5 9B n=0.8 8F n=0.2 4H n=0.4* 21E n=1 1D1 n=1.5 9C n=0.2 9A n=0.8* 4C n=0.8 8D n=0.6 1F1 n=2 8A n=0.8sq 21E/22E n=1.0 21A n=0.6 8E n=0.2 4A n=0.6 Legend: Rule# Min. Spacing (µm) n FIGURE 9. The Final Layout (showing CMC modified rules in * ) * This CMOS14TB design rule was modified by CMC. See CMOSIS5 Design Rules Modification document. To access from the CIW, select: CMOSIS5 => CMOSIS5 documentation => Design Rules. Inverter Layout Design Example (10/50)

We ll use a modular concept in our design by designing a separate cell for the NMOS device, then repeating for the PMOS device. We ll then add those cells into the inverter layout cell, and place the connectivity paths and the pin assignment. 4.3 The NMOS To create the NMOS cellview: Form the CIW, select File => New => Cellview... then fill out the form as follows: 1. Library Name: mylib_inverter 2. Cell Name: my_nmos 3. Tool: Virtuoso 4. Click OK. 4.3.1 Introduction & Options Setup Now we will start drawing our first transistor. which will be the NMOS transistor of the CMOS inverter. From the schematic, we know that this transistor has a channel width of 1.2u. The width of the transistor will correspond to the width of the active area. We will select the n-diffusion layer (nisland) and draw a rectangular active area to define the transistor. Let s set the Grid Resolution first to aid us in the design process. There are 2 types of grid points: Minor & Major. We ll set the minor grid dots to display every 0.1 microns, and the major ones to display every 0.5 microns. Form the Virtuoso Editor, select Options => Display Set the Minor Spacing to: 0.1 Set the Major Spacing to: 0.5 Select Options => Layout Editor Set the Aperture to 0.1 (the mouse step value) Now you ll need to redraw the layers. To do so, select Window => Redraw on the Virtuoso Editor window. This displays the new grid resolution points. Click on the Zoom-In icon on the left until you can see both the major dots (bright) and the minor dots (less bright). We can now draw using the minor dots as a guide for a 0.1 micron distance. 4.3.2 Drawing the N-Diffusion (N-Island) 1. In the LSW, left-click on the nisland layer to select it. This implies that any operation you do next will only affect this layer. 2. Select the Rectangle icon, to draw an nisland rectangle. Note the text at the bottom of the Virtuoso Editor window directing you to Inverter Layout Design Example (11/50)

point at the first corner of the rectangle We ll always observe the messages displaying at the bottom of the window for directions. 3. Draw a rectangle of vertical dimension 1u (10 vertical minor dots), and an arbitrary horizontal dimension of, say, 2.5 micron (5 major dots). We ll adjust it shortly. 4. Note the Status Banner above showing the various dimensions. Descriptions are shown in the figure below. Cursor Coordinates Difference between the last coordinate entered and the current coordinates nisland Layer X-Y Coord. FIGURE 10. Descriptions of the Layout Editor window. 4.3.3 The Gate Poly The second step is to draw the gate. We will use a vertical polysilicon rectangle to create the channel. Note that the length of the transistor channel will be determined by the width of this poly rectangle. 1. Select poly dg layer from the LSW. This uses the poly layer for layout drawing (poly-pn uses the poly layer for pin assignment). FIGURE 11. Selecting the Poly Layer. Inverter Layout Design Example (12/50)

2. Let s place a rectangle of arbitrary dimension, say 1 micron width, and extending a micron or so over the diffusion area. 3. Therefore, click on the Rectangle icon to activate the rectangle drawing mode. 4. Draw the poly rectangle as shown below. Note the status bar on the top right displaying cmd:rectangle, illustrating that the present active mode is rectangle drawing. 5. Press the ESC key on your keyboard to deactivate the Rectangle mode. FIGURE 12. A non-refined poly-over-diffusion. 6. This rough sketch of the poly needs to be adjusted later to comply with the CMOSIS5 design rules. We ll do that shortly, but let s first draw the metal contacts, in order to complete the basic masks layout. 4.3.4 Making Active Contacts and Covering them with Metal-1 The contact is composed of a metal1 mask, and a contact cut, which connects the metal1 above to the source/drain diffusion areas. Repeat as before, by drawing arbitrary rectangles for the contact cuts using the contact-dg layer, and drawing arbitrary metal1 rectangles using metal1-dg layer, as shown below. FIGURE 13. The unrefined NMOS transistor Layout. Voila! Here s our nmos transistor... If it were that straightforward, the process technology companies would be out of business by now :-) Let s next adjust the dimensions to follow the CMOSIS5 Mask Layout Design Rules. 4.3.5 Refining by following the Design Rules It s a usual common practice to first start by drawing a minimum-size transistor. We can later follow by stretching the layers and dimensions to suite our required dimensions. Inverter Layout Design Example (13/50)

Referring to figure 8 earlier (The final Layout), the Rules Number and the Minimum Allowed Dimension have been illustrated for your convenience, instead of having to browse through a hundred or so design rules! The rules illustrated on the drawing are representative of the CMOSIS5 rules. CMC has relaxed some rules, by increasing the minimum dimensions. About 10 or so rules have been relaxed accordingly. At a later stage, we ll have to indicate to the tool that we re using the relaxed rules. A list of the modified rules could be accessed from the CIW. We ll re-emphasis the note mentioned before on how to get the modified rules. This CMOS14TB design rule was modified by CMC. See CMOSIS5 Design Rules Modification document. To access from the CIW, select: CMOSIS5 => CMOSIS5 documentation => Design Rules. This procedure would be followed for any other library you may wish to use. As an example, the TSMC s cmosp35 library has a similar relaxed rules list provided from the CIW by CMC. We ll leave you to go through the much-shorter modified list to get a feel of the Rules Description, however, we ll supply the pertinent rules as we go. TABLE 1. Design Rules Required for drawing the NMOS Device Rule # Rule Description The next sections will illustrate how to implement the Design Rules. 4.3.6 Implement the Design Rules - the Ruler CMOSI5 Min. Size (µm) 1. Click on the Ruler icon. As an alternative, select Window => Create Ruler. CMC s Modified Min. Size (µm) 4A Poly min. width 0.6 no change 4D Min. Poly overlap of N/P-island over Field 0.45 0.6 21A N-island min. width 0.6 no change 8A Contact required size (Square) 0.8 X 0.8 no change 8D Min. island contact spacing to poly 0.6 no change 8E Min. enclosure by N/P-island 0.2 no change 21A N-island min. width 0.6 no change FIGURE 14. Create Ruler form. Inverter Layout Design Example (14/50)

2. A message at the bottom of the Layout Editor window asks you to point at the first point of the ruler. The ruler aids in measuring dimensions more easily. draw rulers across all boundaries that you think you d need to stretch next, as shown below. FIGURE 15. Rulers to aid in stretching layers. 3. Press the ESC key when done to deactivate the Ruler command. 4.3.7 Implement the Design Rules - Selecting Objects After you draw objects or layers, you can edit them. You d first need to select them. There are 2 selection modes: Full & Partial. Full: You select the entire layer / object. Partial: You can either select the entire object, a part, an edge, or a corner of it. To toggle between the 2 modes, use the F4 function key on your keyboard. The selection mode is displayed in the status banner of the window. (F) Full mode. (P) Partial mode. 1. let s then start by moving the Poly layer mask. 2. Make sure the Full mode of selection is in effect (toggle F4). Move over the poly layer until a dotted line surrounds its entire poly boundary. Click once to select it. 3. Move the mouse slightly, and notice the change in it s shape to a 4-way arrow. 4. Click on the poly layer now, and drag it (without releasing the left-mouse button) to any farther location. Inverter Layout Design Example (15/50)

5. Click outside the masks layers area to deselect all layers. 6. Now we ll have more space to stretch the left contact and it s overlap metal. 7. Click F4 to toggle to partial mode, since we ll be stretching edges, rather than moving whole layers. Ensure the selection mode shows (P). 8. Move to the right edge of left contact. A dotted line should highlight that edge alone. 9. Click once on that right edge, and move the mouse slightly. Notice the change in the shape of the mouse pointer from an arrow to a limiting arrow. 10.Now is the time to drag the edge to reach the 0.8 ruler mark, as illustrated below. An alternative method would be to click on the Stretch icon, and follow the instructions at the bottom of the Layout Editor window. FIGURE 16. Stretching Layer Edges. 11.Repeat these ideas for all the other layers. 12.If you make an error, click on the Undo icon. Also, press the ESC key on your keyboard, and click occasionally outside the layout editing area to release any editing mode or unselect all layers. 13.Now you d realize the reason we changed the (Options=> Layout Editor => Aperture => 0.1) in order to set the min. aperture step to 0.1 microns for precision editing. 14.You may first modify the left contact and its metal1 layers, then select both of them, and press the c key on your keyboard to copy them to the right location (drain/ Source). Inverter Layout Design Example (16/50)

15.Finally, you should have the NMOS transistor displaying as shown below. FIGURE 17. The Final NMOS transistor layout. 4.3.8 Checking Design Rules and Fixing Errors Before saving the NMOS transistor layout, you need to check the design against your design rules. Interactive design rules checking is part of the Diva program. The interactive Design Rule Checker (DRC) uses rules defined in the DIVAdrc.rul file. They have been defined for you as part of the cmosis5 design kit files. DRC flags the errors it finds by drawing polygons around the errors on the marker layer with the purpose error. This layer usually appears as a blinking layer and is not selectable. The DRC program removes the error flag polygons automatically when you run DRC again. 1. Select Verify => DRC... The DRC form appears. 2. Again, you are encouraged here to go to the CIW, and select CMOSIS5 => CMOSIS5 documentation => Design Rules Inverter Layout Design Example (17/50)

Read the part that talks about setting the switch. In our case here, we ll not have to select that switch, as we re using the CMC s relaxed rules. For the sake of ensuring that you can use the switch, click on the Set Switches button, and verify you have the HP14TB switch available. Note also the Rules File and Rules Library defined on the form. FIGURE 18. The DRC form. 3. Expand the CIW vertically in order to view the messages that will follow. 4. Select OK to run the DRC program. You should get only 1 rule violation at the end of the DRC process, as follows: ********* Summary of rule violation for cell "my_nmos layout" ********* # errors Violated Rules 1 1K: nisland outside nwell to substrate contact spacing > 25um 1 Total errors found 5. Note the Rule # 1K above. It states as follows (from the CMOSIS5 rules document): Rule # Rule Description 1K Any active N-island outside N-wells can be no further than 25µm from the contact1 of a substrate contact by metal1 or butting contact. The contacts must be connected to VSS (lower potential) by continuous metal 1, 2, or 3. CMOSI5 Min. Size (µm) CMC s Modified Min. Size (µm) 0.6 no change 6. This violation is okay then, since we have not placed the nwell yet, as this will be at a later stage during the PMOS layout design. 7. The easiest way to correct errors is to delete the controversial layers, and redraw them properly, by selecting each layer and pressing the Delete key on your keyboard. 8. Now we can delete the error marker. Select Verify => Markers => Delete all... Inverter Layout Design Example (18/50)

9. Select OK on the form that appears. 10.To clear the rulers, select Window => Clear All Rulers. 11.To save the design, select Design => Save. 4.4 The PMOS To create the PMOS cellview: Form the CIW, select File => New => Cellview... then fill out the form as follows: 1. Library Name: mylib_inverter 2. Cell Name: my_pmos 3. Tool: Virtuoso 4. Click OK. We ll leave you to draw the PMOS transistor, using the pisland layer, and similar to the NMOS transistor. Note here the N-Well spacing of 1.5 micron around the pisland. The new Design Rules are described in the table below, in addition to the previous ones in Table 1. The figure to follow illustrates the final layout. TABLE 2. Design Rules Required for drawing the PMOS Device Rule # Rule Description CMOSI5 Min. Size (µm) CMC s Modified Min. Size (µm) 22A Pisland min. width 0.6 no change 1A N-Well min. width 2.2 no change 1D1 Min. enclosure of a P-island - 3.3 V nominal VDD 1.5 no change FIGURE 19. The final PMOS transistor layout. Inverter Layout Design Example (19/50)

When done, save the design first. Perform then a DRC. The following are the errors/violations that you should get on the CIW: ********* Summary of rule violation for cell my_pmos_min layout ********* # errors Violated Rules 1 1H2: nwell contact to nwell spacing > 3.2um (or no nwell co... 1 1I: pisland inside nwell to nwell contact spacing > 25um 2 Total errors found These violations should disappear later when you place the NMOS and PMOS transistors together, as described in the next section. 4.5 The Inverter Layout Here, we ll instantiate the pmos and nmos cells into the new inverter layout, connect them according to the Design Rules, place the I/O pins, and finally perform a DRC on the layout. 4.5.1 Placing the PMOS and NMOS Cells To open the Inverter cellview (we created it a few sections back): Form the CIW, select File => Open 1. Library Name: mylib_inverter 2. Cell Name: my_inverter 3. View Name: Layout 4. Click OK. 5. Click on the Instance icon, and select to place the pmos and nmos instances in the inverter s window. 6. Note the box surrounding the cells, showing only the cell names (my_pmos, my_nmos). 4.5.2 Listing the Cells in the Inverter Cellview 1. Select Design => Hierarchy => Tree. Inverter Layout Design Example (20/50)

2. Select OK to Display Current to Bottom lists of views. The following widow appears. FIGURE 20. Hierarchy Tree. Tree shows all the hierarchy contained in my_inverter. The parenthesis (1) indicate the number of instances of a particular cell. 4.5.3 Changing Display Level To fit the design into the window, press the f key. The top-level of the hierarchy is denoted as level 0. At this level, you only view the outlines of the pmos & nmos cells you placed into your top level design (my_inverter). You can display the details of the sub-cells by changing the display level. Select Options => Display. The Display Options form appears. Change the To Level to say 3. This is more than we d need, as we have only levels 0 and 1 in this design. Click OK. FIGURE 21. Display Options window. Inverter Layout Design Example (21/50)

The window displays all cells sub-levels. To quickly display level 0, press the Control-f bindkey. To toggle to level 1 through 3, press Shift-f. 4.5.4 Flattening the sub-cells Normally, you d have to draw the connections between the instances at the top-level, as they are not usually drawn in a separate cell. This requires moving the contents of the subcells up to the top-level, i.e. flattening the cells so they are no longer considered as instances, enabling path routing to be performed more deliberately. Display level 0 by pressing Control-f. Select the nmos cell, then press Control as you click to select the pmos cell. the Control key allows multiple-object selection. Select Edit => Hierarchy => Flatten... Since we need to move the contents of the sub cells up one level, the form should be set correctly. Click OK to accept. All layers are now selectable (flattened). Finally, select the entire pmos or nmos transistors and move them to vertically align their contacts. Refer to the final layout figure presented before to get an idea of the required alignment lines. Follow the following rule spacing: Rule # Rule Description 1F1 N-Well min. spacing in x and y to an external N- island. 3.3 V nominal VDD. CMOSI5 Min. Size (µm) CMC s Modified Min. Size (µm) 2.0 no change 4.5.5 Using Path Stitching We ll use the Path command to draw the final connections. This allows for continuous manual outlining of a path using a certain layer. You can then switch to another layer as you continue drawing, and the tool will automatically place the appropriate contact/via as you go. The library provided by the vendor has to have that via/contact already defined in its set. Snapping the cursor to objects is called Gravity. It is turned on by default, and is helpful when creating instances and devices. Turning it off makes it easier to draw paths. To toggle gravity, move the cursor inside the Layout Editor window, and press the g bindkey. Note the message on the CIW stating Turned off gravity. Back again to the Signal Flow Diagram, we ve already decided we ll use metal1 for all inputs, outputs, and supply rails. This means we ll have to have a contact at the input to connect the metal1 feeder to the poly gate of the transistors. Also, it s customary to draw the supply rails (VDD, VSS) a little wider than their minimum. We now implement the above concepts. 1. On the LSW, select the poly layer. Inverter Layout Design Example (22/50)

2. Click on the Path icon. A form appears. 3. We know from the design rules (Rule # 4A) that the minimum poly width is 0.6 micron. Ensure that it reads 0.6 in the width field of the form, as shown below. Also note that the justification is centre, meaning that the mouse pointer will trace the centre line of the path as you draw it. FIGURE 22. Create Path window. 4. Select the layout Editor window by clicking on its title bar. The messages bar at the bottom directs you to point at the first point of the path. Do so at the nmos poly centre line, and trace through till you reach the pmos poly side, then double-click for final placement. Refer to the final layout drawing presented earlier for more comprehensive illustrations. 5. Draw the following using the design rules in the following table: metal1-poly contact Drain metal1 path Gate input metal1 path VDD & VSS paths Substrate contacts 4.5.6 Miscellaneous design steps and Final Layout Extend the N-Well to enclose the substrate contact: The substrate on which the transistors are built must be properly biased. The way to do this is to add substrate contacts. The NMOS transistors are build on a p-type substrate, we will have to create a p-type substrate contact. Likewise for the nmos transistor. Inverter Layout Design Example (23/50)

One note worth mentioning here is that the p+ and n+ layers in this process are automatically drawn to enclose the p-island and n-island respectively during fabrication pre-processing. Your design stream is represented in a GDSII format which can be automatically produced by the Cadence tools after completing your design layout masks. Other technologies/processes may, however, require you to draw the p+ and n+ masks. Try to utilize the copy-paste facility while placing the contacts. VDD rail may be copied and inverted to create its VSS couterpart. A final layer called the prbound defines the cell. This defines the cell boundary when selecting it. Place the prbound around the inverter cell. The N-Well and the supply rails can eventually extend beyond the prbound layer, to connect to other adjacent cells. The new Design Rules are described in the table below, in addition to the ones described earlier. TABLE 3. Design Rules Required for drawing the Final Inverter Layout Rule # Rule Description CMOSI5 Min. Size (µm) CMC s Modified Min. Size (µm) 9A Metal1 min. width 0.6 0.8 9B Min. metal1 spacing 0.8 no change 9C Min. metal1 overlap of contact 1 0.2 no change 4H Min. poly spacing to related N/P-island over field 0.2 0.4 21E/ 22E Min. P-island to N-island spacing 1.0 no change 4.5.7 Creating Pins Now that all the connections are complete, we need to add some information used by other Cadence tools. We need to add net labels to help in diagnosing problems found by the Layout Versus Schematic (LVS) program. The LVS will be addressed shortly. Also, we need to create pins. Pins are used by the Cadence tools as follows: Pins define the connectivity between the hierarchy levels. That is, a pin indicates where this cell can connect to routing or to other instances when the cell is placed into a larger design. Pins specify the access direction for Cadence Routing tools. The LVS program checks to see if you have placed labels that conflict with the nets you define for the pins. Inverter Layout Design Example (24/50)

Here, we ll draw the following pins: TABLE 4. Inverter Pin Designation Pin Name Input/Output Access Direction Layer vdd! I/O top, left, right metal1-dg vss! I/O bottom, left, right metal1-dg In input top, bottom metal1-dg Out output top, bottom metal1-dg 1. In the LSW, click-left on the metal1-dg layer. 2. Select Create => Pin. The Create Symbolic Pin form appears. You will be using shape pins in this tutorial, not symbolic pins. Ensure the Shape pin form appears, and if it did not, click on the shape pin mode button. The shape pin form should then appear. 3. Fill in the Terminal Name field as follows: vdd! vss! In Out 4. To associate a name with a pin, click left on Create Label. 5. Set the access direction to top, left, right by clicking on bottom to turn it off. FIGURE 23. Create Shape Pin form. Inverter Layout Design Example (25/50)

6. Draw the rectangle for the vdd! pin coincident with the power line at the top of the inverter, as shown below. Start the vdd! pin at this corner Finish the vdd! pin at this corner The vdd! appears after you click left on the second corner. FIGURE 24. Drawing the vdd! pin. 7. Now vdd! disappears from the Create Shape Pin form. the first name listed becomes vss!. 8. turn on and off the access direction according to the table given before, and draw the remaining pins. Inverter Layout Design Example (26/50)

9. When done, click on the Save icon to save the design. The layout should appear as shown below. FIGURE 25. The Final Inverter Layout. 4.6 Performing a DRC on the Inverter Layout The Design Rule Checker checks your design against physical design rules defined in the divadrc.rul file located in the CellTechLib directory. Select Verify => DRC..., then click OK. You should get no errors. Inverter Layout Design Example (27/50)

5.0 Extracting Connectivity from the Layout Circuit extraction is performed after the mask layout design is completed, in order to create a detailed net-list (or circuit description) for the simulation tool. The circuit extractor is capable of identifying the individual transistors and their interconnections (on various layers), as well as the parasitic resistances and capacitances that are inevitably present between these layers. Thus, the "extracted net-list" can provide a very accurate estimation of the actual device dimensions and device parasitics that ultimately determine the circuit performance. The extracted net-list file and parameters are subsequently used in Layout-versus-Schematic comparison (LVS) and in detailed transistorlevel simulations (post-layout simulation). The mask layout only contains physical data. In fact it just contains coordinates of rectangles drawn in different colors (layers). The extraction process identifies the devices and generates a netlist associated with the layout. Make sure you have a layout window with a finished design ready. Make sure that the design does not contain any DRC errors. From the Layout Editor window, select Verify => Extract. A new window with extraction options will appear. The default options will only extract ideal devices. This ideal case would result in a list much similar to the schematic. For a more accurate representation, however, we will have to take the parasitic effects into account. To enable the extraction of parasitic devices, a selection parameter called a switch has to be specified. You can type the switch into the designated box, or you can select it from a menu using the Set Switches option. Click on it, and drag to highlight both switches, then click OK. FIGURE 26. The Extract form. Extracting Connectivity from the Layout (28/50)

The switches specified in the example (above) to enable extracting the parasitic capacitances are: -> Cparasitic? : Extracts the parasitic capacitances. -> extract_side_cap : Extracts the side_wall capacitances. No switch was available in the available design kit to extract parasitic resistances. However, this should not be a major concern, as the design is relatively small. Check the Command Interpreter Window (the main window when you start Cadence) for errors after extraction. Following a successful extraction you will see a new cell view called extracted for your cell in the library manager. See the following section for accessing the extracted view. The CIW should display the following lines to illustrate the creation of the extracted cell view : saving rep mylib_inverter/my_inverter/extracted DRC started...thu Jun 24 00:01:21 1999, completed...thu Jun 24 00:01:31 1999 CPU TIME = 00:00:02 TOTAL TIME = 00:00:10 ********* Summary of rule violation for cell my_inverter layout ********* Total errors found: 0 5.1 The Extracted Cell View Following the extraction step a new cellview is generated in your library. This cell view is called extracted view. Try loading the cellview. It will display a layout that looks almost identical to the layout you just extracted. Extracting Connectivity from the Layout (29/50)

You will notice that only the I/O pins appear as solid blocks and all other shapes appear as outlines. Toggle between shift-f and control-f to see different levels of the hierarchy. FIGURE 27. The Extracted Cellview. This will reveal a number of symbols. If you zoom in you will be able to identify individual elements, such as transistors and capacitors. You will notice that the parameters (e.g. channel dimensions) of these devices represent the values they were drawn in the layout view. Apart from your actual devices you will notice a number of elements, mainly capacitors in your extracted cell view. These are not actual devices, they are parasitic capacitances, side effects formed by different layers you used for your layout. The next step will be to correspond the extracted netlist to that of the schematic. This is called the Layout Versus Schematic (LVS) checking. This will ensure that the schematic that we have drawn and the layout are identical. Extracting Connectivity from the Layout (30/50)

6.0 Layout Versus Schematic In this step we are going to compare the schematic and the extracted layout to see if they are identical. 1. Open the schematic cellview of the inverter design. 2. From the Verify menu in the Extracted window, select the option LVS. 3. If you had previously run a LVS check, this would pop-up a small warning box. Make sure that the option Form Contents is selected in this box. 4. The top half of the LVS options window is split into two parts. The part on the left corresponds to the schematic cell view and the right part corresponds to the extracted cell view that are to be compared. FIGURE 28. The LVS form. 5. Make sure that the entries in these boxes represent the values for your circuit. 6. Set the Priority field to 20. Priority 0, being the default, slows down other actions on the system. 7. Although there are a number of other options for LVS, the default options will be enough for basic operations, select Run to start the comparison. Layout Versus Schematic (31/50)

8. The comparison algorithm will run in the background, the result of the LVS run will be displayed in a message box. Be patient, even for a very small design the LVS run can take some time (minutes). FIGURE 29. LVS Job Status. 9. The succeeded message in the above message box, indicates that the LVS program has finished comparing the netlists, NOT THAT THE CIRCUITS MATCH. It might be the case that the LVS was successful in comparing the netlists and came up with the result that both circuits were different. 10.To see the actual result of an LVS run you have to examine the output of the LVS run. The Output option is right next to the Run command. FIGURE 30. Output Results of an LVS process. 11.You can take a look at the complete LVS result here. The most important part of the report can be found in the figure above. It states that the netlists did indeed match. If you discover that there is a mismatch, you must go back to the layout view and correct the error(s). 12.Most of the other options on the LVS form, are for finding mismatches between two netlists and to generate netlists that include only parasitic effects relevant to one part of the circuit. Layout Versus Schematic (32/50)

13.If your job did not get completed, click on Info in the LVS form and look at the log. This tells you what caused the job to terminate, and when. 6.1 Summary of the Cell Views So far you have created a number of cell views corresponding to the same circuit. In this section we want to review all of these cellviews and discuss why they are used. 1. Schematic view: For any design, the schematic should be the first cell view to be created. The schematic will be the basic reference of your circuit. 2. Symbol view: After you are done with the schematic, you will need to simulate your design. The proper way of doing this is to create a separate test schematic and include your circuit as a block. Therefore you will need to create a symbol. 3. Layout view: This is the actual layout mask data that will be fabricated. It can be generated by automated tools or manually. 4. Extracted view: After the layout has been finalized, it is extracted, devices and parasitic elements are identified and a netlist is formed. 5. Test Schematic: A separate cell is used to as a test bench. This test bench includes sources, loads and the circuit to be tested. The test cell usually consists of a single schematic only. Layout Versus Schematic (33/50)

7.0 Simulating the Extracted Cell View After a successful LVS you will have two main cell views for the same circuit. The first one is the schematic, which is your initial (ideal) design, the second is the extracted, that is based on the layout and in addition to the basic circuit includes all the layout associated parasitic effects. Since both of these views refer to the same circuit they can be interchanged. In this example we are going to re-run the simulation example, but we will make the simulator to use the extracted cell view instead of the schematic cell view. Make sure that you are in the test schematic, that you used to simulate your design earlier. 1. Start Analog Artist using Tools => Analog Artist. The Analog Artist window will pop-up. 2. From the Setup menu choose the Environment option. A new dialog box controlling various parameters of Analog Artist will pop-up. The line that we will have to alter is called the Switch View List. This entry is an ordered list of cell views that contain information that can be simulated. The simulator (in fact the netlister) will search until it finds one of these cellviews. The default entry does not contain an extracted cellview. We will simply add an entry for extracted cellview in front of the schematic cellview. As a result of this modification, the simulator will use the extracted cell view of the cell, if one is available. Click OK on the form. FIGURE 31. Adding the Extracted view in the Switch List in Analog Artist s Environment. Simulating the Extracted Cell View (34/50)

3. Select Analyses => Choose, and enable the 13nsec transient analysis as earlier before. 4. Select Variables => Copy from CellView. 5. Select the In and Out nets to display the voltages as before. 6. Select Tools => Parametric Analysis, to set the Cout values. 7. use a value of Cout: 0 -> 0.15p F, and total of 3 steps, as before. 8. From the form, select Analysis => Start. 9. The Waveform output is as shown below. FIGURE 32. Post-Layout Extracted Simulation Results. Simulating the Extracted Cell View (35/50)

For comparison, we ve included the Pre-Layout Simulation Results below. FIGURE 33. Schematic (Pre-Layout) Simulation Results. Next, we ll introduce the Cascaded Inverters design referred to in the previous Schematic Entry & Analog Design flow. Simulating the Extracted Cell View (36/50)

Example(2): Hierarchical Layout Design Simple Buffer Design 8.0 Introduction For convenience, the steps mentioned in the Buffer design example referred to in the previous Schematic Entry & Analog Design flow will be repeated in the last section of this example. The buffer is composed of 2 inverters in cascade. 9.0 Buffer Layout Design 9.1 Creating a new Layout Cellview Just like we did when we instantiated the Symbol cellview for the inverter to create the Buffer, we ll perform a similar step for the layout cellview. 1. For a change, press F6 to open the Library Manager. 2. Select the inverter library, as set from before. 3. Select File => New =>Cellview. Fill in the data as follows, then click OK: Library: your_library Cell: my_buff1 Tool: Virtuoso (Viewname becomes Layout automatically) 4. The Layout window opens. Click the Instance icon, then click on Browse on the form that opens. 5. Select: my_inverter, Layout view. 6. Click on the layout window to place two of it by the coordinate axis. 7. A red box reads the layout name (my_inverter). This is the top level of the layout. 8. Press Shift-f to display all levels of the layout. Introduction (37/50)

9. Details of the inverters show, as illustrated below. FIGURE 34. The unflattened inverter cells. 9.2 Flattening the Connect Cell Normally, you would draw the connections between the instances in the Buffer at the top level, called level 0. You cannot access the 2 inverter cells as they stand now, as they are in level 1. You d have to move the data in the cells up one level to level 0, i.e. Flatten the cells. 1. Select both instances. 2. To display the outlines of the instances, press Control-f. 3. Select Edit => Hierarchy => Flatten. Buffer Layout Design (38/50)

4. The flatten Form appears. You need to move the contents of the inverters up just one level. The default form settings are set correctly. FIGURE 35. Flatten Cells form. 5. Click left on the outline of one of the inverter cells. 6. Click left on OK. The instance outline disappears and the data in the inverter cell appears. Repeat for the other cell. 7. To display all levels, press Shift-f. 8. A good choice is top save your design at this time. Click the Save icon. 9. Press F4 to invoke partial selection mode. 10.Use Path Stitching as before to connect the metal-1 output of the first inverter to the metal-1 input of the second one. You may just select an edge and stretch it to the next metal edge. Do so for the vdd! and vss! rails also. 11.As before, to create the pins, first select the metal1-dg layer on the LSW. 12.Select Create => Pin => (Shape Pin) => (Rectangle) Fill in the form with: vdd! vss! In Out_all, as shown below. FIGURE 36. Adding the Pins. 13.Follow the instruction at the bottom of the Layout window to place each pin. Buffer Layout Design (39/50)

14.Save the Buffer layout. FIGURE 37. The final Buffer layout. 10.0 Perform DRC At this stage, you want to verify your design is clean of any Design Rule Violations (DRV s). 1. From the Layout view, select Verify => DRC..., then click OK on the form. 2. Since you had not followed the layout rules in placing (abutting) the cells together, most likely you ll get DRV s. Observe the CIW and the layout window. Displayed below are 2 violation descriptions from the CIW, and their corresponding markers displayed in the Layout window. ********* Summary of rule violation for cell "my_buff1 layout" ********* # errors Violated Rules 1 1B: nwell at same potential < 1.6um 1 1F1: nwell to nisland spacing < 2.0um 2 Total errors found Perform DRC (40/50)

FIGURE 38. Layout with Violations. 3. First connect the nwells together, as wells are usually connected, and adjust the nwell to nisland spacing to be a minimum of 2.0um. Use the ruler to assist you. 4. Use the steps: Verify => Markers => Find => Apply This enables you to identify each individual marker location and it s corresponding violation rule. In this design, fixing the nwell violation will clear off the second violation. 5. Run DRC again. You should get no violations this time. 6. Save the Design. 11.0 Extract the Parasitics 1. Use Verify->Extract with Flat switch turned on to extract the layout for flat LVS. 2. To enable parasitic extraction, Set Switches to enable both the Cparasitic? and the extract_side_cap. 3. Click OK on the form. The CIW should display no errors. Extract the Parasitics (41/50)