Royal Military College of Canada

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1 Microelectronics Lab Cadence Tutorials Schematic Entry & Digital Simulation (Using Composer / Verilog-XL / Simwave) Department of Electrical & Computer Engineering Royal Military College of Canada Cadence University Alliance Program Member [Version (1) for Cadence.1999a - Date: July, 1999] Developed by: Mark Hileeto Prof. D. Al-Khalili Important: Please read the following disclaimer Information is provided as is without warranty or guarantee of any kind. No attempt has been made to examine this information with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data until you re confident you can implement any of it s procedures in your environment. Copyright 1999, Royal Military College of Canada, Kingston, Ontario. Permission to duplicate and distribute this document is herewith granted for sole educational purpose without any commercial advantage, provided this copyright message is accompanied in all the duplicates distributed, and with prior permission from the Royal Military College of Canada, Department of Electrical and Computer Engineering. All rights reserved. Cadence is a trademark of Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134

2 !! "# $%& ' ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( Schematic Entry for Digital Designs (Using Composer) Table of Contents: 1.0 Introduction and the Design Hierarchy Creating a New Library Creating a New Cell View Modifying the Bus Range Order and Pin Sorting Options Schematic Capture and Creating a New Symbol Creating a Symbol Cellview from a Pin List Modifying the appearance of the Symbol Creating the Top-Level Schematic Adding and Naming the Schematic Pins, Wires, and Buses Adding Pins Adding Wires and Buses Updating Defaults Naming the Wires and Buses Attaching the Border Saving the Simulation Session Saving the System Environment to a file Saving the System State to a file Descending into the design and Creating the Sub-Modules Descending into the design Creating the Full-Adder Symbol Placing the Symbols Connecting and Naming the Nets Creating the Full-Adder and Half-Adder Cells Check & Save, Print, and Exit...19 ( P.T.O. --> ) Digital Flow - TOC (1/2)

3 !! "# $%& ' ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( Digital Simulation (Using Verilog-XL Integration) Table of Contents: 10.0 Introduction to Verilog-XL Integration Starting Verilog-XL Integration Setting-up Verilog-XL Integration The Verilog-HDL Stimulus File Running the Simulation...26 Digital Simulation Waveform Display (Using SimWave) Table of Contents: 15.0 Introduction to SimWave Displaying the Waveforms More about SimWave The Time Cursors Deleting or Relocating Signals Saving the Setup file Re-Simulating Printing Waveforms Removing the Simulation Files and Exiting...32 Digital Flow - TOC (2/2)

4 RMC - VLSI Lab: Cadence Tutorial Schematic Entry for Digital Designs (Using Composer) 1.0 Introduction and the Design Hierarchy Pre-requisites: Completed the Introduction to Cadence & Unix tutorial. In this tutorial, you ll build a 4-Bit Adder circuit using the Cadence schematic entry tool, Composer. Start by creating a sub-directory to the cadence directory, called Mylibs. In Mylibs, you ll store all your design libraries and cells in order to organize the work. In a Unix terminal, type the following from your home directory: mkdir ~/cadence/mylibs We ll create a new library, called mylib_adder-4, in order to separate our work from the other predefined libraries. It will, in turn, contain the new Cell, add_4bit_top, the new top-level schematic, with input and output ports. The add_4bit_top Cell will contain a 4-bit-adder symbol, add_4bit. The symbol will be composed of 4 similar sub-modules (also called Cells) of full-adders (add_full). Each is composed of sub-sub-modules (also called Cells) of half-adders (add_half). The design hierarchy is as illustrated below. We, therefore, note the modular architecture of Cadence in order to allow individual selection of a cell for a specific use without having to select the full hierarchy- if that cell is imbedded in a tree. This allows for cell reuse. add_4bit_top add_full add_full add_full add_full add_half add_half FIGURE 1. The Design Hierarchy Introduction and the Design Hierarchy (1/32)

5 2.0 Creating a New Library 1. Start Cadence as explained in the Introduction to Cadence & Unix tutorial, by typing the alias cadence from a Unix terminal prompt. 2. On the CIW banner, select File => New => Library Under Library, Directory (non-library directories), double-click on Mylibs. 4. Under Library, Name, type mylib_adder_4. 5. Under Technology File, select Don t need a techfile. This is because you ll not be designing any mask layouts (addressed in a separate tutorial). The window should look as shown below. Click on OK. Notice the message in the CIW stating that the new library has been created. It s encouraged to use an underscore _, instead of a dash - when naming libraries and cells. FIGURE 2. New Library window 3.0 Creating a New Cell View 1. On the CIW banner, select File => New => Cell View. 2. Fill in the form as shown below to define the new add_4bit schematic cell view: Tool: Choose Composer-Schematic. This automatically defines the View Name to be schematic (note under Tool the various design entry tools). Cell Name: Type add_4bit. Library Name: Select mylib_adder_4. FIGURE 3. New Cell Name window Creating a New Library (2/32)

6 3. When done, click OK. 4. An empty Composer Window is now displayed as shown below. Note that the CIW performed some background operations, amongst which, it attached a default techfile (cdsdeftechlib) to the library mylib_adder-4, as read from the CIW output area. The Schematic Window Title Bar tells you the Cell Name Icons to supplement pull-down menus The Design Entry Area A duplicate of the CIW prompt Line FIGURE 4. Composer Schematic Entry window areas We have now initiated the design of a schematic cellview for the add_4bit cell. Later, we ll create a symbol cellview for it as well. 4.0 Modifying the Bus Range Order and Pin Sorting Options A bundle of wires is referred to as a Bus. Each bus is given a name and a Bus-Width reference. Each wire in the bundle is given the bus name and a wire number. As an example, we ll refer to an 8-bit wide bus as Input<7:0>. Wire number <7>, named Input<7>, is the most significant bit (MSB) in the bus. This Bus Range Order is descending. By default, Composer sets the Bus Range Order to ascending. This is not desirable during simulation. To change it to descending, follow these steps: 1. From the Composer window, select Design => Options => Editor. 2. Modify the Bus Range Order to Descending, as shown in the figure below. 3. Also, modify the Symbol Generator Pin Sorting to Geometric. This facilitates placing pins on symbols as will be illustrated in section(5.1), step #3. Modifying the Bus Range Order and Pin Sorting Options (3/32)

7 4. Click OK on the form. FIGURE 5. Modifying the Bus Range Order and Pin Sorting Options 5.0 Schematic Capture and Creating a New Symbol The process of editing a design is called schematic capture. In Composer you could use several approaches which all lead to performing one specific action. We could select from the pull-down menus, or click on one of the icons on the left of the design entry form, or use a shortcut letter, referred to as a Bindkey. You ll begin by creating the symbol cellview for add_4bit. The Symbol Editor Window will appear to facilitate this process. On the other hand, note that the schematic window, which will incorporate the schematic cellview, is still open. Keep it open, as you ll descend into it to add components in a later section. The top-level schematic design, called add_4bit_top, will be created in a later stage. You ll then place (add as a component) the add_4bit symbol to it. You ll then add the input and output pins, then descending to create the various components hierarchically. 5.1 Creating a Symbol Cellview from a Pin List To create the shape of the new add_4bit symbol, follow these steps from the Composer Schematic Editor window: 1. Select Design => Create Cellview => From Pin List. 2. The Cellview From Pin List form appears. Fill it as follows: Schematic Capture and Creating a New Symbol (4/32)

8 Input Pins: Ain<3:0> Bin<3:0> Cin Output Pins: Sum<3:0> Cout Cell Name: add_4bit This sequence creates symbols automatically, based on their primary input and output pins. Click OK when done. FIGURE 6. Cellview From Pin List form 3. Click OK on the form. A special Symbol Editor window opens to show you what the symbol would look like. FIGURE 7. Composer-Symbol Editing window Schematic Capture and Creating a New Symbol (5/32)

9 5.2 Modifying the appearance of the Symbol You ll now stretch the rectangle, move the pin locations, and assign a Part Name to it. 1. Click on the rectangle edges and drag to the new location. There are two rectangles: an outer red one, and the inner green one. Start with the outer one, which defines the symbol selection boundary. The inner green one defines the physical appearance of the symbol as it would show when placed in a schematic. 2. Click on the pins and pin names, move the mouse to the new location, then click again to drop. 3. To change the Part Name property, select the [@partname] in the window, then perform either of the following: Centre-Click to display the auxiliary menu, then select Properties..., or Click on the Property icon on the left (scan through the icons until you locate it), or Press the bindkey q on the keyboard, or From the main menu, select Edit => Properties => Objects. 4. Modify the form as shown below by typing ADD-4 in the Label field, and changing the Height field to 0.1, then click OK. FIGURE 8. Edit Object Properties window 5. Finally, the symbol should look as shown below. FIGURE 9. Modified the symbol appearance in the Symbol Editor window Schematic Capture and Creating a New Symbol (6/32)

10 6. To close the symbol Editor Window, select Window => Close. A window will prompt you that the cellviews have been changed. Select Yes to save the modifications and exit. 6.0 Creating the Top-Level Schematic The Top-Level schematic will contain the ADD-4 symbol. We could later place the I/O pins. Now that the add_4bit symbol cellview has been created in your library, it became a Component. The next step is to create a top-level schematic cellview (add_4bit_top), and use Add Component to place the add_4bit symbol in it. Note: To avoid confusion with the cellview naming, note that for every cell, we re creating 2 views- a schematic and a symbol. The order of creating these cellviews in the tutorial may vary. 1. From the CIW, select File => New => Cellview Fill it as follows, then click OK on the form: Library Name: mylib_adder_4 Cell Name: add_4bit_top Tool: Composer-Schematic 3. A new Composer schematic window appears for the new cell. Select Add => Instance. The Add Instance form opens. You may alternatively click on the Instance icon. 4. Click on Browse. The Library Browser appears. Caution: watch out here for cyclic selection of a cell, as explained in the Introduction to Cadence & Unix tutorial. 5. Select:- Library: mylib_adder_4; Cell: add_4bit; View: symbol. The add_4bit symbol appears in the schematic window, and follows the mouse. Note that the Add Instance form now reads add_4bit in the Cell Name field. FIGURE 10. The Library Browser Creating the Top-Level Schematic (7/32)

11 6. Bring the schematic window to the front by clicking on its title bar. The add_4bit symbol follows the mouse as you move it on the window. Position and click to place it at the center of the window. 7. To cancel the Add Instance command, press the Cancel button on the form, or the Esc key when the schematic window is active. 6.1 Adding and Naming the Schematic Pins, Wires, and Buses In composer, a schematic pin is a primary input, output, or input/output terminal for the schematic. Pins, wires, and buses can be added using the menus or icons. Scan slowly through the icons, and note the description that appears as you float on each Adding Pins 1. Scan through the icons, and select the Pin icon. The Add Pin form opens. 2. Type the following in the Pin Names field (note the space between the pin names): A_in<3:0> B_in<3:0> C_in Sum<3:0> C_out FIGURE 11. Add Pins form The input pins are A_in<3:0> B_in<3:0> C_in, and the output pins are Sum<3:0> C_out. You will change the Direction on the form to output later on, just before you place the Sum<3:0> pin. The shape of a schematic input pin follows the mouse as you move it in the window. 3. Now click somewhere close to the symbol to place the A_in<3:0> pin, then a 2nd click for the B_in<3:0>, and a 3rd click for the C_in pin. Stop before you do the 4th click. Note how the Pin Names in Add Pin form begin to clear as you place each pin. 4. On the Add Pin Form, change the direction of the pin from input to output as shown. FIGURE 12. Add Pin form, after changing Direction from input to output Creating the Top-Level Schematic (8/32)

12 5. Click in the schematic window to place the 2 remaining output pins. Follow by clicking Cancel on the Add Pin form to close it, as all the Pin Names have cleared out by now. 6. To move a pin, simply click and drag it to the new location Adding Wires and Buses 1. Click on the Wire(narrow) icon, on the left of the Composer s schematic window, the Add Wire form appears. 2. Click on the schematic window banner to select it. 3. To route the wires, you could follow either of 2 methods: Click once to place each wire segment and twice for the final wire end placement, or Snap to the diamond. This is a neater method when placing wires. As you move the mouse on the schematic window, the pin closest to the end of the wire becomes highlighted with a diamond symbol. You can snap connect the end of the wire to the highlighted pin by clicking the bindkey s (for snap). The wire then jumps to the highlighted pin, closing the gap with straight segments joined at right angles. Snapping automatically routes the wire around other symbols. Ensure that you selected the schematic window before performing the wire snapping. 4. Complete the C_in and C_out wires using snapping. You can click on undo up to 10 times if you make a mistake. Recall that this was set up earlier in the CIW. 5. Click on the Wire(wide) icon. Now, use the s bindkey as before and connect the buses for A_in<3:0>, B_in<3:0>, and Sum<3:0>. You can move any pin, or component by clicking and dragging it to the new location. 6. Now, click on the Check and Save icon to save your work. You should get the following message on the CIW: Schematic check completed with no errors. "mylib_adder_4 add_4bit_top schematic" saved Updating Defaults Now is a good time to update the.cdsenv defaults. It is a good working practice to update the.cdsenv whenever you have a new tool open, and have made modifications in it s environment variables. From the CIW, select Options => Save Defaults... Click on OK on the form Naming the Wires and Buses Note: This procedure is redundant, as net names are implicitly derived from the pins they re connected to. We ll mention the following steps for the sake of familiarization. 1. Click once on the bus connected to the A_in<3:0> Pin. 2. Click on the icon called Wire Name. A form opens. Creating the Top-Level Schematic (9/32)

13 3. In the Names filed, type A_in<3:0> and press Enter. The wire name follows the pointer as you move it on the schematic window. FIGURE 13. The Add Wire Name window 4. Position the name above the bus with the pointer on the horizontal center-line of the bus, and click to place it. 5. Press the Esc key to cancel the Add Wire Name Command. 6. Repeat for the other wires and buses accordingly, then click on Check and Save. Finally, the schematic window should look as shown below. FIGURE 14. The Add_4bit_Top schematic, with pins, connections, and the add_4bit symbol Creating the Top-Level Schematic (10/32)

14 6.2 Attaching the Border Borders are added to the design the same way as we add instances, i.e. from a library. Your working directory now contains a text file called cds.lib which you copied earlier. This file lists all the paths to the libraries that you can use. By default, if you had not copied it, Cadence would have automatically created a standard one and placed it in your working directory. The new design library mylib_adder_4 that you created should be listed now in the cds.lib file. The cds.lib file should list a line that shows the path to the US_8ths borders library, otherwise, you have to manually include this path. Refer to section (6.0) in the tutorial Introduction to Cadence & Unix on how to modify the cds.lib setup file. 1. Click on the Instance icon, and select the US_8ths library, and a suitable border, i.e. select the Asize Cell Name. A border follows the mouse. On the Composer window, you may click on the Zoom-out-by-2 icon to easily display the border boundaries. 2. Move the border to the center of the window, and click once to place it. You may then press the Esc key, or click Cancel on the form. 3. You may now wish to select the entire circuit, and drag it to a more central position. 4. To edit the title of the sheet, from the pull down menus in Composer, select Sheet => Edit Title. A form appears. Fill it in as shown below, then click OK, and note the changes on the schematic design s title block. Company: RMC, VLSI Lab dwg_no: 1 rev: 1 tilte: Adder - 4 Bit 5. On the schematic window, press the bindkey f (fit) to display the full schematic. 6. To select the whole design, go to the farthest top left corner of the schematic, left-click once, then, without releasing the mouse, drag to the other corner of the circuit. You can then click once and drag the design to another more central location, then click last to place it. Make sure you then click outside the circuit area to unselect. 7. To add text to make the schematic more illustrative, go to Add => Note => Note Text Type in the Note Text Box: Top Level 4-Bit Ripple Adder 9. Change the Height to (0.15) 10.A Text Box follows the mouse. Place it under the schematic, then press the Esc key. 11. Click on the Check and Save icon. 12.You may now close all the open schematic windows. Creating the Top-Level Schematic (11/32)

15 13.The final top-level design should be as shown below. FIGURE 15. The final Add_4bit Top Design 14.You will, in a later section, descend into the design and create the sub-level hierarchies. 7.0 Saving the Simulation Session 7.1 Saving the System Environment to a file Referring to the Introduction to Cadence & Unix tutorial, we ll now save the state of our design. The software will also saves the schematic and simulation windows, since they re both active. Select Options => Save Defaults. then click OK to save the file to your root directory. 7.2 Saving the System State to a file To save a simulation session to be able to reload it later from a new CIW run: 1. Go to the CIW and select Options => Save Session. 2. Click OK on the default name cdssession.save. This saves the current session in your working directory. This is a natural breakpoint. You may exit the CIW now, and restart later. Saving the Simulation Session (12/32)

16 8.0 Descending into the design and Creating the Sub-Modules In this section, you ll automatically create the add_4bit schematic cellview, which is composed of 4 full_adder cells. We ll use the Create Cellview command. The new schematic contain the pins defined for the add-4bit symbol. The sequence is as follows: Descending into the design Creating the symbols Placing the symbols Connecting and naming the nets Creating the cells for the sub-modules/cells 8.1 Descending into the design 1. Start the CIW, then select File => Open. 2. Select the Add_4bit_Top Cell Name in mylib_adder_4 Library for editing. Click OK. 3. Move the mouse on the add_4bit symbol, and centre-click to open the auxiliary menu. 4. Select Descend Edit. If you had saved the schematic cellview earlier, you d have the option of opening either the schematic or the symbol cellviews, else, you ll default to the symbol cellview. 5. In the latter case, to quickly create the schematic cellview, from the symbol Editing window, go to Design => Create Cellview => From Cellview Make sure the From View Name is symbol, and the To View Name is schematic. Click OK. A create Schematic form appears. Click on OK. 7. The add_4bit schematic cellview appears. It contains the schematic input and output pins created by the Create Cellview command earlier. You are now ready to start creating the schematics for the full-adder sub-modules. The procedure will involve creating a Full Adder s symbol, placing 4 of them on the schematic sheet, then routing the wires and buses. Afterwards, we ll descend into the Full Adder s symbol, and create it s schematic, which will be composed of 2 Half Adder symbols and a logic gate from the hcells library. Do not confuse between the hcells library and the _hcells library. The latter is a shadow library utilized when implementing a design directly from VerilogHDL into the Cadence environment. These libraries were created by Canadian Microelectronics Corporation (CMC) to be used for digital designs using the cmosis5 technology. We note here that if we were using the cmosp35 technology at the beginning when we invoked Cadence, the library to use for our primitives (basic gates) would be wcells. We ll then continue by descending into one of the Half Adder symbols to create their schematics, which is composed of primitives from the hcells source library. Descending into the design and Creating the Sub-Modules (13/32)

17 8.2 Creating the Full-Adder Symbol We ll create the Full Adder s symbol (add_full) just the same way as we did before while creating the add_4bit symbol. 1. Select Design => Create Cellview => From Pin List. 2. Fill the form that appears as follows, then click OK: Input Pins: Ai Bi Ci Output Pins: So Co Cell Name: add_full FIGURE 16. Full Adder s Cellview From Pin List form 3. The Symbol Generation Options form opens. There s no need to modify it. Click OK. 4. The Composer-Symbol Editing window appears. Change the geometry of the rectangles, as explained before by pulling the corners and dropping them to the new location. 5. You may alternatively change the display green triangle to a circle from the Add => Shape => Circle. 6. Modify the Part Name to read Full-Adder. This is left as an exercise. Read the Prompt line at the bottom of the Composer for instructions while drawing. 7. If you have difficulty in placing the shapes, reduce the snap spacing by going to: Design => Options => Display, and reducing the Snap Spacing to 0.01, as an example. This reduces the objects relocation pitch. 8. To ascend back to the add4bit_symbol s schematic, select Window => Close. 9. Choose Yes to save the add_full s symbol. Descending into the design and Creating the Sub-Modules (14/32)

18 8.3 Placing the Symbols You ll now place 4 of the add_full symbols in the add_4bit schematic. 1. Click on the Instance Icon. The Add Instance form opens. Browse, and select add_full symbol in the mylib_adder_4 library. 2. In the Add Component form, under Array, type 4 in the Rows field. This puts 4 of the symbols automatically. 3. Note the Prompt Line in the schematic window is displaying the message: Point at location for first instance Click in the Design Entry Area to place the first component at the bottom, as that will be assigned Instance #0. 4. As you then move the mouse, the other components appear. Click to place them above the first symbol. 5. Press the Esc key to stop placing more symbols. 8.4 Connecting and Naming the Nets 1. Spread out the input and output pins as necessary, then place the wires and the input and output buses as explained earlier. 2. Click on the Check and Save icon. You should get 12 errors. This is because we haven t named the nets yet. Accept the message that pops up to continue with saving anyway. Note the little 12 squares that show to identify the error markers. 3. We continue by naming the buses as follows. 4. Click on the Wire Name icon. The form appears. 5. In the Names field, type <3:0> 6. Click to set the Bus Expansion to ON. FIGURE 17. Add Wire Name form for the multiple wires and buses The Bus Expansion button tells the system to extract individual bit names from the array names. The first name will be <3>, the second will be <2>, and so on... Descending into the design and Creating the Sub-Modules (15/32)

19 Setting the Placement button to multiple tells the system that you want to place an array of names rather than just one name at a time. 7. Position the mouse on the first net to be named. The <3> name follows the pointer. Place it and continue to the next wire. 8. Now, select the Check and Save icon. The CIW should show a following messages: Schematic check completed with no errors. "mylib_adder-4 add_4bit schematic" saved. You may ignore warning messages. If one is displayed, check to see if you have dangling extensions at the ends of the buses. The final add_4bit schematic should look as shown below. FIGURE 18. Complete add_4bit schematic with bus nets named Descending into the design and Creating the Sub-Modules (16/32)

20 8.5 Creating the Full-Adder and Half-Adder Cells At this time, you re done with the add_4bit schematic. You may now descend to edit the Full Adder s schematic (add_full). 1. In the add_4bit schematic, select Design => Create Cellview => From Instance. 2. The prompt line at the bottom of the schematic window asks you to point at instance to generate view 3. Click on any of the add_full symbols, and select View Name as Schematic. Click OK. 4. A Create Schematic window opens. Change to size A, and type cmosis5 as shown below. Click OK. 5. The schematic editing window appears, with the full_adder s input and output pins already placed. 6. The full_adder is composed of 2 half_adders and a 2-input OR gate. 7. We ll quickly create the symbols for the half adders. Select Design => Create Cellview => From Pin List. Fill in the fields as follows, then click OK: Input Pins: A B Output Pins: S C Cell Name: add_half 8. The Composer-Symbol Editing window appears. Change the geometry of the rectangles, as explained before by pulling the corners and dropping them to the new location. Modify the Part Name to read Half-Adder, then Click OK when done. 9. To ascend back to the add_4bit symbol schematic, select Window => Close, and choose Yes to save the add_half symbol. FIGURE 19. The Half-Adder Symbol 10.You should now be in the Full-Adder schematic window (add_full). 11.Click on the Instance icon. Browse to select the add_half symbol cellview, and place 2 of them in the window. 12.Add an hor2 gate from the hcells library. As a substitute, you may use components from the sample library. Descending into the design and Creating the Sub-Modules (17/32)

21 13.Wire the Full-Adder schematic as shown below. For further description on the hcells library components on the CIW, select CMOSIS5 => CMOSIS5 documentation => hcells and IO cells Descriptions. FIGURE 20. The Full-Adder Schematic 14.Click on Check and Save. You should get no errors. You ll now create the Half-Adder s schematic as you did before for the Full-Adder s. 1. In the Full-Adder s schematic, select Design => Create Cellview => From Instance. 2. The prompt line at the bottom of the schematic window asks you to point at instance to generate view 3. Click on any of the add_half symbols, and select View Name as Schematic. Click OK. 4. A Create Schematic window opens. Change to size A, and type cmosis5 as before. Click OK. 5. The schematic editing window appears, with the add_half s input and output pins. 6. The Half-Adder is composed of 2-input XOR and And gates. 7. Add an had2 gate and an hxor2 gate from the hcells library. 8. Wire the Full-Adder schematic as shown below. FIGURE 21. The Half-Adder schematic Descending into the design and Creating the Sub-Modules (18/32)

22 9.0 Check & Save, Print, and Exit 1. When done with the design of the Full-Adder, click on the Check and Save icon. 2. Make sure nothing is selected by left-clicking on an empty area on the schematic, and then pressing the ESC key on your keyboard. This procedure ensures that there s no active command waiting to be invoked. 3. Center-click using the mouse. An auxiliary menu appears. Select Return. This returns you to the higher hierarchical level. Click on the Check and Save icon as you proceed to the top level of your design for confirmation. 4. Any errors or warnings that exist within the design will be reported in the Cadence s CIW. All errors should be corrected, and then the design checked and saved again. When no errors exist, CIW displays the fact. Note: The causes of all warnings should be determined and carefully understood by you before you choose to accept them in your design. 5. To print from the Composer window, Select Design => Plot => Submit. 6. Click on Plot Options... in the lower right corner of the window that appears. 7. Under Plotter Name, select the name of the printer you are using. Read the form carefully. 8. When done plotting, you may wish to close the composer window. From the menu bar, select Window => Close. 9. You may then quit the Cadence environment. From the CIW, select File =>Exit. 10.A form appears. Click on Yes to quit. 11.Another form appears. Read it, then click Cancel. You ve now completed the schematic Entry tutorial. Next, we ll talk about how to invoke Verilog-XL to simulate the digital design. Check & Save, Print, and Exit (19/32)

23 RMC - VLSI Lab: Cadence Tutorial Digital Simulation (Using Verilog-XL Integration) 10.0 Introduction to Verilog-XL Integration In this tutorial, we ll introduce simulating a digital design, using Verilog-XL Integration from the Composer schematic entry tool. We ll introduce a stimulus file written in Verilog- HDL. We ll then display the various waveforms using SimWave from within the Verilog- XL Integration tool. At this time, you may wish to familiarize yourself with Verilog-HDL, however, the simple example presented will be fully explained. The next step after creating a design is to simulate it to simulate it to verify it meets the input/output requirements. Simulation involves applying a set of test vectors to the input and observing the output on a graphical user interface (GUI). We recall from Section (3.0) in the Introduction to Cadence & Unix tutorial the reference to Verilog-HDL as a means for design entry. In fact, we may describe a design in a Hardware Description Language then simulate it using the Cadence CIW environment. The CIW allows us to either enter our design in a schematic form or in an HDL textural form, or a combination of both. We may then import a stimulus file, written in the Verilog- HDL code, into verilog-xl Integration in order to apply the test vectors and stimuli into our design. We may then graphically display the various waveforms in SimWaves. Schematic Entry using Cadence/Composer (And/Or) HDL code of design written in VHDL or Verilog-HDL Cadence/Verilog-XL Integration Verilog-HDL Stimulus code SimWaves Graphical Interface FIGURE 22. Basic design process in the Cadence environment Introduction to Verilog-XL Integration (20/32)

24 Note: Recognize the difference between Verilog-HDL (a hardware description language), and Verilog-XL Integration (a program in the Cadence environment that could read Verilog-HDL code and implement it directly into your design) Starting Verilog-XL Integration Ensure that you first go through the steps explained in Section (1.0 and 2.0) to start the CIW and display your schematic design in Composer. 1. From the CIW, select File => Open, and select the add_4bit_top schematic in the mylib_adder_4 library. 1. From the Composer pull-down menus, select: Tools => Simulation => Verilog-XL. 2. The Setup Environment window appears after a short period of time. All the necessary information should be already entered in the form. FIGURE 23. Verilog-XL Integration Setup Environment window 3. The Run Directory is where the information about the simulation will be saved. Cadence uses the convention of the schematic name followed by the extension run1 to signify the first simulation for a design. Verify that the Run Directory is add_4bit_top.run1 and click OK. 4. After a period of time, the Verilog-XL Integration window will appear as shown below. FIGURE 24. Verilog-XL Integration Control window Starting Verilog-XL Integration (21/32)

25 5. It is a good common practice when starting a simulation to go first to the Setup s pulldown menu, and go through each of its items in order. This helps in familiarization with the various settings. 6. By default, Verilog-XL only records the values of the inputs and outputs for a given schematic. You may, however, wish to display some of the internal signals in your circuit. To make sure that you display (record) all the desired signals that you want, select Setup=> Record Signals... The following window appears. Ensure Top Level Primary I/O is chosen. Click OK. FIGURE 25. Record Signals Options window 12.0 Setting-up Verilog-XL Integration Due to the way the Cadence environment is organized we need to sometimes initially specify the location of some files, i.e. models, setup files, or libraries to the tools. In the case of the Verilog-XL Integration Cadence tool, we need to specify the location of the models set library. Other tools, i.e. Analog Artist (the Cadence Analog simulation tool) will require us to perform similar steps for its model set library. The Verilog models for the hcells library of the cmosis5 technology we re using resides in the path: /CMC/kits/cmosis5/cadence/cmosis5.2.3/models/verilog On the other hand, models for the Analog Artist library are specified by replacing the last directory leaf (verilog) with either spectre or hspice, depending on the simulation engine we decide to use. 1. For a Verilog-XL simulation, go to the above shown path using the workstation s File Manager program. You ll find 2 sub-directories: nwb and udp. 2. From the Verilog-XL Control window, select Setup => Simulation Click on More at the bottom-right corner of the window. 4. In the Library Directories field, type in the following 2 paths if they do not exist (place a single space between the two paths): Setting-up Verilog-XL Integration (22/32)

26 /CMC/kits/cmosis5/cadence/cmosis5.2.3/models/verilog/nwb /CMC/kits/cmosis5/cadence/cmosis5.2.3/models/verilog/udp These paths Tip: Browse to each subdirectory, then copy the path showing on the File Manager s path field into the Libraries Directory field in order to eliminate typos. 5. Click OK to invoke the form. The complete form should look as shown in the following figure. FIGURE 26. Complete Simulation Options form Setting-up Verilog-XL Integration (23/32)

27 13.0 The Verilog-HDL Stimulus File We ve now completed the various setup steps necessary to perform a basic Verilog simulation. Next, we need to introduce the stimulus file into the Cadence/Verilog-XL environment (refer to figure 1 earlier). Verilog-XL creates an initial default Verilog stimulus template file. We may follow the following steps: 1. From the Verilog-XL Control window, select Stimulus => Verilog. 2. When the no test fixture warning appears, click on Yes to create the stimulus template file. 3. When the Stimulus options window appears, the Mode: Select button will be pressed, as shown below. FIGURE 27. Initial Stimulus Options window 4. The list on the previous window shows a file called testfixture.verilog. This is a default testfixture file that Verilog-XL generates automatically. It usually contains initialization values for all the input signals, i.e. 0 s, by default. Therefore, a common practice is to copy that initialization stimulus file to a new file (we d rather not overwrite on it), and then modify and add to it the various test vectors we wish to introduce into our design. We therefore select the Mode: Copy button. The window changes. 5. Within the Copy From box, under File Name, either enter testfixture.verilog, or browse until you find it, then single-click to select it. The Verilog-HDL Stimulus File (24/32)

28 6. Under the Copy To box, let s replace testfixture.new with add4bit.test1. We ll use the extension.test# to signify a testfixture (stimulus) file. 7. Click on the Make Current Test Fixture button at the bottom of the window. Note that the field Current Test Fixture is still empty. At this point, click Apply. Note that the Current Test Fixture field changes to read add4bit.test1. Click Cancel now, since we have already performed the copying process. FIGURE 28. Stimulus Option window- completed 8. Now is the turn to modify the testfixture file, and introduce some stimuli into it. The standard way is to have selected the Mode: Edit earlier, after clicking Apply in the previous step. It is, however, preferable to edit the stimulus file by opening it from the workstation s standard file manager. Edit the file by double-clicking on the file manager s icon. Note that the stimulus file now resides in the following directory: $HOME/cadence/Add_4bit_Top.run1/add4bit.test1 FIGURE 29. The default stimulus file generated by Verilog-XL The Verilog-HDL Stimulus File (25/32)

29 9. The stimulus commands are written in the Verilog-HDL, a language much like C. As you become more familiar with the syntax, you ll be able to perform more complex functions. For the time being, the presented stimulus file is sufficient. Comments are preceded by double slashes //. Edit the stimulus file to show the Verilog code as follows: // comments begin with // // 4-bit-adder stimulus file. Inputs: A_in, B_in, C_in. initial begin A_in = 0; B_in = 0; C_in = 0; // Start at time zero (ns) // begin<=>end groups a set of steps, as in Pascal language // At the beginning, all three signals should be low. // There s no delay between each of them reading 0 initially. // We ve modified the look of the default testfixture here. #10 A_in = 2; // A_in becomes 2 (in Decimals) = 0010 (in Binary). #10 B_in = 4; // When no base is indicated, the values are read in #10 C_in = 1; // Base 10. Another representation for A_in = 2 #10 A_in = 3; // in Binary would be A_in = 4 b0010, #10 B_in = 7; // where the first number (4) represents the width of the #10 C_in = 1; // bus, and the ( b) would interpret the base of the values #10 A_in = 13; // to follow(binary). (A_in = 4 h2). Other input values follow. #10 B_in = 4; // #10 is a delay of 10 nanosec between each. #10 $finish; // After 10 nsec, stop simulation. end // end the Testfixture stimulus file // When you complete editing the file, save it and return to the Verilog-XL Integration window Running the Simulation You are now ready to run the simulation. To begin the compiling and execution process, simply click on the icon Start Interactive on the left. This is the same as selecting Simulation => Start Interactive. FIGURE 30. Start Interactive button Keep an eye on the window and the progress to look for errors and warnings. When the C1> prompt appears at the bottom of the Verilog XL window, you are ready to continue. Notice that the Verilog-XL window icons are all accessible now, as shown next. Running the Simulation (26/32)

30 FIGURE 31. Verilog-XL Integration Control in the Continue mode Now click on the Continue icon, located below and to the right of the Start Interactive icon. Finally, the Verilog-XL window would update after the simulation, and only the View- Waveforms icon would be accessible. Click on the View-Waveforms icon to invoke SimWave, the graphical interface program to Cadence/Verilog-XL Integration. This is a breakpoint. You may now save your defaults and session from the CIW s Options menu. We ll talk next about SimWave. Running the Simulation (27/32)

31 RMC - VLSI Lab: Cadence Tutorial Digital Simulation Waveform Display (Using SimWave) 15.0 Introduction to SimWave SimWave is the Graphical Display Program for digital signals. It provides some functions that allow you to layout the timing diagram under various options, and then print the final product to a postscript file. Unfortunately, this version of SimWave does not allow to directly print the waveforms to a printer. Once you invoke SimWave from the Verilog-XL Control window, take your time and browse through the various pull-down menu options Displaying the Waveforms Before we jump in and display the signals, let s adjust some of the display options. Afterwards, follow these steps for some waveform display options: 1. Select Options => Grid => Setup Time Grid. Unselect Automatic, then Under Step, type 20.0ns. Click OK. 2. Select Options => Grid => Show Time Grid. 3. Select Options => Display Options => Values to the Left. 4. Select Options => Display Options => Show Messages. 5. Select Options => Default Radix => Decimal. 6. Select Edit => Add Signals... A SimWave Browser window appears as shown below. FIGURE 32. SimWave Browser window Introduction to SimWave (28/32)

32 7. Double-click on the word test under Instances. The word top is displayed. Doubleclick on top. Your 5 input and output ports are displayed under Signals. 8. Highlight the 5 signals by left-clicking, dragging on A_in, then dragging the mouse downwards till all 5 signals are highlighted, then release the mouse left button. 9. Click on the Display signals Icon (next to the Close Icon), then the Close Icon respectively on the window. FIGURE 33. The Close and Display signals Icons in the SimWave Browser window 10.In Simwave, select View => Zoom Fit. Simwave should display as below. FIGURE 34. The SimWave Display, with waveforms 17.0 More about SimWave Finally, we ll mention a few quick tips to get you to interpret your signals more clearly The Time Cursors Notice the three values in the upper right of the window (C1, C2, delta) together can tell the duration of a pulse for instance. Left-click to set the C1, middle-click to set C2, and delta is the positive difference between the two times. More about SimWave (29/32)

33 17.2 Deleting or Relocating Signals To delete a signal (or relocate it), simply click on the signal name on the left window, and either select copy or cut from either the icons or the pull-down menu (Edit) Saving the Setup file Once you ve made modifications to the way waveforms are displayed, e.g. time scale, signals display order, etc..., you may save these set of options to use for a later simulation session. Select File => Setup => Save, and fill it as shown below., then click OK. FIGURE 35. Save Setup window This comes handy if you encountered simulation problems and had to make some modifications, but wish to save the setup formats Re-Simulating If you need to modify for instance the stimulus file, you ll have to clear the waveform display window in the SimWave program first, then apply your modifications. However, SimWave will stay active. Select: File => Database => Close, and select OK. Once you ve made the modifications to your stimulus file, you ll need to start the simulation again by clicking on the Start Interactive icon in the Verilog-XL Integration window in the same manner as in the initial simulation run. You ll be asked if you wish to re-netlist. Only choose Yes if you have made changes to your schematic. When you see the C1> prompt as before, click on the Continue Icon. Once the simulation has been completed, you can restore the setup format in SimWaves. More about SimWave (30/32)

34 Select File => Setup => Restore. FIGURE 36. SimWave Restore Setup window The form should already be filled out. Select OK. The new waveforms should appear in the SimWave window. You could have, as an example, un-selected the Waveform Window button to default the window to all other settings but the previous waveform settings. This gives you the option of selecting a different set of signals Printing Waveforms This newer version of SimWave will print directly to a printer. You may instead print to a postscript file that can be printed later on an EOS printer using the UNIX lpr command. To print as a ps file, select: File => Print => Single Page A window appears, as shown below. FIGURE 37. The Print window Fill out the window appropriately to print. More about SimWave (31/32)

35 18.0 Removing the Simulation Files and Exiting Disk quota may not be an issue at first, but there may be times when you are running low and need to purge some information that you re no longer using. Verilog allows you to do this is a clean way. From the Verilog-XL window, select File => Clean Current Run. This process will remove a number of large files that are regenerated on every run and are, therefore, no longer needed once you view and print your waveforms. This process will not, however, delete your testfixture files nor SimWave setup file. It then becomes a simple task of re-simulation to generate a new set of waveforms. At this point, you may wish to save your session and defaults. From the Verilog-XL window, select File => Quit, and confirm to quit. Close any schematic or other windows appropriately, and exit your CIW session. Congratulations! You ve completed the basic digital simulation flow. Removing the Simulation Files and Exiting (32/32)