Wisam Kadry IBM Research, Haifa 7 June 2012 Workshop on Post-silicon Debug: Technologies, Methodologies, and Best Practices
DAC 2012, Post-silicon Debug Workshop Thanks to Mr. Amir Nahir IBM Research Haifa, Israel Received his BSc in computer science from Technion, IIT in 2005, and is currently pursuing his PhD there. He has been a research staff member at the IBM Research Labs in Haifa since 2006, and has spent most of his time leading the development of Threadmill a post-silicon functional validation exerciser. Since the beginning of 2011, Amir manages the Post-Silicon Validation and Design Automation Group
Agenda Session I (09:00-10:30) Wisam Kadry - IBM Haifa Research Lab., Haifa, Israel Kevin Reick - IBM Corp., Austin, TX Subhasish Mitra - Stanford Univ., Stanford, CA David Erikson - Advanced Micro Devices, Fort Collins, CO Bradley Quinton - Tektronix, Inc., Vancouver, BC, Canada Break (10:30-11:00) Session II (11:00-12:30) Alan Hu - Univ. of British Columbia, Vancouver, BC, Canada Keshavan Tiruvallur - Intel Corp., Portland, OR Nagib Hakim - Intel Corp., Santa Clara, CA Valeria Bertacco - Univ. of Michigan, Ann Arbor, MI Sharad Kumar - Freescale Semiconductor, Inc., Noida, India Lunch (12:30-13:30) Panel (13:30-15:00) Moderator: Harry Foster - Mentor Graphics Corp., Plano, TX
More complex chips
Observe
Control
Localize
Recreate
Find root cause and fix
Session I (09:00-10:30) Kevin Reick - IBM Corp., Austin, TX Subhasish Mitra - Stanford Univ., Stanford, CA David Erikson - Advanced Micro Devices, Fort Collins, CO Bradley Quinton - Tektronix, Inc., Vancouver, BC, Canada
Mr. Kevin Reick IBM Corp., Austin, TX Joined IBM in 1982. Has a BS in Electrical Engineering from Rutgers University and MS in Computer Eng. from Syracuse University. Mr. Reick has held a variety of technical leadership positions that have continually positioned IBM s leadership in the server market. Mr. Reick is a recognized technical expert in IBM (with more than 30 patents) in the areas of Reliability, Availability, Serviceability (RAS) and Chip/System bringup
Prof. Subhasish Mitra Electrical Engineering and Computer Science Stanford Univ., Stanford, CA Directs the Robust Systems Group in the Depts. of Electrical Engineering. and Computer Science.His research interests include robust system design, VLSI design, CAD, validation and test, and emerging nanotechnologies. Prior to joining Stanford, Prof. Mitra was a principal engineer at Intel Corporation. He received Ph.D. in Electrical Engineering from Stanford University.
Mr. David S. Erikson Advanced Micro Devices, Fort Collins, CO Sr. MTS engineer in AMD's Silicon Validation Architecture team. David has fifteen years of experience in validation, debug, and system architecture at companies including AMD, Intel, and National. He also has experience in a startup company and in medical device development. David has held roles ranging from architect, debug and validation lead, validation manager, and system design manager. David is a graduate of Dartmouth College.
Dr. Brad Quinton Tektronix, Inc., Vancouver, BC, Canada Chief Architect for the Embedded Instrumentation Group at Tektronix. Over 15 years of experience in the semiconductor industry. His PhD from the University of British Columbia explored on-chip debug architectures and it is behind the technology developed by the Tektronix Embedded Instrumentation Group
Workshop on Post-silicon Debug: Technologies, Methodologies, and Best Practices
Session II (11:00-12:30) Alan Hu - Univ. of British Columbia, Vancouver, BC, Canada Keshavan Tiruvallur - Intel Corp., Portland, OR Nagib Hakim - Intel Corp., Santa Clara, CA Valeria Bertacco - Univ. of Michigan, Ann Arbor, MI Sharad Kumar - Freescale Semiconductor, Inc., Noida, India
Prof. Alan J. Hu Dept. of Computer Science Univ. of British Columbia, Vancouver, BC, Canada Received his BS and PhD degrees from Stanford University. For over 20 years his main research focus has been, automated, practical techniques for formal verification. He has served on the program committees and chaired major CAD and formal verification conferences. A member of the Technical Advisory Board of Jasper Design Automation.
DAC 2012, Post-silicon Debug Workshop Mr. Keshavan Tiruvallur Intel Corp., Portland, OR Keshavan is an Intel Fellow in the Intel Architecture Group, Platform Validation Engineering for Intel Corp. He is responsible for the technical oversight on the post-silicon validation debug process and methods. He joined Intel in 1983 immediately after graduating from college. He is currently leading enhanced platform debug capabilities within Intel as well for Intel's customers in this new era of increased integration.
Dr. Nagib Hakim Intel Corp., Santa Clara, CA Received his MS and Ph.D. degrees in Electrical Eng. from Columbia University. Joined Intel in 1992. Worked in CAD tool development for the analysis of manufacturing variations, circuit performance and reliability, and platform power / performance optimization. He is currently a Principal Engineer in the Platform Validation Engineering dep. He has more than 40 publications, and served on the Technical program Committee of major EDA conferences
Prof. Valeria Bertacco Electrical Engineering and Computer Science Univ. of Michigan, Ann Arbor, MI Received her M.S. and Ph.D. from Stanford University. Her research interests are in the area of design correctness, with emphasis on full design validation, digital system reliability and hardware security assurance. She is currently spending her sabbatical at the Addis Ababa Institute of Technology in Ethiopia
Mr. Sharad Kumar Freescale Semiconductor, Inc., Noida, India Manages the SoC post silicon validation and emulation teams for Freescale in Noida, India. Been with Freescale for close to 12 years. He has a Master in Electrical Engineering from Michigan State University. He is also responsible for defining the validation tools and methodology for Freescale's PowerPC based embedded communication SoCs.
Workshop on Post-silicon Debug: Technologies, Methodologies, and Best Practices
Panel (13:30-15:00) Moderator: Harry Foster - Mentor Graphics Corp., Plano, TX
Mr. Harry Foster Mentor Graphics Corp., Plano, TX Harry Foster is Mentor Graphics' Chief Scientist for verification. He is co-author of seven books on functional verification, and holds multiple patents in this area. Harry serves as chair of the IEEE 1850 Property Specification Language (PSL) working group, and was the original creator of the Accellera Open Verification Library (OVL) assertion library standard. Harry has over than twenty years of industry experience in design and verification. He is the recipient of the Accellera Technical Excellence award for his contribution to developing industry standards.
Workshop on Post-silicon Debug: Technologies, Methodologies, and Best Practices