Model-Based Development Tools for Embedded Multi-Core Systems
Multicore and multiprocessor software projects are 4.5x more expensive, have 25% longer schedules, and require almost 3x as many software engineers. 1
Meet the Multi-Core Challenge The demand for more sophisticated comfort features, and increasing safety requirements are factors that express the need for additional processing power within embedded systems. Due to physical restrictions, which limit further increases of clock rates, single-core processors are no longer adequate to satisfy the requirements of next generation embedded systems. This makes changes towards a new processing technology with multi-core inevitable. Multi- and many-core processors will be the basis technology for future embedded systems as all leading chip manufacturers Intel, IBM, ARM, Nvidia, Freescale, MIPS, TI are focusing their strategy on multi-core architectures2. Challenges due to the new Multi-Core technology Surveys have shown, that using this new technology, multi-core and multi-processor software projects are 4,5 times more expensive, have 25% longer schedules, and require almost 3 times as many software engineers. 4.5x more expensive 25% longer schedules 3x as many engineers Master the Multi-Core Challenges with Timing Architects Save Money e.g. by making precise predictions of resource needs Save Time e.g. by preventing late and time consuming changes Save Resources e.g. by selecting overhead optimized system design Timing-Architects Tool Suite enables engineers to master the multi-core challenges. By using TA tools for a multi-core project, costs, time, and the need of resources will be reduced and even drops below the level of expenses for a single-core project. 1 VDC Research, "Next Generation Embedded Hardware Architectures: Driving Onset of Project Delays, Costs Overruns, and Software Development Challenges" September 2010 2 Arbeitskreis Multi-Core, Andreas Herkersdorf, TU Munich, Relevanz eines Multi-Core-Ökosystems für künftige Embedded Systems December 2011 3
The Timing The Timing Architects Architects Tool Suite Tool Suite Integrated Solution Integrated for Solution designing, for developing designing, developing and verifying and verifying embedded embedded multi- and many-core multi- and many-core systems systems Closed-Loop Closed-Loop Solution for Solution iterative for system iterative design, system simulation, design, simulatio automated automated optimization optimization and target verification and target verification 4 4
Architects Timing Tool Architects Suite Benefits Tool Suite Benefits ol Suite is The the framework TA Tool Suite of integrated is the framework development of integrated tools for development real-time multi- tools and for real-time many-core multi- systems. and many-core systems. all these Regarding development all these steps development the TA solution steps was the especially TA solution designed was especially for the embedded designed multi-core for the embedded era. multi-core era. gner Specification of hierarchical Specification requirements of hierarchical requirements Design of software architecture Design of software architectures Mapping of software functions Mapping to of hardware software functions resourcesto hardware resources Integrating new software Integration modules of in new existing software systems modules in existing systems Designer Page 8 Page 8 lator In-depth evaluation of the systems and components timing behavior Depth evaluation of the systems and components timing behavior Evaluation of hardware resource consumption of application software and Evaluating hardware resource consumption of application software and operating system operating system Performance analysis and evaluation of different hardware platforms and software design Page Performance analysis and evaluation of different hardware platforms and software Interference and effects analysis 12 designs Interference and cause-effect analysis Validating and comparing design decisions early in the development process Validation and comparison of design decisions early in the development process Simulator Page 12 izer Semi-automated design Semi-automated of embedded multi- design and of embedded many-core multi- software and architectures many-core software architectures Automated mapping of Automated software functions mapping to of hardware software functions resourcesto hardware resources Page Trade-off and capability Trade-off analysis and of embedded capability analysis multi- and of embedded many-core multi- software and many-core software 16 architectures as well as architectures hardware platforms as well as hardware platforms Optimizer Page 16 ector Verification of system Verification implementations of system on target implementations hardware on target hardware Comparison of simulation Comparison results and of system system implementations implementations against simulation results and model specification Page Detection of hardware bottlenecks 20 Detection of hardware bottlenecks Reverse/re-engineering of legacy applications Reverse/re-engineering of legacy applications Inspector Page 20 -Architects The Tool Timing-Architects Suite is a worldwide Tool Suite unique is a solution worldwide which unique covers solution the system which design covers phase, the system design phase, and analysis, simulation architecture and analysis, optimization architecture and deployment, optimization as and well deployment, as target verification. as well as target verification. 5 5
TA Tools TA in Tools the Development in the Development Process Proces The integrated solution The for integrated designing, solution developing, for designing, and verifying developing embedded and verifying multi- and embedded many-core multi- systems and many-core systems se seamlessly integrated integrated your development in your development process. process. Designer Designer Simulator Simulator Optimizer Optimizer Inspector Insp Architecture Architecture System Design System Design Module Design Module Design We are supporting We are supporting The TA Tool Suite covers The TA the Tool whole Suite development covers the whole process development of an embedded process real-time of an embedded system. With real-time TA tools system. we support With TA Tools w project managers, architects, support project developers, managers, integration architects, and developers, test engineers integration alike to get and the test most engineers out of the alike new to get multi-core the most out of t technology. multi-core technology. Project Manager Project Manager Software Architect Software Architect Software DeveloperSoftware Developer Integration EngineerIntegration Engineer Test Engineer Test Engineer 6 6
ing Timing Architects Architects Tool Suite Tool Benefits Suite Benefits ol Suite allows The TA you Tool the Suite import allows of AUTOSAR you the import System of AUTOSAR Description System and/or ECU Description Configuration and/or files. ECU In Configuration standardlopment processes, standardized this development allows the automation processes, of this the allows modeling the steps. automation Further of imports the modeling of standardized steps. Further imports of files. In e available standardized new or in-house formats are formats available upon and request. new or in-house formats upon request. our embedded Model real-time your embedded system with real-time the system with Make the well-founded Make forecasts well-founded about the forecasts system about the system graphical model intuitive editor graphical or import model existing editor or import existing utilization and dimensioning utilization of and the dimensioning hardware. of the hardware. from standard systems interfaces from standard (e.g. AUTOSAR, interfaces (e.g. AUTOSAR, TEA) as well AMALHTEA) as from hardware as well target as from traces. hardware target Compare traces. software implementation Compare software alternatives implementation and alternatives and optimize them regarding optimize real-time them and regarding performance real-time and performance e and optimize Simulate different and system optimize design different system design properties. properties. ives at early alternatives stages in the at development early stages in the development. process. Import hardware target Import traces hardware of your target software, traces of your software, automatically re-construct automatically a timing re-construct model from a it, timing model from it, e your single-core Optimize software your single-core architecture software for architecture analyze for the target trace analyze regarding the target real-time trace and regarding real-time and rformance multi- high-performance many-core multi- processor or many-core processor performance properties performance and compare properties the trace and to compare the trace to s. platforms. simulation results. simulation results. Tool Suite The TA is the Tool closed-loop Suite is the solution closed-loop for iterative solution system for iterative design, system design, tion, automated simulation, optimization automated and optimization, target verification and target verification SAR LTHEA L s & ements icore TM sor or Model lications 1 Kq X 1/A + Behavioral Modeling Behavioral Modeling AUTOSAR AMALTHEA ADL s & Requirements TA System Model MultiCore TM Prozessor Processor Model OSEK VDX Applications 1 Kq Functional Code X 1/A OS & RTE Configuration & Code + TA System Model Executable MultiCore TM Prozessor Functional Code OS & RTE Configuration & Code Target Import of software description, Import of software description, requirements and further requirements and further Executable information from standard information from standard or customer individual customer architecture individual architecture description languages description languages For a detailed analysis, For TA a detailed analysis, TA provides precise models provides for precise models for semiconductor processors semiconductor and processors and operating system overheads operating systems MultiCore TM Prozessor Target Export of optimized Export architecture of optimized architecture description and extended description and extended requirements to third-party requirements tools to third-party tools for further processing for further processing CPU 2 E Model CPU 1 CPU 2 OS & RTE Model Debugger/ Profiling Import of target traces Import from of target traces from debugger or instrumentation debugger or instrumentation based profiling based profiling Debugger/ Profiling 7 7
Designer Designer Managing complexity Managing of complexity highly integrated of highly and integrated functional systems, functional enabled systems, by enabled seamless by seamless switching between switching individual between abstraction individual abstraction layers la and implementation and implementation layers for requirements, layers for requiremen design constraints design constraints and system and specification. system specificatio 8
Use the TA Designer Use the for: TA Designer for: Specification of hierarchical Specification requirements of hierarchical requirements Design of software Design architecture of software architectures Mapping of software Mapping functions of software to hardware functions resources to hardware resources Integrating new software Integration modules of new in software existing modules systems in existing systems 9 9
Designer The TA Designer enables to manage the complexity of highly integrated and functional systems. This is possible by a seamless switch between different levels of abstraction in your functional composition design as well as software architecture design. Furthermore, the TA Designer is used for specification of requirements and design constraints as well as integration support tool for internal development and collaborative software development between OEM and Tier 1. Use the TA Designer for: Functional compositing Requirements specification Integration of runnables in tasks Verification of software architecture constraints Exchange of designs in collaborative development Key-features of the TA Designer: Support for the system design Various import/export capabilities of software architecture information, e.g. AUTOSAR or AMALTHEA open-source model, including software components description as well as event-chains and sequencing constraints Automated validation of individual system architecture design constraints Intuitive specification of requirements including timing and resource-consumption requirements Graphical specification of event-chains, e.g. for data-flow evaluation Specification of system architecture constraints, e.g. runnable sequencing constraints Interactive graphical data flow and interaction visualization on all software layers Automated data consistency checking Many views are enhanced by information from simulation, executed in the background, and automated validation checks on the model Interactive UML editing capabilities Means to aggregate software in a functional or logical structure to make complexity manageable Graphical support for merging different software models and automated consolidation of system artefacts as well as automatic integration of collaborative developed software components 10
Requirements Specification Specification of requirements on entity metrics like an upper limit on response time of a task, e.g. deadline, or an upper limit for net execution time of a runnable. Hierarchical Dataflow Analysis Interactive hierarchical dependency analysis of the software architecture on all layers, enhanced by advanced filtering and aggregation functions. Constraints Visualization Overlay functions allow interactive visualization of requirements and constraints, e.g. event-chains or runnable sequencing constraints. UML Modeling Modeling and visualizing the system model with familiar UML diagrams as well as export for documentation purpose and exchange with other stakeholders. Grouping and Structuring of Software Artefacts Functional or logical aggregation of software artefacts, e.g. runnables or signals, in order to make complexity manageable. 11
Simulator Simulator In-depth analysis Depth of analysis system of behavior system regarding behavior regard timing behavior timing and behavior resource and efforts, resource enabled efforts, by enab interactive and interactive interconnected and interconnected data visualization data visuali charts. charts. 12
Use the TA Simulator Use the for: TA Simulator for: Depth evaluation In-depth of the systems evaluation and of components the systems timing and components behavior timing behavior Evaluating hardware Evaluation resource of hardware consumption resource of application consumption software application and operating software system and operating system Performance analysis Performance and evaluation analysis of and different evaluation hardware of different platforms hardware and software platforms design and software designs Interference and Interference effects analysis and cause-effect analysis Validating and comparing Validation design and comparison decisions early of design in the decisions development early process in the development process 13 13
Simulator The TA Simulator allows a highly performant simulation and evaluation on scalable abstraction, and detail layers as well as an user-friendly and interactive representation of results. Developed exclusively for multi- and many-core systems, the TA Simulator enables to evaluate system behavior at all stages of the development process. Starting from the early design of the software, without any costly or even non-available hardware, right to the comparison of implementation alternatives. The TA Simulator allows the use of abstract processors, user-designed processors or semiconductor processors, developed by TA in cooperation with chip suppliers. Use the TA Simulator for: In-depth evaluation of system and components timing behavior as well as resource consumption Evaluating hardware resource consumption of application software and operating system Performance analysis and evaluation of different hardware platforms as well as software designs Interference and cause-effect analysis Validation and comparison of design decisions early in the development process Key-features of the TA Simulator: Model-based schedulability evaluation and comprehensive forecast of the dynamic software behavior of multi- and many-core real-time systems Local and global scheduling, leveraging the full potential of multi-core systems Hardware and software resource consumption and system performance evaluation for multi- and many-core systems Automatic in-depth evaluation of hardware effects, e.g. Cache Hit/Miss, communication overhead or blocking effects Detailed simulation and analysis of abstract or vendor specific processor systems, e.g. Infineon AURIX or Freescale MPC57xxx family Energy-aware system scheduling analysis (including frequency scaling or core turn-off analysis and visualization) Time response evaluations allow a detailed scenario analysis by use of supporting means Metrics and event-chains Requirement violations Time, distribution and estimator analysis regarding Temporal resource consumptions Time responses Metrics and event-chains Requirement violations 14
Task Call-Graph Specification Graphical modeling editor for software model review and interactive modification, e.g. runnable call positions or mode-based branches in task execution path. Schedule Sequence Gantt chart visualization of all traced entities, e.g. tasks, runnables or semaphores, as well as additional status information. This allows analyzing the execution and interaction of software and hardware as well as resource consumption. Performance Evaluation Analyzing resource consumption like CPU load as well as effects from dynamic frequency adapting systems as a function of time, in order to improve energy efficiency of the overall system. Timing and Performance Metrics Evaluation Overview on metric estimators for all tasks, ISRs or runnables, containing metrics like response time or net execution time with different representative estimators like maximum or average. Timing and Performance Metrics Distribution Analyzing the distribution of metrics, e.g. response time, for entity instances on different layers, like tasks, runnables or individual eventchains. The interactive interconnection to other views like the Gantt chart allows an in-depth scenario evaluation. 15
Optimizer Optimizer Semi-automatic Semi-automatic software architecture software architecture design and desi deployment deployment of software of to software hardware, to enabled hardware, by enab comprehensive comprehensive solution comparisons solution comparisons for for trade-off analysis. trade-off analysis. 16 16
Use the TA Optimizer Use for: the TA Optimizer for: Semi-automated design Semi-automated of embedded design multi- of and embedded many-core multi- software and many-core architectures software architectures Automated mapping Automated of software mapping functions of to software hardware functions resources to hardware resources Trade-off and capability Trade-off analysis and of capability embedded analysis multi- of and embedded many-core multi- software and many-core software architectures as well architectures as hardware as platforms well as hardware platforms 17 17
Optimizer The TA Optimizer allows a model-based design space exploration and automated multi-criteria optimization of embedded systems. Individual needs can be specified and multiple configuration settings can be optimized simultaneously. For automatic software deployment on the target platform, TA Optimizer detects automatically sufficient software partitioning and allocation policies. This allows an optimal migration from single- to multi-core systems as well as the improvement of existing multi-core systems. Use the TA Optimizer for: Giving software integrators an objective basis and support at the decision-making process of how to partition and allocate software fragments to individual cores Allow software architects to analyze the design space and conduct comprehensive trade-off analysis Evaluate different software variations and provide policies to project teams for an optimal multi-core solution over different platforms Automatize OS configuration and software deployment Key-features of the TA Optimizer: Automatized optimization of multi-core software architectures regarding specified requirements under consideration of design constraints by improving simultaneously several design decisions Mapping of runnables to tasks Partitioning of tasks Positioning (sequence order) of runnables inside tasks Allocating of tasks to cores Setting of task priorities Setting offset of periodic tasks Guided and visualized trade-off analysis of different software designs Semi-automated parallelization of single-core software architectures Intelligent automatic partitioning (dividing tasks into smaller entities for parallelization and load balancing purposes) Automated design-space exploration of timing and system properties of your embedded real-time multi-core system Automated detection of software partitioning and allocation policies for software fragments Export and update of the OS configuration 18
Constraint Specification Definition of software architecture design constraints, e.g. affinities in the aggregation and positioning of executables or deployment of software to hardware. Optimization Configuration Intuitive configuration of the optimization objectives, allowed system modifications, constraints and requirements as well as optimization search detail level. Optimization Result Comparison Comparison of optimized system solutions with initial software architecture or any other solution by benchmarking an individual set of all possible metrics as well as compliance level of requirements. Trade-Off Analysis Sophisticated visualization of metrics for multicriteria decisions and interactive selection of solutions for individual and efficient ranking and selection of the best solution. Final Solution Selection Overview on metric estimators for all system metrics and its representative estimators, like maximum, average or minimum, like compact visualization of task and ISR allocation. 19
Inspector Inspector Verification Verification of real target of timing real target behavior timing and behavior a resource efforts resource as well efforts as automatic as well as detection automatic of detec divergence divergence between system between model system and its model and its software implementation. software implementation. 20
Use the TA Inspector Use the for: TA Inspector for: Verification of system Verification implementations of system implementations target hardware on target hardware Comparison of simulation Comparison results of system and system implementations implementations against simulation results and model specification Detection of hardware bottlenecks Detection of hardware bottlenecks Reverse/re-engineering of legacy applications Reverse/re-engineering of legacy applications 21 21
Inspector The TA Inspector supports at the verification of real target timing behavior and resource efforts. Furthermore, the TA Inspector supports the automatic detection of divergences between a system model and the generated and executing code on the target. Automatically generated validation reports give project managers and customers easily a precise and automatized status of the delivered products quality. Use the TA Inspector for: Automated evaluation of imported hardware traces regarding existing requirements on timing and resource consumption Reconstruction of a timing model from a hardware trace Fast system health status detection Identification of critical scenarios Helpful instrument for detecting timing bugs in the application software or operating system Key-features of the TA Inspector: Automatically re-construct a timing model from a real hardware target trace Intuitively compare hardware measures with simulation results and therefore, validate the implementation with the simulation Import of standard and customer specific hardware traces Comprehensive and intuitive visualization of hardware traces Validate the hardware trace against specified requirements and generate reports for documentation or project management reporting Automatically extract stimulation patterns from imported hardware traces Execute time schedule evaluations of the target hardware Perform time, distribution, and estimator analysis of target hardware regarding Temporal resource consumption Time responses Metrics and event-chains Requirement violations Reverse-engineer application software resource models from hardware traces Extract real environment stimulation patterns, e.g. for further use in the TA Simulator 22
Automated Trace Import and Model Re-construction Importing target traces and automatically reconstructing a timing model based on individual execution architectures for review or high level evaluation steps. Schedule Sequence Event-chains and other requirements can be evaluated in the same way as with TA Simulator, simply by copying the requirements specification. This enables the evaluation of the interaction between software and real target hardware as well as an immediate detection of differences between design and implementation. Timing and Performance Metrics Distribution Analysis of the distribution of metric values on different entities and copying the critical entity instances in order to have a detail analysis. Automatically check Target against Specification Detection of divergences between specification and implementation by comparing the automatically generated model of the target trace against the designed system model. Verification of Requirements Automatically generated report of verification status on all specified requirements for all kind of entity types giving a fast overview on its compliance/violation ratio. This allows to give project managers and customers a precise status report of the product delivery in a less time-consuming way. 23
TA Services TA Services Our goal is your Our successful goal is your and efficient successful multi-core and efficient software multi-core project. software project. With Timing-Architects With Tool Timing-Architects Suite we offer user-friendly Tool Suite we offer multi-core user-friendly technology. multi-core By providing technology. a comprehensive By providing a comprehe tools for designing, developing, tools for designing, and verifying developing embedded and verifying service embedded portfolio, including service profound portfolio, consulting including profound services, consulting multi- and real-time multi- many-core and real-time embedded many-core systems. embedded broad systems. training offers, broad and custom training software offers, and solutions, custom we software solut Our goal is to broaden Our your goal performance is to broaden and your increase performance the make and increase sure, your the embedded make sure software your embedded solution will software solution wi efficiency of your product efficiency through of your multi-core product technology. through multi-core perform technology. on the highest on the possible highest level. possible level. TA supports you to extract TA supports the true you potential to extract of the true new potential of the new Consulting Consulting Custom Software Custom Solution Software Solution Training Training We understand your We needs! understand We are your needs! With our We team are of highly With skilled our team and of highly Bring skilled your and engineers Bring and your developers engineers and d the experts regarding the embedded experts regarding motivated embedded software engineers motivated software we engineers up to speed we on the new up to multi-core speed on the new mu multi-and many-core multi-and software many-core software provide individual extensions provide individual for extensions processor for technology. processor We at technology. We a architectures. We support architectures. you with We support our tools. you with We are able our to tools. efficiently We are able Timing-Architects to efficiently provide Timing-Architects individual provide your multi-core design your decisions multi-core design customize decisions interfaces customize integrate interfaces trainings to integrate and workshops trainings to support and workshops to and assist you in the and migration assist you in the migration with an existing tool with chain an and existing tool chain your project and teams in your mastering project the teams in maste from single-core to multi-core from single-core to multi-core development process. development process. multi-core challenge. multi-core Our trainings challenge. Our tr processor system processor within all system within Our development all and Our research development and are research held by leading are experts held in by the leading experts phases of the development phases of cycle. the development departments cycle. are also departments looking are also field looking of multi-core software field multi-core software You have not the time You or have resources not the time forward resources to new missions, forward so to dare new missions, architectures so dare and embedded architectures and embedde to apply our tools to to your apply multi- our tools to your to ask questions and to feel ask free questions to and real-time feel free to systems, and real-time additionally systems, additiona core project yourself? multi-core Our highly project yourself? contact Our us about your contact specific us about your trained specific in didactic skills. trained Therfore, in didactic we skills. Th trained and motivated highly experts trained will and motivated multi-core challenge. multi-core We are challenge. can We guarantee are you the can best guarantee support you the bes assist you in the modeling experts of will your assist you happy in the to develop your happy individual to develop your you individual can get on the market. you can Besides get on the market. system, the import of modeling your data of to your system, software the solutions in software the area solutions of in the helping area you of to develop helping your you to develop you our tools, the architecture import design, of your data to embedded our tools, the real-time embedded multi-core real-time multi-core expertise, multi-core of course expertise, we of cou as well as the evaluation architecture and design, as systems. well as the systems. provide trainings and provide support trainings for the and suppo optimization of your evaluation embedded and optimization of your Timing-Architects product Timing-Architects portfolio product real-time system. Together embedded we get real-time system. (e.g. how to model an (e.g. embedded how to model an embe the most out of your Together multi-core we get the most out of real-time multi-core real-time system with multi-core TA system system! your multi-core system! Tool Suite and how to Tool evaluate Suite and your how to evalu system with TA Tool system Suite). with TA Tool Suite). For more information For please more feel information free to contact please us: feel info@timing-architects.com free to contact us: info@timing-architects.com or +49 (0) 941 604 889 or +49 250. (0) 941 604 889 250. 24 24
earch Research Projects Projects e from single The change to multi-core from technology single to multi-core in technology In order in to hold its position In order as to innovation hold its position leader as in innovation the leader in the systems embedded results in new systems challenges, results resulting new challenges, field of caused embedded by real-time field of embedded multi-core real-time systems, multi-core systems, eed to guarantee the need real-time to guarantee requirements real-time as requirements Timing-Architects as well as actively Timing-Architects participates actively in several participates in several efficient the use efficient of hardware use of resources hardware on resources a on national a highly and international national research and international projects with research projects with racting and interacting interfering and hardware interfering architecture. hardware architecture. university, SME and university, industry partners. SME, and industry partners. HEA Model AMALTHEA based Open Model Source based Open Source WEMUCS Tools for WEMUCS efficient and Tools iterative for efficient and iterative ment environment development for automotive environment multi-core for automotive development, multi-core optimization development, and test optimization of multi-core and test of multi-core. systems. software. software. Design of S³Core scheduling Design algorithms of scheduling and algorithms ZeloS³ and Development ZeloS³ of new Development integrated methods of new integrated methods nication methods communication for safety-critical methods multi-core for safety-critical for multi-core model-driven design for model-driven and hardware design executed and hardware executed e systems, as real-time well as methods systems, for as well analysis as methods for verification analysis for efficient verification and robust for efficient multi-core and systems. robust multi-core systems. luation of timing-requirements. and evaluation of timing-requirements. utomotive Industries Mobile Avionic Industrial and Medical Automation hitects provides leading solutions for the Most of the techniques and methodologies can be Industrial and Automotive Mobile Avionic sign, simulation, automated optimization and applied out-of-the-box in other domains, like avionic Medical or Automation fication of embedded real-time multi-core ur tools and expertise have been proven in industrial and medical automation, as well. In some cases domain-specific adaptions may be necessary to fully ects in the Timing-Architects automotive and mobile provides devices leading solutions support for the system design Most of or the development techniques and process methodologies or can be is gives us system deep design, understanding simulation, of the automated needs optimization, increase precision and of applied simulation. out-of-the-box Please feel in free other to domains, like avionic or nges arising target with verification the new multi-core of embedded real-time contact multi-core us in order to industrial discuss and specific medical requirements automation, of as well. In some cases y. systems. Our tools and expertise have been the proven respected in domain. domain-specific adaptions may be necessary to fully many projects in the automotive and mobile devices support the system design or development process or ive domain. This gives us deep understanding Mobile of the needs increase precision of simulation. Please feel free to and challenges arising with the new multi-core contact us in order to discuss specific requirements of ion for multi-core: technology. Motivation for multi-core: the respective domain. computation power Integrating co-processors into main-processor ficantly cheaper (as multiple ECUs) More flexibility in dynamic switching between Automotive Mobile cing weight (High-integration of multiple ECUs energy saving and performance e ECU) Motivation for multi-core: Reducing reaction Motivation time for applications for multi-core: More computation power ges by applying multi-core: More performance and Integrating bandwidth co-processors for multimedia into main-processor Significantly cheaper (as multiple ECUs) and soft real-time requirements applications More flexibility in dynamic switching between Reducing weight (High-integration of multiple ECUs energy saving and performance y criticality Challenges by applying multi-core: on one ECU) Reducing reaction time for applications ging highly collaborative and distributed Highly dynamic load requires flexibility of global lopment (i.e. Challenges AUTOSAR ) by applying multi-core: More performance and bandwidth for multimedia scheduling variability (generic Hard software and is real-time individually requirements applications Strong mode-dependency in application gured) Safety criticality Saving energy by Challenges frequency scaling by applying scheduling multi-core: Managing highly collaborative and distributed algorithms Highly dynamic load requires flexibility of global development (i.e. AUTOSAR ) Efficiently manage heavy scheduling use of resource locking High variability (generic software is individually due to many peripheral Strong interactions mode-dependency in application configured) Saving energy by frequency scaling scheduling algorithms Efficiently manage heavy use of resource locking due to many peripheral interactions 25 25
Facing the Multi-Core Challenge Dear Colleagues, Embedded systems technology has emerged in many fields of application during the last decades and significantly improved our personal and social productivity, health diagnostic and recovery as well as general comfort in daily life. However, even if embedded systems have made significant improvements in these fields, most systems are far away from fulfilling the criteria what the majority would call adaptive, intelligent or even safe. But, a new fundamental technology has been introduced by semiconductor vendors during the last years, having the potential to deliver enough computation power for highly advanced algorithms and programs a great possibility and mandatory step for better embedded systems. For the last three years, Timing-Architects has supported several companies all over the world with their first steps applying multi-core technology. We have faced many challenges and have solved many problems together with our customers. We have integrated the insights into our tools and we permanently share our knowledge with our customers and partners, in order to make the start and usage of multi-core technology much easier for them. Nevertheless, we also know the multi-core development process still has screws for improvement - necessarily we are calling out for an embedded domain mission, the Multi-Core Mission. Let us revolutionize the system development of embedded systems in a way that multi-core technology becomes not only applicable, but will extraordinary enable to enhance systems function, performance, reliability, and robustness. Let us use the possibility to restructure the development and integrate methodologies and technologies, which have been proven by time to significantly reduce or eliminate unnecessary manual development steps. Performing these inevitable steps, which by now simply were not applied because of the missing need to improve existing legacy repositories. All this is an invest, not to reduce engineer s jobs, but to give space and focus for using our personal capacity in a more valuable way. In order to follow this Multi-Core Mission, we need you. Facing the Multi-Core Challenge together with us, focusing on new technical question coming up every day with concurrent system development and integrating the insights in our services and tools. We are looking forward to help you with the migration and successful application of multi- and many-core systems. Join us and let s face the Multi-Core Challenge together. Sincerely, Dr. Michael Deubzer, CTO Timing-Architects Embedded Systems GmbH was awarded by the BMWi as Germanys most innovate Start-Up of the year 2011 as well as Germanys new information and technology company of the year 2013. 26
For more information please contact Timing-Architects Embedded Systems GmbH Franz-Mayer-Straße 1 93053 Regensburg Germany Phone: +49 (0) 941 604 889 250 Fax: +49 (0) 941 604 889 259 Email: info@timing-architects.com www.timing-architects.com Timing-Architects Embedded Systems GmbH quality management is certified according to DIN ISO 9001:2008