CATEGORY I TYPE OF INTERFACE Interfaces that the equipment asynchronously multiplexes into (or demultiplexes from) higher speed signals



Similar documents
TAN-030 Application Note Performance Characteristics of the XRT7300 Device for DS3 Applications Rev. 1.00

ANT-20, ANT-20E Advanced Network Tester PDH MUX/DEMUX

Application Note. Line Card Redundancy Design With the XRT83SL38 T1/E1 SH/LH LIU ICs

INTERNATIONAL TELECOMMUNICATION UNION

DigiPoints Volume 1. Student Workbook. Module 5 Growing Capacity Through Technology

LAB 12: ACTIVE FILTERS

Sol: Optical range from λ 1 to λ 1 +Δλ contains bandwidth

Chapter 12: The Operational Amplifier

DS26303 OCTAL 3.3V T1/E1/J1 SHORT HAUL LIU PRODUCT BRIEF

Chapter 6 Bandwidth Utilization: Multiplexing and Spreading 6.1

INTRODUCTION TO COMMUNICATION SYSTEMS AND TRANSMISSION MEDIA

(Refer Slide Time: 2:10)

TECHNICAL TBR 12 BASIS for December 1993 REGULATION

TUTORIAL FOR CHAPTER 8

Multiplexing. Multiplexing is the set of techniques that allows the simultaneous transmission of multiple signals across a single physical medium.

2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier

Timing Errors and Jitter

The Calculation of G rms

TECHNICAL TBR 14 BASIS for April 1994 REGULATION

DataSMART 554 & 558 T1/FT1 Plug-in DSU/CSUs Page 1 of 8. T1/FT1 Single-port Plug-in DSU/CSUs

DS2186. Transmit Line Interface FEATURES PIN ASSIGNMENT

Lab #9: AC Steady State Analysis

The Phase Modulator In NBFM Voice Communication Systems

UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences. EE105 Lab Experiments

Chapter 4 T1 Interface Card

Lecture 12 Transport Networks (SONET) and circuit-switched networks

Propagation Channel Emulator ECP_V3

DS2187 Receive Line Interface

It explains the differences between the Plesiochronous Digital Hierarchy and the Synchronous Digital Hierarchy.

1+1 PROTECTION WITHOUT RELAYS USING IDT82V2044/48/48L & IDT82V2054/58/58L HITLESS PROTECTION SWITCHING

DS-3 Technology and Testing Overview

TCOM 370 NOTES 99-6 VOICE DIGITIZATION AND VOICE/DATA INTEGRATION

MT9043 T1/E1 System Synchronizer

Designing Stable Compensation Networks for Single Phase Voltage Mode Buck Regulators

DigiPoints Volume 1. Student Workbook. Module 4 Bandwidth Management

PART 3 - Access Services Original Page 1 SECTION 31 - Synchronous Broadband Network Services (SBNS) ACCESS SERVICE

Wideband Driver Amplifiers

DCM555 - Data Communications Lab 8 Time Division Multiplexing (TDM) Part 1 - T1/DS1 Signals

)454 6 ")43 0%2 3%#/.$ $50,%8 -/$%- 34!.$!2$):%$ &/2 53% ). 4(% '%.%2!, 37)4#(%$ 4%,%0(/.%.%47/2+ $!4! #/--5.)#!4)/. /6%2 4(% 4%,%0(/.%.

W a d i a D i g i t a l

Physical Layer, Part 2 Digital Transmissions and Multiplexing

AN-837 APPLICATION NOTE

What Does Communication (or Telecommunication) Mean?

CHAPTER 8 MULTIPLEXING

Clock Data Recovery Design Techniques for E1/T1 Based on Direct Digital Synthesis Author: Paolo Novellini and Giovanni Guasti

Engineering Sciences 22 Systems Summer 2004

TUBE-TECH HLT 2A Stereo High- and Low shelving, T- filter & Low- and High cut

Spike-Based Sensing and Processing: What are spikes good for? John G. Harris Electrical and Computer Engineering Dept

Using Pre-Emphasis and Equalization with Stratix GX

GSM Testers for Rent and Sale

Communications. SONET/SDH Multi-Ch/Multi-Rate Framer+Serdes Mappers + Framers Transceivers/CDR

Pericom PCI Express 1.0 & PCI Express 2.0 Advanced Clock Solutions

Chapter 4: Passive Analog Signal Processing

Solution. (Chapters ) Dr. Hasan Qunoo. The Islamic University of Gaza. Faculty of Engineering. Computer Engineering Department

CLOCK AND SYNCHRONIZATION IN SYSTEM 6000

PCI Express Transmitter PLL Testing A Comparison of Methods. Primer

SDI SDI SDI. Frame Synchronizer. Figure 1. Typical Example of a Professional Broadcast Video

The Effect of Network Cabling on Bit Error Rate Performance. By Paul Kish NORDX/CDT

VCO Phase noise. Characterizing Phase Noise

SIGNAL PROCESSING FOR EFFECTIVE VIBRATION ANALYSIS

How To Power A Powerline System On A Cell Phone Or Ipad Or Ipa Computer (For A Cell)

DigiPoints Volume 1. Leader Guide. Module 5 Growing Capacity Through Technology

Department of Electrical and Computer Engineering Ben-Gurion University of the Negev. LAB 1 - Introduction to USRP

Chapter 6 PLL and Clock Generator

Frequency Response of Filters

PIEZO FILTERS INTRODUCTION

AT&T Private Line Service OC-192 SERVICE DESCRIPTION AND INTERFACE SPECIFICATION

Chap 4 Circuit-Switching Networks

Selecting the Optimum PCI Express Clock Source

Objective. To design and simulate a cascode amplifier circuit using bipolar transistors.

Course 12 Synchronous transmission multiplexing systems used in digital telephone networks

DVT913 TV CHANNEL CONVERTER

Sheilded CATx Cable Characteristics

FAST TUTORIALS FOR TIME-CHALLENGED TECHNICIANS

Ultra640 SCSI Measured Data from Cables & Backplanes

T1/E1/OC3 WAN PLL WITH DUAL

Multiplexing on Wireline Telephone Systems

ANALYZER BASICS WHAT IS AN FFT SPECTRUM ANALYZER? 2-1

DATA SHEET. TDA1518BQ 24 W BTL or 2 x 12 watt stereo car radio power amplifier INTEGRATED CIRCUITS

Starlink 9003T1 T1/E1 Dig i tal Trans mis sion Sys tem

Chapter 9: Controller design

Computer Networks and Internets, 5e Chapter 6 Information Sources and Signals. Introduction

5 in 1 DVB-T Transmitter & Dual Cast Agile Digital Transposer TV EQUIPMENT

AN Application Note: FCC Regulations for ISM Band Devices: MHz. FCC Regulations for ISM Band Devices: MHz

Synchronous Optical Network (SONET)

Successfully negotiating the PCI EXPRESS 2.0 Super Highway Towards Full Compliance

EECC694 - Shaaban. Transmission Channel

Computer Networks II

SDH and WDM: a look at the physical layer

HDSL Basics. HDSL Basics. Introduction. HDSL Overview

MICROPHONE SPECIFICATIONS EXPLAINED

EMC Basics. Speaker : Alain Lafuente. Alain.lafuente@we-online.com

Working with T3 and T1: Technology, Troubleshooting and Fault Location

US-Key New generation of High performances Ultrasonic device

Network Performance: Networks must be fast. What are the essential network performance metrics: bandwidth and latency

V CC TOP VIEW. f SSO = 20MHz to 134MHz (DITHERED)

Glitch Free Frequency Shifting Simplifies Timing Design in Consumer Applications

1. ANSI T T1

SDH and WDM A look at the physical layer

VCO K 0 /S K 0 is tho slope of the oscillator frequency to voltage characteristic in rads per sec. per volt.

Transcription:

TAN-048 AP NOTE HOW THE JITTER TRANSFER CHARACTERISTICS OF THE XRT71D00 DS3/E3/STS-1 JITTER ATTENUATOR IC COMPARES WITH THE JITTER TRANSFER CHARACTERISTIC REQUIREMENTS OF BELLCORE GR-499- CORE 1

INTRODUCTION The purpose of this Applications Note is two-fold. 1. To present the Jitter Transfer Characteristics of the XRT71D00 device, for DS3 Applications, and 2. To illustrate how these Jitter Transfer Characteristics compare with the Category II Interface to Category II Interface Jitter Transfer Characteristics requirements per (for DS3 applications). JITTER TRANSFER CHARACTERISTIC REQUIREMENT FOR DS3 APPLICATIONS For DS3 Applications, specifies Jitter Transfer Characteristic requirements for three combinations of interfaces/configurations. Category II Type of Interface to Category I Type of Interface (e.g., for an M13 MUX application, this configuration relates the input Jitter, within an input DS3 signal, to the resulting output jitter, within an output DS1 signal). Category I Type of Interface to Category I Type of Interface (e.g., this configuration would typically involve jitter across a Multiplexer/De-Multiplexer pair). Category II Type of Interface to Category II Type of Interface (e.g., this configuration would typically involve jitter within a Repeater/Regenerator application). For completeness, the Bellcore definition of each of the Category I and Category II types of interfaces are presented below. CATEGORY I TYPE OF INTERFACE Interfaces that the equipment asynchronously multiplexes into (or demultiplexes from) higher speed signals Examples of Category I Type of Interface Low speed interfaces to Multiplexers (e.g., the DS1 interface to an M13 MUX). Low speed interfaces to Add-Drop MUXes and, Low speed interfaces to Digital Cross Connect Systems (DCS) 2

CATEGORY II TYPE OF INTERFACE Interfaces for signals that do one of the following. Regenerates Demultiplexes into (or is created by) lower speed signals. Synchronously multiplexes into (or demultiplexes from) higher speed signals. Examples of Category II Type of Interface Regenerators High Speed interfaces to Multiplexers (e.g., the DS3 interface to an M13 MUX). High Speed interfaces to Add-Drop MUXes and/ High Speed interfaces to Digital Cross Connect Systems (DCS) Jitter Transfer Characteristics Requirements (Summary) As mentioned above, specifies the Jitter Transfer Characteristic requirements for the following Interface Configurations. Category II Type of Interface to Category I Type of Interface (e.g., for an M13 MUX application, this configuration relates the input Jitter, within an input DS3 signal, to the resulting output jitter, within an output DS1 signal). Category I Type of Interface to Category I Type of Interface (e.g., this configuration would typically involve jitter across a Multiplexer/De-Multiplexer pair). Category II Type of Interface to Category II Type of Interface (e.g., this configuration would typically involve jitter within a Repeater/Regenerator application). Out of each of these Category Interface/Configurations, the only one that will be discussed in this document is the Category II Type of Interface to Category II Type of Interface Jitter Transfer Characteristic requirements. Each of the remaining Category Interface/Configurations involve determining the Jitter Transfer Characteristics across other circuitry, such as Multiplexer/De-Multiplexer pairs, Digital Cross-Connect System, and Add-Drop-MUXes. Since the intent of this document is to discuss Jitter Characteristics of LIU and the XRT71D00 devices, discussions of these remaining Category Interface/Configurations are beyond the scope of this document. The Jitter Transfer Characteristic Requirement for a Category II to Category II type of Interface (in DS3 applications) is plotted below in Figure 1. 3

0.1dB Slope = -20dB/Decade Jitter Gain (db) 10 59.6kHz 596kHz Jitter Frequency, Hz Figure 1, Illustration of the Jitter Transfer Characteristic requirements for Category II to Category II Type of Interfaces (e.g., DS3 Repeater/Regenerator Applications). Figure 1 indicates that (for a Category II to Category II Type of Interface/Configuration), the maximum Jitter Gain (over all frequencies above 10Hz) is 0.1dB. Further, this curve indicates that a 20dB/decade roll-off, in the Jitter Gain must begin at frequencies of 59.6kHz or less. 4

JITTER TRANSFER CHARACTERISTIC MEASUREMENTS OF THE XRT71D00 DEVICE Jitter Transfer Characteristics measurements of the XRT71D00 (for DS3 applications) have been recorded and are tabulated below in Table 1. Please note that measurements were taken for whenever the input jitter amplitude is small (e.g., 1UIpp) and large (e.g., 10 UIpp). Further, these measurements were also made for the two different settings of the BWS (Bandwidth Select) input pin. Table 1, The Jitter Transfer Characteristics of the XRT71D00 device, for DS3 Applications BWS Setting Low High Low High Input Jitter (UI-pp) 1 UI 1 UI 10 UI 10 UI Jitter Frequency (Hz) Jitter Gain (db) Jitter Gain (db) Jitter Gain (db) Jitter Gain (db) 10-0.10-0.10-0.30-0.01 20-2.04-0.24-2.24-0.13 30-3.68-0.35-4.33-0.36 40-5.98-0.53-6.16-0.78 50-7.55-1.00-7.82-1.12 60-9.57-1.46-9.17-1.66 80-12.54-2.25-11.28-2.64 100-14.67-3.07-13.36-3.52 125-16.67-3.88-14.91-4.76 150-17.32-5.74-16.78-5.89 200-18.77-7.75-18.96-7.90 300-21.43-12.04-21.81-10.89 500-22.22-16.74-26.09-14.98 >1000-25.42-21.13-33.44-20.66 NOTE: This data was taken via the XRT71D00/XRT7300 Evaluation Board. Hence, this data reflects the Jitter Transfer Characteristics of the composite solution consisting of both the XRT7300 LIU IC and the XRT71D00 Jitter Attenuator IC. Table 1 indicates that when the BWS input pin is low, then the -3dB Frequency of the Jitter Transfer Characteristic curve occurs at around 30Hz. Further, this table also 5

indicates that when the BWS input pin is high, then the -3dB Frequency of the Jitter Transfer Characteristic curve occurs at around 100 Hz. Figure 2 presents a plot of each of the Jitter Transfer Curves, listed in Table 1. Jitter Transfer Characteristics of the XRT71D00 Jitter Attenuator IC, DS3 Applications 5 0-5 -10 Jitter Gain, db -15-20 Jitter Transfer, BW S = Low, Input Jitter = 1UI-pp Jitter Transfer, BWS = High, Input Jitter = 1UI-pp Jitter Transfer, BW S = Low, Input Jitter = 10UI-pp Jitter Transfer, BWS = High, Input Jitter = 10UI-pp -25-30 -35-40 0 100 200 300 400 500 600 700 800 900 1000 Jitter Frequency, Hz Figure 2, Plot of the Jitter Transfer Characteristics of the XRT71D00 Jitter Attenuator IC, for DS3 Applications. TEST CONDITIONS a. Tests performed with the Wandel & Goltermann ANT20, on the XRT7300/XRT71D00 Evaluation Board. b. Test Pattern used: Unframed 2^23-1 PRBS Pattern. c. Transmit Output of W&G ANT20 Tester = DSX-3 6

CONCLUSIONS: The test results, presented in Table 1 and Figure 2 indicate the following. a. The peak gain of the Jitter Transfer Characteristics never exceeds 0.1dB. b. The -3dB Frequency of the XRT71D00 device (for each of the various combinations of BWS and FSS settings) is all considerably less than 59.6kHz. As a consequence, the Jitter Transfer Characteristics of the XRT71D00 device is compliant with the Jitter Transfer Characteristic requirements, per Bellcore GR-499- CORE (for a Category II to Category II type of Interface DS3 Applications). 7

8