(12) Umted States Patent (10) Patent N0.: US 7,861,013 B2 Hunkins et a]. (45) Date of Patent: Dec. 28, 2010
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1 US B2 (12) Umted States Patent (10) Patent N0.: US 7,861,013 B2 Hunkins et a]. (45) Date of Patent: Dec. 28, 2010 (54) DSPLAY SYSTEM WTH FRAME REUSE 6,884,116 B2 4/2005 Suzuki et a1. USNG DVDED MULT-CONNECTOR ELEMENT DFFERENTAL BUS CONNECTOR (Continued) (75) nventors: James D. Hunkins, Toronto (CA); FOREGN PATENT DOCUMENTS Lawrence J. King, NeWmarket (CA); EP A1 12/2003 Syed A. Hussain, Scarborough (CA) (73) Assignee: éitlagggczlcnzgogies ULC, Markham, (Continued) OTHER PUBLCATONS ( * ) Notice: Subject to any disclaimer, the term of this patent is extended Or adjusted under 35 _ Allen, Danny; External PC-EXpress Graphlcs for Laptops; from U'SC' 154(1)) by 171 days' wwwpcworldcom; Apr. 23, 2007; pp (21) Appl. N0.: 11/955,7s3 C t' d ( on me ) Primar y ExamineriAlford W Kindred (22) Filed: Dec. 13, 2007 Assistant ExamineriDavid E MartineZ (65) P P bl D rior u ication ata (74) Attorney, Agent, or FirmiVedder Price P.C. Us 2009/ A1 Jun. 18, 2009 (57) ABSTRACT (51) /00 ( ) A method includes reducing power of a?rst graphics proces G 06 F 13/12 (2006:01) sor'by disabling or not using its rendering engine and leaving G06F 13/00 ( ) a d1splay eng1ne ofthe same?rst graph1cs processor capable '. /. / of out P uttin g dis P la y frames from a corres P ondin g?rst frame (52) US. Cl /30, , buffer to a display A display frame is rendered by a Second (58) Field of Classi?cation Search /30, graphics processor While the rendering engine of the?rst 710/62> 300 graphics processor is in a reduced power state, such as a See apphcanon?le for Complete Search hlstory' non-rendering state. The rendered frame is stored in a corre (56) References Cited sponding second frame buffer of the second graphics proces U.S. PATENT DOCUMENTS sor, such as a local frame buffer and copied from the second frame buffer to the?rst frame buffer. The copied frame in the?rst frame buffer is then displayed on a display While the 4,992,052 A 2/l99l Verhoeven rendering engine of the?rst graphics processor is in the 6,130,487 A 10/2000 Bertalan et a1. reduced power state. Accordingly thermal output and power 6,162,068 A 12/2000 Wu output is reduced With respect to the?rst graphics processor 6,171,116 B1* 1/2001 Wicks et a /79 since it does not do frame generation using its rendering 6,261,104 B1 7/2001 Leman engine, it only uses its display engine to display frames gen 6,338,635 B1 1/2002 Lee erated by the second graphics processor. 6,721,188 B1 4/2004 Jarvis etal. 6,811,433 B2 11/2004 Jou 12 Claims, 28 Drawing Sheets
2 US 7,861,013 B2 Page 2 US. PATENT DOCUMENTS TW B 1/2005 7,402,084 B2 7/2008 Wu 2006/ Al* 8/2006 Carty /305 OTHER PUBLCATONS 2006/ A1 12/2006 HO Valich, Theo; External R600 and Cross?re cards are on the Way; from 2009/ A1 6/2009 Hunkins www?leinquirer net; Mar ) L3 2009/ A1 6/2009 Hunkms et a1 PC Express External Cabling Speci?cation Revision 1.0; PC-SG; FOREGN PATENT DOCUMENTS JAL 4, 2007; PP 1442 JP /2004 * cited by examiner
3 US. Patent Dec. 28, 2010 Sheet 1 0f 28 US 7,861,013 B2
4 US. Patent Dec. 28, 2010 Sheet 2 0f 28 US 7,861,013 B2 m2 glgw
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10 US. Patent Dec. 28, 2010 Sheet 8 0f 28 US 7,861,013 B2 Pin # Top row "Plug side shape" T62 3rd mate T61 2nd mate T60 3rd mate T59 3rd mate T58 2nd mate T57 3rd mate T56 3rd mate T55 2nd mate T54 3rd mate T53 3rd mate T52 2nd mate T51 3rd mate T50 3rd mate T49 2nd mate T48 3rd mate T47 3rd mate T46 3rd mate T45 3rd mate T44 2nd mate T43 3rd mate T42 3rd mate T41 2nd mate T40 3rd mate T39 3rd mate T38 2nd mate T37 3rd mate T36 3rd mate T35 2nd mate T34 3rd mate T33 3rd mate 1st mate "Receptacle (SMT)" CPRSNT1# Opt 3.3V Return <-> Dif Data PC E+ Dif Data PCE Dif Gnd Dif Data PC E+ Dif Data PCE Dif Gnd Dif Data PC E+ Dif Data PCE Dif Gnd Dif Data PC E+ Dif Data PCE Dif Gnd Opt 3.3V Power <-> Opt 3.3V Power <-> Opt 3.3V Power <-> Opt 3.3V Power <-> Dif Gnd Dif Data PC E+ Dif Data PCE Dif Gnd Dif Data PC E+ Dif Data PCE Dif Gnd Dif Data PC E+ Dif Data PCE Dif Gnd Dif Data PC E+ Dif Data PCE FG. 10 TPO TNO TP1 TN1 TP2 TN2 TP3 TP4 TP4 TN4 TP5 TN5 TP6 TN6 TP7 TN7
11 _TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT _OODDDDDDDDDDDDRCCCDDDDDDDDDDDDOC.PPWWWWWWWWWWWWGPPWWWWWWWWWWWWWPP _ttddgddgddgddgwewagddgddgddgddtr.300.aanaanaanaanwrrknaanaanaanaaqws WwmwawwawwawmaesoEdwmdmmdmmdwmwNc Tmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm US. Patent Dec. 28, 2010 Sheet 9 0f 28 US 7,861,013 B2 n _ - TT _ _ FmDQMCC CC%#m PN PM fmmee EEw e dtn U0 PP _ aw _mm+_ +- +_m aa m,v _ Transmitters FG " _ > m _mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm _mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm
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13 US. Patent Dec. 28, 2010 Sheet 11 0f 28 US 7,861,013 B2 B32 2nd mate Dlf Gnd! RP8 B30 B31 3rd 2nd mate Dif Data PCE+ Dtf Gnd i! RN8 B29 3rd mate Dif Data PCE 1! RP9 -- B28 B27 3rd 2nd mate Dif Data PCE+ Dif Gnd i! RN9 B26 3rd mate Dif Data PCE! B25 2nd mate Dif Gnd i! RP1O B24 3rd mate Dif Data PCE+ i RN10 B23 3rd mate Dif Data PCE i B22 2nd mate Dif Gnd i i RN11 RP11 B20 B21 3rd mate Dif Data PCE- PCE+ i i B19 2nd mate Dif Gnd - : DifClkP B18 3rd mate Dif Clock <->!! DifClkN B16 B17 3rd 2nd mate Dif Clock <-> Dif Gnd!! RN12 RP12 B14 B15 3rd mate Dif Data PCE- PCE+!! l RN13 RP13 B13 B12 B11 3rd 2nd mate Dif Data PCE+ Dif Gnd l B10 2nd mate Dif Gnd! RN14 RP14 B9 B8 3rd mate Dif Data PCE B7 2nd mate Dif Gnd i RP15 B6 3rd mate Dif Data PCE+ i! RN15 B5 3rd mate Dif Data PCE- i! B4 2nd mate Dif Gnd i! B3 2nd mate Opt 3.3V Return i! B2 3rd mate Opt 3.3V Power i B1 2nd mate SB_RTN i i i i Receivers (Trans on GPU) FG. 13 Connector shell i. l
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15 US. Patent Dec. 28, 2010 Sheet 13 0f28 US 7,861,013 B2 Host Side [702 PM Ri é tl tttp'e Top row F's'h gpsége Connector shell T1 CPRSNT1# 3rd mate T2 Opt 3.3V Return <-> 3rd mate i T3 Gnd 2nd mate - TPO T4 Dif Data PCE+ 3rd mate! TNO T5 T6 Dif Gnd Data PCE- 3rd 2nd mate TP1 T7 Dif Data PCE+ 3rd mate ' TN1 T8 Dif Data PCE- T9 Dif Gnd 3rd mate 2nd mate! TP2 T10 Dif Data PCE+ 3rd mate i TN2 T11 Dif Data PCE- 3rd mate ' T12 Dif Gnd 2nd mate! TP3 T13 Dif Data PCE+ 3rd mate TN3 T14 Dif Data PCE- 3rd mate i T15 Dif Gnd 2nd mate T16 Reserved1 <-> 3rd mate! T18 T17 CPWRON CPERST# <-> 3rd mate T19 CWAKE# <-> 3rd mate ' T20 Dif Gnd 2nd mate! TP4 T21 Dif Data PCE+ 3rd mate TN4 T23 T22 Dlf Dif Gnd Data PCE- 3rd 2nd mate i TP5 T24 Dlf Data PCE+ 3rd mate, TN5 T25 Dif Data PCE- 3rd mate TP6 T26 T27 Dif Gnd Data PCE+ 2nd 3rd mate TN6 T28 Dif Data PCE- 3rd mate! TP7 T30 T29 Dif Gnd Data PCE+ 3rd 2nd mate TN? T32 T31 Dif Gnd Data PCE- 3rd 2nd mate - T33 Opt 3.3V Power <-> 3rd mate! T34 CPRSNT2# 3rd mate l Connector shell! Transmitters FG. 15
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17 US. Patent Dec. 28, 2010 Sheet 15 0f 28 US 7,861,013 B2 Downstream side [ _ Bottom rov. Plug slde Receptacle ' / Pm # shape" (Through hole)" Cable Connector shell B34 2nd mate SB_RTN B33 3rd mate Opt 3.3V Power B32 2nd mate Opt 3.3V Return B31 2nd mate Dif Gnd RNO RPO B30 B29 3rd mate Dif Data PCE+ PCE B28 2nd mate Dif Gnd ' RP1 RN1 B27 3rd mate B26 3rd mate Dif Data PClE+ Dif Data PCE B25 2nd mate Dif Gnd RP2 B24 3rd mate Dif Data PCE+ ' RN2 B23 3rd mate Dif Data PCE B22 2nd mate Dif Gnd RP3 B213rd mate Dif Data PClE+ RN3 B20 3rd mate Dif Data PClE B19 2nd mate Dif Gnd DifClkP DifClkN B18 3rd mate B17 3rd mate Dif Clock Dif Clock B16 2nd mate Dif Gnd ' RP4 RN4 B15 3rd mate B14 3rd mate Dif Data PClE+ Dif Data PCE B13 2nd mate Dif Gnd RP5 B12 3rd mate Dif Data PClE+ ' RN5 B113rd mate Dif Data PCE B10 2nd mate Dif Gnd RP6 B9 3rd mate Df Data PClE+ RN6 B8 3rd mate D f Data PCE B7 2nd mate Dif Gnd RN7 RP7 B5 B6 3rd mate Dif Data PClE+ PCE- -- B4 2nd mate Dif Gnd ' B3 2nd mate Opt 3.3V Return B2 3rd mate Opt 3.3V Power B1 2nd mate Connector shell SB_RTN Receivers (Trans on GPU) FG. 17
18 US. Patent Dec. 28, 2010 Sheet 16 0f 28 US 7,861,013 B2 Top row P'" # s?gpsege (smpt)" 1st mate T34 3rd mate CPRSNT1# '. "Pl i "Rece tacle i T33 3rd mate Opt 3.3V Return <-> - T32 2nd mate Gnd! T313rd mate Dif Data PC E+ TPO! T30 3rd mate T29 2nd mate Dif Data PCE- Dif Gnd TNO ' T28 3rd mate Dif Data PC E+ TP1! T27 3rd mate T26 2nd mate Dif Data PCE- Dif Gnd TN1 i T25 3rd mate Dif Data PC E+ TP2 i T24 3rd mate Dif Data PCE- TN2, T23 2nd mate D f Gnd T22 3rd mate Dif Data PC E+ TP3 i T213rd mate Dif Data PCE- TP4 T20 2nd mate Dif Gnd! T19 3rd mate Reserved1 <->! T18 3rd mate CPERST# <-> T17 3rd mate CPWRON <-> ' T16 3rd mate CWAKE# <->! T15 2nd mate Dif Gnd T14 3rd mate Dif Data PC E+ TP4 i T13 3rd mate Dif Data PCE- TN4, i "? a a Peta TF5 T10 3rd mate Dif Data PCE- TN5 i T9 2nd mate Dif Gnd T8 3rd mate Dif Data PC E+ TP6 : T7 3rd mate Dif Data PCE- TN6 i T6 2nd mate T5 3rd mate Dif Gnd Dif Data PC E+ TP7 i T4 3rd mate Dif Data PCE- TN7 - T3 2nd mate Gnd! T2 3rd mate Opt 3.3V Power <-> T13rd mate CPRSNT2#! 1st mate Transmitters (Rec on GPU) FG. 18
19 US. Patent Dec. 28, 2010 Sheet 17 0f 28 Connector shell US 7,861,013 B2!! i _ T2 T1 Opt CPRSNT1# 3.3V Return <-> 3rd mate! T3 Gnd 2nd mate i TPO T4 Dif Data PCE+ 3rd mate i TNO T5 Dif Data PCE- 3rd mate i TP1 -- T6 T7 Dif Gnd Data PCE+ 2nd 3rd mate i TN1 T8 Dif Data PCE- 3rd mate i -_ T9 Dif Gnd 2nd mate ' TN2 TP2 T10 T11 Dif Data PCE+ PCE- 3rd mate T12 Dif Gnd 2nd mate TP3 TN3 T13 Dif Data PCE+ T14 Dif Data PCE- 3rd mate 3rd mate i T15 Dif Gnd 2nd mate T16 Reserved1 <-> 3rd mate T17 CPERST# <-> 3rd mate i T18 CPWRON <-> 3rd mate, T19 CWAKE# <-> 3rd mate T20 Dif Gnd 2nd mate ' TP4 T21 Dif Data PCE+ 3rd mate! TN4 T22 Dif Data PCE- 3rd mate T23 Dif Gnd 2nd mate TP5 T24 Dif Data PCE+ 3rd mate! TN5 T25 Dif Data PCE- 3rd mate T26 Dif Gnd 2nd mate TP6 TN6 T27 Dif Data PCE+ T28 Dif Data PCE- 3rd mate 3rd mate i T29 Dif Gnd 2nd mate. TP7 T30 Dif Data PCE+ 3rd mate TN? T31 Dif Data PCE- 3rd mate i T32 Gnd 2nd mate. T33 Opt 3.3V Power <-> 3rd mate T34 CPRSNT2# Connector shell 3rd mate Transmitters FG. 19 i i
20 US. Patent Dec. 28, 2010 Sheet 18 0f 28 US 7,861,013 B2 i i 702 i i / i 1st mate Flat Cable B1 SB_RTN Opt 3.3V Return Power 2nd 3rd mate i B4 Dif Gnd 2nd mate B5 B6 B7 Dif Gnd Dif Data PCE+ PCE- 2nd 3rd mate RNO RPO -- B8 Dif Data PCE+ 3rd mate RP1 B9 Dif Data PCE- 3rd mate RN1 B10 Dif Gnd 2nd mate B12 B11 Dif Data PCE- PCE+ 3rd mate RN2 RP2 B13 Dif Gnd 2nd mate B14 Dif Data PCE+ 3rd mate RP3 B15 Dif Data PCE- 3rd mate RN3 B16 Dif Gnd 2nd mate B17 Dif Clock 3rd mate DifClkP, B18 Dif Clock 3rd mate DifClkN, B19 Dif Gnd 2nd mate ' B20 Dif Data PCE+ 3rd mate RP4 ' B22 B21 Dif Gnd Dif Data PCE- 3rd 2nd mate RN4 -- B23 Dif Data PCE+ 3rd mate RP5 B25 B24 Dif Gnd Dif Data PCE- 3rd 2nd mate RN5 -- B26 Dif Data PCE+ 3rd mate RP6 B27 B28 Dif Gnd Dif Data PCE- 3rd mate 2nd mate RN B29 Dif Data PCE+ 3rd mate RP?. B30 Dif Data PCE- 3rd mate RN? ' B31 Dif Gnd 2nd mate ' l B32 Opt 3.3V Return 2nd mate B33 Opt 3-3V Power 3rd mate B34 SB_RTN 2nd mate st mate l i Receivers FG. 20 l l
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