Solving Network Challenges

Transcription

1 Solving Network hallenges n Advanced Multicore Sos Presented by: Tim Pontius

2 Multicore So Network hallenges Many heterogeneous cores: various protocols, data width, address maps, bandwidth, clocking, etc. Typically very high bandwidth between cores or to/from main memory So floor plan may be driven by board requirements Physical design is challenging for large chips Need to maximize performance while minimizing area and power consumption Need fast and easy performance verification Solving Network hallenges for Advanced Multicore Sos - Tim Pontius 2

3 May want to divide large chips into several different domains Want network to safely (power, clock, voltage, etc) and automatically handle domain crossings S S S S S S Hypothetical Multicore Network T T T T T T T Some links may be wider T M than others ntelligent agents allow each core to use different protocols, data widths, address map, clock frequencies, etc. T T T M M M S T T T T T T T T S S S S S M M Solving Network hallenges for Advanced Multicore Sos - Tim Pontius 3

4 Network Must Be Scalable Want to connect several (maybe dozens or hundreds) of cores to the network Each core may be unique osts of network must be linear with number of cores even though communication possibilities increase quadratically Exponential area increase, power increase, latency, etc are all unacceptable Need good support for unbalanced networks too nitiators Targets, nitiators Targets, nitiators Targets Desire flexibility in network topology But still need guarantees that deadlock cannot happen Solving Network hallenges for Advanced Multicore Sos - Tim Pontius 4

5 outer Design is mportant for Scalability Per-port/per-V buffer sizing Full throughput switch Wormhole routing redit based flow control MxN outer VA units (per V) nput nput port port port unit unit unit V Storage redit tracking SA units (per oport) Switch Solving Network hallenges for Advanced Multicore Sos - Tim Pontius 5

6 Mem Flexible Topology Examples Accel PUs trl Solving Network hallenges for Advanced Multicore Sos - Tim Pontius 6

7 A ealistic Multicore Network Solving Network hallenges for Advanced Multicore Sos - Tim Pontius 7

8 Must Be Deadlock Free Any possibility of deadlock must be eliminated before the device is manufactured Non-blocking flow control is important to avoid deadlock Virtual channels (or a similar method) can allow other traffic to bypass blocked traffic Without non-blocking flow control, any loops in the network topology become hazardous deally, network automatically generates routes that are guaranteed deadlock free Alternatively, at least a check is needed for deadlock possibility Especially important for a non-uniform network Make sure your network provider addresses this issue! Solving Network hallenges for Advanced Multicore Sos - Tim Pontius 8

9 Performance Verification Typically the performance of a network depends on both the configuration of the network (topology, etc) and the nature of the traffic carried by that network Often real traffic is not available Need good tools to help develop realistic traffic examples Want multiple use cases, possibly with different parts of the So powered on/off or with modifications to clock frequencies Need to quickly assess performance Transaction level modeling can significantly improve speed while maintaining cycle accuracy Solving Network hallenges for Advanced Multicore Sos - Tim Pontius 9

10 Monitoring and Trace Performance monitoring and hardware tracing provide excellent visibility into what is happening inside the So Allows user to trace traffic, monitor bandwidth, etc By making the monitor/trace logic efficient, one may choose to leave the function in the final So product However, security becomes a concern in such cases Must ensure this capability does not open a security hole Useful even when only included in prototypes Debug of development boards, FPGA implementations, etc Solving Network hallenges for Advanced Multicore Sos - Tim Pontius 10

11 Other mportant onsiderations ache coherence and /O coherence an simplify software development effort Support for DAM scheduling mprove DAM performance by scheduling transactions to minimize page misses and turn-around penalties Security features Prevent selected cores from accessing private data or secure portions of So Especially important for devices that can load apps in field Usually want a mix of /W, ead-only, and No-access Solving Network hallenges for Advanced Multicore Sos - Tim Pontius 11

12 Sample Security Solution Multi-region firewall enforces access policies Per-target e-programmable Layered architecture supports many domains with variable region sizes Target access control Per initiator Per role (e.g. secure/not) Per access type (D/W) PU & OS Flexible security error caching and reporting Mutually Secure Domains omm. Links Strea ming Media Media Stream Solving Network hallenges for Advanced Multicore Sos - Tim Pontius 12

13 Summary The interconnect network plays an important role in a Multicore So And presents many challenges Bandwidth, scalability, physical design, clocking issues, QoS, performance verification, deadlock avoidance, monitor/trace, power consumption, DAM scheduling, coherence, security Sonics products solve all of these challenges for you A total system approach 200+ successful tapeouts Over 2 Billion units shipped Visit our booth to learn more Solving Network hallenges for Advanced Multicore Sos - Tim Pontius 13

14 Questions Solving Network hallenges for Advanced Multicore Sos - Tim Pontius 14

15 Thank You Solving Network hallenges for Advanced Multicore Sos - Tim Pontius 15

16 Solving Network hallenges for Advanced Multicore Sos - Tim Pontius 16