Operational Amplifiers / Comparators Application Note Op-Amp / Comparator Tutorial

Transcription

1 Operational Ampliiers / Comparators Op-Amp / Comparator Tutorial No.1149EBY4 A TABLE OF CONTENTS 1.What is Op-Amp/Comparator? 1.1 Model o ampliier (Voltage ampliier) and Op-Amp 1.2 What is Op-amp/Comparator? 1.3 Op-amp and Comparator circuit construction 2.Absolute maximum rating 2.1 Rated power supply voltage 2.2 Rated dierential input voltage 2.3 Rated common mode input voltage 2.4 Maximum power dissipation and storage temperature range 2.5 Electrostatic discharge tolerance 3.Electrical characteristic o op-amp and comparator 3.1 Circuit current/quiescent current Icc / Iq and power consumption 3.2 Input oset voltage Vio 3.3 Input bias current/input oset current Ib/Iio 3.4 Common mode input voltage range Vicm/CMR 3.5 Maximum output voltage (output voltage range) Vom / Voh, Vol 3.6 Common Mode Rejection Ratio (CMRR) 3.7 Power Supply Rejection Ratio (PSRR) 3.8 Large signal voltage gain (Large amplitude voltage gain, open loop voltage gain) Av 3.9 Slew Rate (SR) 3.1 Response time tre / tphl / tplh 3.11 Open loop voltage gain requency characteristics and unity gain requency/gain bandwidth product 3.12 Model o negative eedback system and oscillation condition 3.13 Total Harmonic Distortion plus Noise (THD + N) 3.14 Equivalent input noise source 1/27

2 1.What is Op-Amp/Comparator? 1.1 Model o ampliier ( voltage ampliier ) and Op-Amp An ampliier has a unction to increase an input signal by ampliication actor o ampliier or outputting. Electric / Electronic circuit uses voltage and current in the main or input signal and output signal. Coniguration o such ampliying circuit is classiied into the our types shown below: 1. VCVS (Voltage Controlled Voltage Source) Voltage input/voltage output 2. CCCS (Current Controlled Current Source) Current input/current output 3. VCCS (Voltage Controlled Current Source) Voltage input/current output 4. CCVS (Current Controlled Voltage Source) Current input/voltage output Function required or all our types shown above is to detect and ampliy an input signal without attenuating, and supply output signal with no attenuation o the load. We will consider the unction required or an ampliier by modeling the input signal source, ampliier, and load. Figure (a) - (d) show the model o our ampliiers described above including the input signal source and load. Figure (a) shows the model o voltage controlled voltage source. Input resistance o this ampliier is represented by Ri, output resistance by Ro, and ampliication actor by Av. Input signal source is modeled by voltage source Vs, output resistance Rs, and load RL. Output voltage is calculated by the equation below by use o these models: Vo=(RL/(Ro+RL)) Av (Ri/(Rs+Ri)) Vs (1.1.1) Signal voltage is divided by Rs and Ri, so that the attenuated signal is input to the ampliier. Output voltage rom the ampliier is divided by Ro and RL, and supplied to the load. The greater Ri is, the less attenuated is the signal voltage input to the ampliier; the smaller Ro is, the less attenuated is the output voltage supplied to the load. Assume that Ri = [Ω] and Ro = [Ω] in the ormula (1.1.1), then Vo=Av Vs (1.1.2) We understand that ampliied voltage can be supplied to the load without attenuating, with no attenuation o voltage at the signal source. Thereore, it is desirable that ininite input resistance and zero output resistance are provided or voltage controlled voltage source. Input resistance and output resistance required or the ampliier o the other three types are summarized in the table Op-amp is a voltage controlled voltage source when classiied into the our types o ampliier described above. Thereore, high input resistance and low output resistance are preerable or an op-amp, which in general has a circuit coniguration close to such characteristics. Vs Rs Ri Vi Av Vi Ro RL Is Ii Rs Ri Ro RL Ai Ii table1.1.1 Ideal input and output resistance input output ampliier type resistance resistance VCVS (op-amp) CCCS (a) VCVS (op-amp) (b) CCCS VCCS CCVS Rs Vi Ii Ro Vs Ri G Vi Ro RL Is Rs Ri R Ii RL (c) VCCS (d) CCVS Fig The type o ampliier 2/27

3 1.2 What is Op-amp/Comparator? Op-amp (operational ampliier) is a dierential ampliier provided with high input resistance and low output resistance. It consists o + input terminal (non-inverting input terminal), - input terminal (inverting input terminal), output terminal and power supply terminal (plus and minus side), and the dierential voltage between + input terminal and - input terminal is increased by the ampliication actor provided by the ampliier, and output. Drawing symbol o op-amp is shown in igure Op-amp, in general use, composes a negative eedback circuit by connecting resistors and capacitors between the output terminal and - input terminal, and executes analogue signal processing such as ampliying o signal, addition, subtraction, and iltering. Figure shows an example o use or an ampliier. This circuit, which is called an inverting ampliier, increases an input signal by an ampliication actor determined by resistance R1 and R2, and outputs a signal with phase reversed 18 degrees. When the ampliication actor o op-amp is assumed to be "a", input signal "", and output signal "", "" can be represented by the equation below: =-(R2/(R1+(R1+R2)/a)) (1.2.1) Ampliication actor o op-amp (voltage gain) is great in general. Thereore the equation is approximated as ollows: -(R2/R1) (1.2.2) High ampliication actor is desired or op-amp in order to make output voltage error due to ampliication actor as small as possible.when we review the act that the ampliying is great, it means that the potential dierence between + input terminal and - input terminal is made as small as possible. In other words, the greater the ampliication actor is, the more established is the relation + = -. This relation where potential o + input terminal is almost equal to potential o - input terminal is called virtual short-circuit. When negative eedback circuit is conigured in use, this relation is established, and application circuit is designed by use o this relation. Terminal o comparator consists o + input terminal, - input terminal, output terminal, and plus/minus power supply terminal, which is the same as op-amp. Drawing symbol is also the same as op-amp (igure 1.2.1). It provides a circuit which ampliies the potential dierence between two input terminals and outputs either high or low. It is used in general or a voltage comparator circuit or ixing the potential o either + input terminal or - input terminal, and determining the high or low level o voltage o input signal with reerence to such potential. The output voltage level is as ollows: When "Potential o + input terminal > Potential o - input terminal" is established, high level is output. When "Potential o - input terminal > Potential o + input terminal" is established, low level is output. Great dierence between the op-amp and comparator is the availability o phase compensation capacitor. Op-amp requires phase compensation capacitor or preventing oscillation because it conigures a negative eedback circuit in use, while comparator does not require this capacitor because it does not conigure negative eedback. Phase compensation capacitor limits the response time o input/output time. Comparator which has no phase compensation capacitor has a greatly improved response capability in comparison with op-amp. Inveting input(-in) Positive(high side) supply voltage () Non inverting input(+in) Output() Negative(low side) supply voltage () Fig Op-amp and Comparator symbol 3/27

4 R2 voltage input voltage R1 a V REF reerence voltage VREF output voltage time Virtual short +=- (when voltage gain "a" is large value) (a) non inverting voltage comparator Relationship o input and output voltage =a (Vp-Vn) (-Vn)/R1=(Vn-)/R2 Equation o Output voltage =-{R2/(R1+(R1+R2)/a)} -(R2/R1) (A ) voltage input voltage output voltage time V REF voltage reerence voltage VREF output voltage input voltage time (b)inverting voltage comparator Fig inverting ampliier Fig input and output waveorm o voltage comparator 4/27

5 1.3 Circuit construction o operational ampliier and voltage comparator Fig shows internal circuit blocks o op-amp. Basically, it is constructed by three stages, that is input stage, gain stage and output stage. The input stage is dierential ampliier that ampliies dierence o two input voltage and suppress common mode voltage. Input common mode voltage range is mainly decided by this input stage. Voltage gain o op-amp is increased by gain stage, because only input stage voltage gain is not enough. For general op-amp, phase compensation capacitor is inserted between input and output o gain stage. Output stage suppresses op-amp characteristic luctuation caused by load. Output current driving ability is decided by output stage. The kinds o output circuit constructions are class A, class B, class C, and class AB etc. Harmonic distortion is deteriorated in class A, class AB, class B, class C sequence. Fig.1.3.1(b) speciies BA4558 simpliied schematic. It has class AB output stages that ensure low distortion. Fig shows voltage comparator construction. That is almost same as op-amp, but it is not inserted phase compensation capacitor because applications using negative eedback are not assume. Phase compensation capacitor limits operating speed, response time is very short by rejected this capacitor. Output stage constructions o voltage comparator are mainly open collector (or open drain) type and push-pull type. Fig (b) shows BA1393 simpliied schematic. The output stage is open collector type. +input phase compensation capacitor Cc +input input stage gain stage output stage output input stage gain stage output stage output -input -input (a) basic op-amp building blocks (a) basic voltage comparator building blocks -IN +IN OUT -IN OUT +IN input stage gain stage output stage input stage gain stage output stage (b) BA4558 sinpliied schematic (b) BA1393 simpliied schematic Fig op-amp circuit construction Fig voltage comparator circuit construction 5/27

6 2. Absolute maximum rating Typical items o absolute maximum rating op-amp/comparator include the ollowing: 1. Rated power supply voltage 2. Rated dierential input voltage 3. Rated common mode input voltage 4. Storage temperature range 5. Maximum power dissipation Absolute maximum rating reers to a condition which must not be exceeded even momentarily or the items described on speciication including the above. Applying a voltage in excess o absolute maximum rating and using under high and low temperature environment may cause characteristic deterioration and destruction o IC. 2.1 Rated power supply voltage It is the maximum power supply voltage that can be applied between plus power supply terminal (Vcc terminal) and minus power supply terminal (VEE terminal) without characteristic deterioration and destruction o internal circuit. Figure shows an example o power supply voltage that can be applied to op-amp/comparator with rated power supply voltage 36V. Rated power supply voltage indicates the voltage between Vcc terminal and VEE terminal, and i (Vcc - VEE ) does not exceed rated voltage, no problem is ound in applying such voltage. Thereore, when 24[V] is applied to Vcc terminal and -12[V] to VEE terminal, characteristic deterioration and destruction are not ound. What should be noted is that rated power supply voltage and operational power supply voltage are dierent parameters. Rated power supply voltage reers to a power voltage that can be applied without characteristic deterioration or destruction o IC, and does not mean a power supply voltage or normal operation. Voltage must be set within operational power supply voltage range or operating IC normally. Value o rated power supply voltage and operational power supply voltage depends on a model. They may be equal in some cases, and they may be dierent in other cases. =18[V] = 36[V] =24[V] =-18[V] =GND =-12[V] Split supply ±18[V] Single supply 36[V] Split supply 24[V] -12[V] Fig Applicable supply voltage (In case o rated supply voltage is 36V) 6/27

7 2.2 Rated dierential input voltage It reers to the maximum voltage that can be applied between + input terminal (non-inverting input terminal) and - input terminal (inverting input terminal) without characteristic deterioration and destruction o IC. Polarity o this voltage is determined by whether to apply voltage to - input terminal with reerence to + input terminal, or apply voltage to + input terminal with reerence to - input terminal. Polarity is not o much concern, but what matters is how much voltage can be applied between input terminals. However, it must be assumed that the potential o input terminal is above potential o VEE terminal. Rated dierential input voltage is determined by withstand voltage o transistor connected to input terminal (such as NPN transistor and PNP transistor), etc. Vid + Fig Rated dierential input voltage 2.3 Rated common mode input voltage It reers to the maximum voltage that can be applied without characteristic deterioration or destruction o IC with + input terminal (non-inverting input terminal) and - input terminal (inverting input terminal) set at the same potential. Rated common mode input voltage is dierent rom common mode input voltage range o electric characteristic item. Rated common mode input voltage does not guarantee normal operation o IC. When expecting normal operation o IC, voltage within common mode input voltage range must be ollowed in the electric characteristic items. Rated common mode input voltage is VEE -.3 [V] and Vcc +.3 [V] in general, while the voltage up to power supply rating can be applied to some models. It is determined by protective circuit coniguration o input terminal, withstand voltage o parasitic element and input transistor, etc. - - Vicm + Fig Rated common mode input voltage 7/27

8 2.4 Maximum power dissipation and storage temperature range Maximum power dissipation indicates an power which IC is capable o consuming at an ambient temperature Ta = 25 (normal temperature). IC generates heat when it consumes power, and the temperature o chip becomes higher than ambient temperature. The temperature allowed in a chip is ixed, so that consumable power is limited. Maximum power dissipation is determined by the temperature acceptable by IC chip in a package (junction temperature) and thermal resistance (heat dissipation) o package. The maximum value o junction temperature is normally equal to the maximum value o storage temperature range. Storage temperature range reers to a temperature range where IC can be stored without excessive deterioration o its characteristic. Heat generated by IC, when consuming power is dissipated rom mold resin and lead rame o package. Parameter which shows this heat dissipation actor (hardness o heat to escape) is called thermal resistance, and is represented by θj =a[ /W].Temperature o IC inside the package can be estimated orm this thermal resistance. Figure shows a model o thermal resistance o package. θj-a is represented by the sum o thermal resistance θj-c between chip cases (packages) and thermal resistance θc-a between a case (package) and outside. When thermal resistance θj-a, ambient temperature Ta, and power consumption P are known, chip temperature can be calculated by the equation below: Tj=Ta+θj-a P[W] (2.4.1) Figure shows the thermal relaxing curve (degrading curve). This curve is a graph which shows how much power an IC can consume at some ambient temperature, and indicates power consumed by IC chip without exceeding allowable temperature. Let us consider chip temperature o BA456RF (SOP8 plastic mold package) or an example. Storage temperature range o BA456RF is between -55[ ] and 15[ ], thereore the maximum allowable temperature o a chip is 15[ ].Thermal resistance o SOP8 isθj-a 181.8[ /W]. When assuming that this IC consumes power 687 [mw] at Ta = 25[ ], junction temperature is calculated as ollows: Tj=25[ ]+181.8[ /W].687[W] 15[ ] (2.4.2) Thereore it is seen that the chip reaches its maximum allowable temperature, and no more electric can be consumed. Chip junction-amibient thermal resistance θj-a=θj-c+θc-a[ /W] where θj-c:junction-case(package) thermal resistance θc-a:case(package)-ampient thermal resistance IC chip θc-a θj-c θj-c Power Dissipation Pd [mw] BA4558F(SOP8) BA4558FV(SSOP-B8) BA4558FVM(MSOP8) Lead Frame θc-a Ambient Temperature Ta [ ] Fig Thermal resistance o IC package Fig Power dissipation vs. Ambient temperature (Mounted 7mm 7mm 1.6mm FR4 glass epoxy board) 8/27

9 2.5 Electrostatic discharge tolerance It represents a damage withstand capability against static electricity o IC, and is one o reliability test items. Example o damaging phenomenon when static electricity is applied to IC includes the phenomenon shown below: Dielectric breakdown o ilm oxide : Caused by high electric ield applied to gate ilm oxide when the transistor has MOS structure. Thermal breakdown o PN junction : Excessive current lows in PN junction o device inside IC because o static electricity, which results in thermal breakdown o junction. Melting o wiring : When overcurrent lows in excess o allowable current o wiring, thermal breakdown occurs. Test procedure used oten or evaluating electrostatic discharge tolerance includes a human body model (HBM) and machine model. Human body model is a modeling o phenomenon in which electric charge on human body is discharged when it is in contact with a device, and machine model is a modeling o phenomenon in which electric charge on metallic equipment having greater capacity and smaller discharge resistance than human body is in contact with a device. Figure shows a simple test circuit o human body model and machine model. Capacitance CESD is charged by high voltage, and discharged through resistance RESD or checking or breakdown. Capacitance / Resistance dier between human body model and machine model. For human model For machine model :CESD = 1[pF], RESD = 1.5[kΩ] :CESD = 2[pF], RESD = [Ω] Common terminal in applying static electricity is VEE terminal (GND terminal) and Vcc terminal in general. IC is generally provided with protective circuit against static electricity, and a measure is taken to prevent excessive current rom lowing inside the circuit. When electrostatic surge occurs, in order to dissipate electric charge to common terminal without breakdown o internal circuit, current route with low impedance is reserved. Also, a resistor may be connected to a terminal in series in order to limit the amount o current. Example o protective circuit is shown in igure The protection circuit establish low inpedance current path or ESD. R RESD protection circuit High Voltage SUPPLY CESD DUT ESD applied pin Internal circuit protection circuit HBM : RESD =1.5[kΩ], CESD=1[pF] MM : RESD = [kω], CESD=2[pF] (GND) I surge current is low into internal circuit, it is thermaly destructed. Fig HBM, MM simpliied test circuit Fig Example o internal ESD protection 9/27

10 3.Electrical characteristic o op-amp and comparator Described here are the electric characteristic o op-amp/comparator and eect in actual use by use o an example. 3.1 Circuit current / quiescent current Icc / Iq and power consumption Standard value in speciication indicates an current o op-amp/ comparator alone lowing under no-load, steady state as shown in igure Measuring condition depends on a model. Actually, circuit current also changes because output current depends on load condition. In calculating power consumption o op-amp/comparator, not only the circuit current but also the output current must be considered. How the power consumption is determined is indicated by use o igure (a) and (b). Figure (a) represents a state where the op-amp supplies output source current to the load. Here, the op-amp consumes the current o Icc + Iout. Power consumption is calculated by multiplying the amperage by voltage. The current o Icc and Iout low along dierent routes, and the voltage applied to current route is dierent. Thereore, in calculating power consumption, it is necessary to divide into output current portion and circuit current portion excluding output current. Considering the description above, power consumption can be calculated by the equation below: P=Icc (Vcc-VEE)+Iout (Vcc-) (3.1.1) Figure (b) shows the state where the op-amp supplies the output sink current to the load. Here, power consumption can be calculated by the ollowing equation in the same concept as that in source current supply described above: P=Icc (Vcc-VEE)+Iout (-VEE) (3.1.2) I CC I CC - + (a) Example o supply curretn test circuit or op-amp (b) Example o supply curretn test circuit or comparator Fig Supply current o op-amp and comparator I CC+Iout I CC Iout Iout I CC RL I CC+Iout RL (a) Current path o output source current (b) Current path o output sink current Fig Calculation o power dissipation 1/27

11 3.2 Input oset voltage Vio It indicates the dierence o potential between + input terminal and - input terminal. In other words, it is a voltage required or setting the output at [V]. Maximum input oset voltage is normally guaranteed under a given condition. The guaranteed value itsel is indicated in absolute value. Input oset voltage is generated by voltage dierence between the base and emitter o transistor connected to + input terminal and - input terminal (voltage dierence between gate and source as or FET). It mainly results rom the discrepancy o two transistor characteristics and asymmetry o circuit. This situation is shown in igure (a), and modeling o op-amp including oset voltage is shown in (b). Input oset voltage actually depends on common mode input voltage, power supply voltage, ambient temperature, etc. Change by such use condition can be estimated by electric characteristic such as CMRR, PSRR, and temperature coeicient. Eect o input oset voltage in actual use is considered, taking an example o circuit shown in igure Figure is a non-inverting ampliier with ampliication actor 1 + R2/R1. When we put the input oset voltage Vio, input voltage, and output voltage, the output voltage is given by the equation below: (1+(R2/R1)) (+Vio) (3.2.1) When we look at above equation, it can be seen that not only the input voltage but also the input oset voltage is ampliied. When we put the input oset at 1[mV], it appears as an error o 1[mV] at the output rom non-inversion ampliier with magniication actor 1[mV]. As an example o characteristics o input oset voltage, characteristic o input oset voltage - power supply voltage and characteristic o input oset voltage - temperature are shown in igure Basically, input oset voltage is occurred by base-emitter boltage dierence o Q1 and Q2 (,n+vbe1ーvbe2ー,p)ーvio= Vio=Vbe1-Vbe2 Vbe1,n Q1 Q2 Vbe2 real op-amp R1 Vio R2,p (a) example o op-amp input stage oset voltage Vio ideal op-amp Vio= (b) input oset voltage model the ciucuit equations are ollowing, =a (+Vio-,n) (-,n)/r1=(,n-)/r2 (1+(R2/R1)) (+Vio) Input oset voltage is increased by voltage gain Fig The model o input oset voltage Fig inluence o input oset voltage Input Oset Voltage [mv] ºC 25ºC 125ºC Input Oset Voltage [mv] V 5V 32V Supply Voltage Ambient Temperature Ta [ ] (a) BA294F input oset voltage-supply voltage (b) BA294F input oset voltage-ambient temperature Fig example o input oset voltage characteristic 11/27

12 3.3 Input bias current/input oset current Ib/Iio Input bias current is a current which lows into input terminal or lows out o input terminal. Direction o current depends on the type o transistor connected to input terminal. In the case o bipolar structure in general, direction lowing into input terminal is applied to NPN transistor, and direction lowing out o input terminal is applied to PNP transistor. Input oset current is the dierence o input bias current respectively o + input terminal and - input terminal. When we put the bias current o + input terminal and - input terminal Ib.p and Ib.n, respectively. The input bias current Ib and input oset current Iio are deined by the equation below: Ib =(Ib,p+Ib,n)/2 Iio= Ib,p-Ib,n (3.3.1) (3.3.2) Input terminal o op-amp/comparator is connected to the base o transistor or bipolar structure, and to the gate o transistor or FET structure in order to provide high input resistance. For this reason, the input bias current is either the base current or gate current o transistor, and is in general on the order o na - µa or bipolar structure, and on the order o A - pa or FET structure. Take an example o igure in considering the eect by input bias current and input oset current in actual use. Figure shows a non-inverting ampliier. When we put the input voltage at and output voltage at, the output voltage is calculated by the equation below: =-(R2/R1) -((1+R2/R1) ((R1//R2) Ib,n-R3 Ib,p)) (3.3.3) =-(R2/R1) -(1+R2/R1) ((R1//R2-R3) Ib-(R1//R2+R3) Iio/2) (3.3.4) When we choose R3 so that R3 = R1/R2, the term o error by input bias current can be eliminated. Here, the output voltage is given by the equation below: =-(R2/R1) +(1+R2/R1) ((R1//R2) Iio) (3.3.5) Figure shows an example o temperature characteristics o input bias current and input oset current. R1 R2 Ib,n Ib,n - + Ib,p (a) example o op-amp input stage Ib,n Ib,p (b)input bias current R3 Ib,p The constructed eedback circuit behaves linear circuit. Thereore superposition criterion is consisting. Output error voltage occurred by input bias current and input oset current is ollowing,,p=,n=r3 Ib,p Ib,n=,p/R1+(,p-Eout)/R2 Eout=(1+R2/R1) ((R1//R2) Ib,n R3 Ib,p) =(1+R2/R1) ((R1//R2-R3) Ib-(R1//R2+R3) Iio/2) Fig input bias current Fig inluence o input bias current and input oset current input bias current [na] ±4V ±7.5V ±15V Input Oset Current[nA] ±4V ±7.5V ±15V Ambient Temperature Ta [ ] Ambient Temperature Ta [ ] (a) BA456RF input bias current - ambient temperature (b) BA456RF input oset current - ambient temperature Fig input bias current and input oset current - temperature characteristic 12/27

13 3.4 Common mode input voltage range Vicm / CMR It indicates an input voltage range where the op-amp/comparator operates normally. I any voltage out o common mode input voltage range is applied, desired output voltage cannot be obtained. Common mode input voltage range is determined mainly by coniguration o input step circuit (coniguration o dierential ampliier circuit). Figure shows the input step circuit coniguration o op-amp o BA4558R and BA294. IC op-amp must operate normally within common mode input voltage range, thereore all transistors on input step must operate in linear area. In the circuit shown in igure 3.4.1, the upper limit o common mode input voltage is an input voltage where Q is not saturated, and the lower limit o common mode input voltage is an input voltage where Q1 and Q2 are not saturated. When we put the voltage between base and emitter o each transistor at Vbe, and the voltage between collector and emitter at Vsat where the transistor begins to be saturated, the common mode input voltage range o op-amp o BA4558R and BA294 is as shown below: Common mode input voltage range o op-amp o BA4558R -Vbe2+Vbe5+Vbe6+Vsat2+VEE < Vicm < VCC-Vbe2-Vsat (3.4.1) Common mode input voltage range o op-amp o BA294 -Vbe1'-Vbe1+Vbe3+Vsat1+VEE < Vicm < VCC-Vbe1'-Vbe1-Vsat (3.4.2) When it is assumed that all Vbe equal to Vsat, Common mode input voltage range o op-amp o BA4558R VEE+(Vbe+Vsat) < Vicm < VCC-(Vbe-Vsat) (3.4.3) Common mode input voltage range o op-amp o BA294 VEE+(-Vbe+Vsat) < Vicm < VCC-(2 Vbe-Vsat) (3.4.4) The lower limit o common mode input voltage range o op-amp o BA4558 is determined by the common mode input voltage where Q2 is saturated because the collector potential o Q2 is higher than that o Q1, and Q1 has an input voltage higher than Q2 where they come into saturation region. Op-amp o BA294 uses a level shit circuit (Q1' and Q2') so that it can apply GND potential or input voltage. The circuit is conigured so that the collector potential o Q1 and Q2 is almost equal. Thereore, Q1 and Q2 are saturated at an almost equal input voltage. When we look at the ormula above, the lower limit o common mode input voltage range o op-amp o BA294 is normally higher or Vbe than or Vsat, and it can be seen that VEE potential (GND potential) is included. Op-amp which thus allows input o VEE potential (GND potential) is called a single power supply op-amp. It is impossible to input GND (VEE) potential or input voltage by use o op-amp such as BA4558R, which is designed or both power sources beorehand, but it can be used suiciently by single power source when appropriate input voltage is set. 3 common 同 相 mode 入 力 input voltage 電 圧 範 囲 range Vbe1 - Q1 + Q3 Vsat Q Vbe2 Vsat2 Cc Q2 Q5 Q4 Q6 Vbe5 Vbe6 (a) BA4558RF input stage simpliied schematic Input Oset Voltage [mv] C 25 C 15C Input Voltage [V] (b) BA4558RF input oset voltage - input voltage common 同 相 入 mode 力 input 電 voltage 圧 範 囲 range Vsat Q Vbe1 Vbe2 Vbe1 Vbe2 - Q1 Vsat1 Q2 Q1 Q2 + Q5 Vbe3 Q3 Q4 Q6 Cc Q7 Input Oset Voltage [mv] ºC 25ºC 125ºC (c) BA294F input stage simpliied schematic Input Voltage [V] (d) BA294F input oset voltage - input voltage Fig BA4558RF and BA294F input common mode voltage range 13/27

14 3.5 Maximum output voltage (output voltage range) Vom / Voh, Voi It reers to a voltage range which can be output by op-amp. Voltage is divided into high level output voltage and low level output voltage. Output voltage range is limited by output circuit coniguration, power supply voltage, and load condition (output current). Take an example o op-amp o BA4558R and BA294 shown in igure to see how the maximum output voltage is limited by output circuit coniguration. Figure (a) shows an output equivalent circuit o BA4558R. High level output voltage o this circuit is limited by saturation voltage o Q1, voltage between base and emitter o Q2 and output protection resistor R1. Low level output voltage is limited by saturation voltage o Q4, voltage between base and emitter o Q3, and output protection resistor R2. The smaller the load resistance is and the greater the output current is, the greater is the voltage all because o saturation voltage o each transistor, voltage between the base and emitter, and protection resistance, which makes the output voltage range smaller. Output voltage o BA4558R is determined by the equation below: Voh=Vcc-(Vce1+Vbe2+R1 Isource) (3.5.1) Vol =VEE+(Vce4+Vbe3+R2 Isink) (3.5.2) Isource represents the output source current, and Isink the output sink current. Figure (b) shows the output voltage - load resistance characteristics o BA4558RF. Figure (c) shows an output equivalent circuit o op-amp o BA294. High level output voltage is determined by the voltage between collector and emitter o Q1, voltage between base and emitter o Q2, and voltage between base and emitter o Q3, and voltage all by R1. Low level output voltage depends on the amount o sink current. Fixed current source o 5µA is connected to the output terminal o op-amp o BA294, and the voltage close to GND level can be output until sink current is several ten µa. When sink current exceeds this amperage, Q4 starts to be conductive, so that the low level output voltage is limited by the voltage between collector and emitter o Q5, and voltage between base and emitter o Q4. Output voltage o BA294 is determined by the equation below: Voh=Vcc-(Vsat1+Vbe2+Vbe3+R1 Isource) (3.5.3) Vol =Vce6 (Isink < several ten µa) (3.5.4) =Vce5+Vbe4 (Isink > several ten µa) (3.5.5) Figure (d) shows the characteristic o output voltage - output current o BA294F. Vsat1 Q1 Q RL Vbe2 R1 R2 Vbe3 Isource Isink Maximum output voltage range Output Voltage [V] VOH VOL Q4 Vsat1 Q6 Q3 Vsat4 (a) BA4558RF output stage simpliied schematic Q1 Vbe2 Vsat6 Q2 Vbe4 Vbe3 Q4 R1 Q3 Isource Isink RL Maximum output voltage range Isink Isink> > about 数 十 1μA Load Resistance RL [kω] (b) BA4558RF output voltage vs load resistance ( =15[V], =-15[V], Ta=25[ ]) Output Voltage [V] VOH VOL Vsat5 5μA current source (c) BA294F output stage simpliied schematic Fig BA4558RF, BA294F output voltage range Load Resistance RL [kω] (d) BA294F output voltage vs load resistance ( =5[V], =[V], Ta=25[ ]) 14/27

15 3.6 Common Mode Rejection Ratio (CMRR) It reers to the ratio o luctuation o input oset voltage when input voltage is changed. Standard o speciication reers to the ratio o luctuation o input oset current when DC input voltage is changed. CMRR=ΔVicm/ΔVio (3.6.1) Deinition o CMRR is the ratio between ampliication actor Ad o ampliier with reerence to input voltage dierence and ampliication actor Ac with reerence to common mode input voltage, CMRR = Ad/Ac, which means the same thing as the equation (3.6.1). It is ideal or an op-amp to increase the potential dierence between + input terminal and - input terminal by the ampliication actor provided or the ampliier, while DC operation point inside the circuit is changed by changing common mode input voltage on actual op-amp, thereore the output voltage luctuate slightly. When we put the ampliication actor with reerence to the input dierential voltage o op-amp at Ad, the ampliication actor with reerence to the common mode input voltage at Ac, the potential o + input terminal at.p, and the potential o - input terminal at.n, then the output voltage rom op-amp is represented by the equation below: =Ad (,p-,n)+ac Vic (3.6.2) =Ad ((,p-,n)+(ac/ad) Vic) (3.6.3) Where, Vic is the common mode input voltage, and equals to (.p +.n)/2. The term (Ac/Ad) Vic in the equation above represents an error term by common mode input voltage, and can be considered to be an input oset voltage. Vio,ic=(Ac/Ad) Vic (3.6.4) Fluctuation o input oset voltage with reerence to the change o common mode input voltage is calculated as ollows by this relation: ΔVic/ΔVio,ic=Ad/Ac=CMRR (3.6.5) We understand that this is equal to the ratio between the ampliication actor Ad o input voltage dierence and the ampliication actor o common mode input voltage mentioned above. Let us consider the eect by the change o common mode input voltage in actual use taking an example o non-inversion ampliier in igure When we put the input oset voltage by Vic = [V] on op-amp at Vio., then the input oset voltage Vio.1 by Vic = 1[V] is calculated as ollows: Vio,1=Vio,+1[V]/CMRR (3.6.6) When Vio. = 1[mV] and CMRR = 8[dB], the input oset voltage Vio.1 by Vic = 1[V] is 2[mV]. Thereore, it appears as an error o 2[mV] on the output voltage i non-inverting ampliier with magniication actor 1 is used. Also, CMRR depends on signal requency, and attenuates as the requency becomes the higher. Figure shows an example o input oset voltage - common mode input voltage characteristics and common mode rejection ratio requency characteristics. R1 R2 The inverting input voltage is same as. Thereore, CMR is. Vicm When Vicm changed, Vio ls also changed. Common Mode Rejection Ratio [db] V 2 5V 32V Ambient Temperature Ta [ ] Fig inluence o common mode input voltage Frequency [khz] (b) BA294F CMRR requency response (a) BA294F CMRR vs ambient temperature ( =5[V], =[V], Ta=25[ ]) Fig example o CMRR characteristics CMRR [db] The circuit equetions is ollowing, =a (+Vio-,n) (-,n)/r1=(,n-)/r2 Vio=Vio,+(-V)/CMRR (1+(R2/R1)) (+Vio) input oset voltage is increased by voltage gain. 15/27

16 3.7 Power Supply Rejection Ratio (PSRR) It reers to the ratio o luctuation o input oset voltage when power supply voltage is changed. Standard o speciication indicates the ratio o luctuation o input oset current when DC power supply voltage is changed. PSRR=Δ(Vcc-VEE)/ΔVio (3.7.1) Deinition o PSRR is the ratio between ampliication actor Ad o ampliier with reerence to input voltage dierence and ampliication actor Ap with reerence to power supply voltage, PSRR = Ad/Ap, which means the same thing as the equation (3.7.1). It is ideal or an op-amp to increase the potential dierence between + input terminal and - input terminal by the ampliication actor provided or the ampliier, while DC operation point inside the circuit is changed by changing power supply voltage on actual op-amp, thereore the output voltage luctuate slightly. When we put the ampliication actor with reerence to the input dierential voltage o op-amp at Ad, the ampliication actor with reerence to the power supply voltage at Ap, the potential o + input terminal at +, and the potential o - input terminal at -, then the output voltage rom op-amp is represented by the equation below: =Ad (+--)+Ap Vcc (3.7.2) =Ad ((+--)+(Ap/Ad) Vcc) (3.7.3) The term (Ap/Ad) Vcc in the equation above represents an error term by power supply voltage, and can be considered to be an input oset voltage. Vio,ps=(Ap/Ad) Vcc (3.7.4) Fluctuation o input oset voltage with reerence to the change o power supply voltage is calculated as ollows by this relation: ΔVcc/ΔVio,ps=Ap/Ac=PSRR (3.7.5) We understand that PSRR is equal to the ratio between the ampliication actor Ad o input voltage dierence and the ampliication actor o power supply voltage Ap mentioned above. Let us consider the eect by the change o power supply voltage in actual use taking an example o non-inversion ampliier in igure When we put the input oset voltage by Vcc = 1[V] on op-amp at Vio.1, then the input oset voltage Vio.2 by Vcc = 2[V] is calculated as ollows: Vio,2=Vio,1+1[V]/PSRR (3.7.6) When Vio.1 = 1[mV] and PSRR = 8[dB], the input oset voltage Vio.2 by Vcc = 2[V] is 2[mV]. Thereore, it appears as an error o 2[mV] on the output voltage i non-inverting ampliier with magniication actor 1 is used. In this connection, PSRR attenuates when the requency increases. Thereore the existence o ripple with high requency on power supply line leads to great luctuation o output voltage. This eect can be suppressed by connecting a bypass capacitor near the op-amp. Figure shows an example o input oset voltage - power supply voltage characteristics and power supply rejection ratio characteristics. When supply voltage(vcc or VEE) changed, Vio ls also changed. Fig Supply voltage dependence o input oset voltage Power Supply Rejection Ratio [db] PSRR [db] Ambient Temperature Ta [ ] (a) BA294F PSRR vs ambient temperature Fig example o PSRR characteristics Frequency [khz] (a) BA294F PSRR requecy response 16/27

17 3.8 Large signal voltage gain (large amplitude voltage gain, open loop voltage gain) Av It reers to an ampliication actor with reerence to dierential voltage between + input terminal and - input terminal o op-amp/comparator. The standard shows voltage gain with reerence to DC voltage. High gain is preerable in general because it is desired to make gain error as small as possible generated when eedback circuit is conigured. When we put the output voltage at and input potential dierence at.d, then the voltage gain Av is given by the equation below: Av=/,d (3.8.1) Take an example o circuit in igure to consider the gain error. This igure shows a non-inverting ampliying circuit, and output voltage is calculated as ollows: =(1+R2/R1) (1/(1+(1+R2/R1)/Av)) (3.8.2) When we put R1 = 1 [kω], R2 = 1[kΩ], and Av = 8dB, this value is calculated as ollows: =1.988 (3.8.3) It is smaller than the ideal ampliication actor 11. Voltage gain depends on requency, and attenuates as the input signal requency becomes the higher. Thereore, the greater the requency is, the greater is the gain error. Figure shows an example o voltage gain temperature characteristics and voltage gain requency characteristics. R1 R Av Voltage Gain [V/V] circuit equation is ollowing, =Av (,p-,n) (-,n)/r1=(,n-)/r2 =(1+R2/R1) (1/(1+(1+R2/R1)/Av)) Large Signal Voltage Gain [db] (a) inverting ampliier (b) dependence o open loop voltage gain or 2dB inverting ampliier Fig inluence o open loop voltage gain Large Signal Voltage Gain [db] 1 5 5V 15V Ambient Temperature Ta [ ] 15 (a) BA294F large signal voltage gain vs ambient temperature (RL=2 [kω]) PSRR [db] dB non-inverting amp open loop voltage gain Frequency [khz] (b) BA294F large signal voltage gain requency response ( =5[V], RL=2[kΩ]) Fig example o large signal voltage gain characteristics 17/27

18 3.9 Slew Rate (SR) It is a parameter which reers to the operation speed o op-amp. It reers to at what rate o time the output voltage rises or alls when square wave pulse is applied to the input. Figure shows the waveorm o input/output voltage. Slew rate makes it possible to estimate what degree o requency signal can be applied. Figure shows the waveorm o output voltage when the sine wave is applied to op amp. When we put the output voltage at (t), amplitude at A, and signal requency at, then (t) can be calculated by the equation below: (t)=a sin(2π t) (3.9.1) When it is dierentiated by t, d(t)/dt=2π A sin(2π t) (3.9.2) The time t when this slope becomes the maximum is when the sine wave reaches the intermediate potential, which is shown by the equation below: d(t)/dt max=2π A (3.9.3) In order that a signal is output without restriction by slew rate, the maximum inclination in the equation above must be smaller than slew rate. SR > 2π A (3.9.4) For example, when you want to make the op-amp with slew rate 1. [V/µs] output a sine wave with amplitude 5[Vp-p], acceptable signal requency is limited to the requency which satisies the equation below: <SR / ( 2 π A ) = 1.[V/µs] / 2 π 5[Vp-p] = 31.83[kHz] (3.9.5) input voltage t output voltage ΔV Δtr Δt t Rising slew rate SR+ = ΔV / Δtr alling slew rate SR- = ΔV / Δt normally measurement voltage range is 1% to 9% o maximum voltage swing Fig slew rate input voltage A 1 t -A 2 output voltage A 1 t Slope o midium voltage:d/dt=2πa Output voltage is limited by slew rate. Output voltage waveorm is distorted that d/dt value is over slew rate. -A 2 Fig input and output waveorm applied sine wave 18/27

19 3.1 Response time tre / tphl / tplh It is a parameter which shows in what time period a pulse is output when square wave pulse is applied to a comparator. It is normally measured by the time period when a voltage reaches 5% o output voltage amplitude, starting rom reerence voltage. Figure shows the input/output waveorm o comparator and op-amp. Rising time and alling time o output waveorm rom op-amp containing phase compensation capacitance are limited by slew rate. Slew rate is determined by the time to charge/discharge the phase compensation capacitance. Comparator has no phase compensation capacitance, and responses in rising time and alling time is earlier than op-amp. In evaluating the response time o comparator, the potential dierence between reerence voltage and signal level, called overdrive, is changed in evaluation. Here, response time is measured by the time period rom reerence voltage up to 5% o output amplitude. It is also possible that the response time is measured by applying an input signal o TTL level (3.5 [Vp-p]). Comparator o BA1393 and BA1339 etc, is an output circuit o open collector type. In this output type, rising time becomes shorter because the output NPN transistor drives the load directly. Rising time is limited by external pull-up resistor, load capacitance (contain parasitic capacitance). overdrive voltage V REF overdrive voltage V REF V REF V RL RL V OH V OL response time tphl 5% o amplitude V OH V OL response time tplh 5% o amplitude output voltage o comparator output voltage o op-amp output voltage o comparator Fig response time o op-amp and comparator output voltage o op-amp 6 6 Output Voltage [V] Input Voltage [1-1 V] input voltage overdrive 5[mV] 2[mV] 1[mV] Output Voltage [V] Input Voltage [1-1 V] overdrive 5[mV] 2[mV] 1[mV] input voltage time [us] time [us] 6 5 (a) alling time (b) rising time Fig BA293F response time (pull-up resistor 5.1[kΩ], Vcc=5V) 6 5 Output Voltage [V] Input Voltage [1-1 V] output voltage input voltage Output Voltage [V] Input Voltage [1-1 V] output voltage input voltage time [us] time [us] (a) alling time (b) rising time Fig BA294F response time (load resistance 1[kΩ], Vcc=5V, 1mV overdrive) 19/27

20 3.11 Open loop voltage gain requency characteristics and unity gain requency/gain bandwidth product Figure shows the open loop voltage gain requency characteristics. Op-amp can be considered to be an integrator, and has a high voltage gain by DC, while reduces the gain as the signal requency becomes the higher. Important parameters o requency characteristics are phase margin, gain margin and unity gain requency. Phase margin φm is a parameter which shows how much margin a phase has with reerence to 18 degrees when the gain is unity. Gain margin GM shows how small the gain is with reerence to unity when the phase is delayed 18 degrees. Unity gain requency t is a requency when the gain is 1. When we put the voltage gain requency characteristics o op-amp at a(), phase margin φm and gain margin GM are represented by the equation below: φm=18 - a(t) (3.11.1) GM=2 log (1 / a( -18 ) ) (3.11.2) Terms or estimating unity gain requency include a parameter called gain bandwidth product (GBW). Gain bandwidth product is a parameter or estimating t assuming that the op-amp is a simple irst order integrator. With use o this assumption, the voltage gain requency characteristics o op-amp are represented by the equation below: a()=a / (1+j( / -3dB ) ) (3.11.3) "ao" is a voltage gain with reerence to DC voltage. (Same as the large signal voltage gain Av in section 3.9) The magnitude o a() is given by the equation below: a() =a / ( 1+( / -3dB ) 2 ) 1/2 (3.11.4) In the equation above, the requency which satisies >> -3dB and the magnitude o voltage gain when = t are shown respectively by the equation below: >> -3dB a() a / ( / -3dB ) a() =a -3dB (3.11.5) =t a(t) a / ( t / -3dB )=1 t=a -3dB (3.11.6) The relation below is established by the two equations above. a() =t (3.11.7) This relation means that the product o gain and requency can always be approximate to t in a requency range which satisies >> -3dB. 2 log a() a Product o gain and requency is constant value (gain bandwidth product) a() =t ( is satisied >> -3dB) -3dB t GM a() φm Fig open loop voltage gain (large signal voltage gain) requency response 2/27

21 3.12 Model o negative eedback system and oscillation condition Op-amp is seldom used alone, but is used in coniguration o negative eedback circuit. One o things that should be noted in coniguration o eedback circuit is the stability. Here, the stability o eedback circuit is described in the main Model o negative eedback system and oscillation condition Model o negative eedback system is shown in igure Transer unction between input and output is calculated by use o this model. "a()" is the ampliication actor o ampliier, and β() is a eedback actor determined by eedback circuit. Transer unction A() between input and output is calculated by the equation below: A()=/=a() / (1+β() a()) (3.12.1) =a() (1+T())-1 (3.12.2) =(1 / β()) (1+1 / T())-1 (3.12.3) T() =β() a() is a parameter called loop gain, and is determined by the product o ampliication actor and eedback actor o ampliier. As can be seen rom the equation (3.12.2), as long as the loop gain is great, the gain o system in general (transmission unction) is 1/β().When the phase o T() rotates 18 degrees and the magnitude is 1, then / = in the equation (3.12.1), and V is output even when input is zero. It means oscillation. In order to make negative eedback circuit stable, beore the phase o loop gain rotates 18 degrees, its magnitude must be attenuated below 1. Stable condition is shown in the equation below: Stable condition o negative eedback system T() < 1, T()=18 (3.12.4) Figure shows an example o requency characteristics o loop gain. Indicator or determining the stability o negative eedback system includes phase margin φm and gain margin GM. φm=18 - T(x) (3.12.5) GM=2 log (1 / T(-18 ) ) (3.12.6) - a() 2 log T() T β() -3dB x GM Negative eedback system is constructed bellow relationship a() (-β() )= transer unction A() is A()=/=a()/(1+a() β()) =a()/(1+t()) =(1/β()) (1+1/T()) -1 where T()=a() β() is loop gain I loop gain is satisied T() >> 1, transer unction is A() 1/β() T() φm (a) Model o negative eedback system (b) Loop gain requency response Fig Negative eedback system model and loop gain requency response 21/27

22 Stability o non-inverting ampliier and dierentialor Take an example o non-inverting ampliier and dierentiator to consider stability. Feedback actor o non-inversion ampliier is determined by resistance, and does not depend on requency. Flow o signal in eedback circuit is in the direction rom output to input, thereore the eedback actor, loop gain, and transer unction are represented by the equation below: β=- / =R1 /(R1+R2) (3.12.7) T()=a() β=(a / (1+j ( / -3dB )) (R1/(R1+R2)) (3.12.8) A()=(1 / β) (1+1 / T()) -1 (3.12.9) Gain a() o op-amp alone and 1/β are shown in the bode plot in igure On this bode plot, T() is a dierence between a() and 1/β. (2 log a() -2 log 1/β =2 log a() β =2 log T() ) The smaller β is (eedback amount smaller), the less is the delay o phase when T() = 1. The greater β is (eedback amount greater), the poorer is the stability. Whenβ=1, the smallest is the phase margin. β=1 (R1 =, R2 = ) when voltage ollower is conigured, and stability o op-amp alone is required. Op-amp containing phase compensation capacitor in general is designed not to oscillate when voltage ollower is conigured. Figure shows a dierentiator (high pass ilter). In dierentiator, eedback circuit contains capacitor, which delays the phase o loop gain. Stability can be improved by connecting a resistor in series to the capacitor. Feedback actor, loop gain, and transer unction are represented by the equation below: β()=-/=(1+j 2π C1Rs)/(1+j 2π C1(R1+Rs)) (3.12.1) T()=a() β()=(a/(1+j ( / -3dB)) (1+j 2π C1Rs/(1+j 2π C1(R1+Rs))) ( ) A()=-(j 2π C1R1/(1+j 2π C1Rs)) (1+1/T()) -1 ( ) Here, it should be noted that the transer unction in DC does not ollow 1/β() when inverting ampliier is conigured, but equals to - (R1/Rs + 1/(j 2π C1)). In a dierentiator, it can be seen that the phase o loop gain advances and stability improves when Rs is connected to C1 in series. R1 R2 Rs C1 R1 a a() a a() T() =1 not insertion o Rs 1/β 1+R2/R1 T() T() =1 T() insertion o Rs -3dB t 1/β t T() φm=9 x= t /(1+R2/R1) z=1/2πc1 (R1+Rs) T() p=1/2πcrs x = t /(1+R1/Rs) insertion o Rs not insertion o Rs φm a a() a a() 1+R2/R1 A() not insertion o Rs A() t insertion o Rs t x= t /(1+R2/R1) Fig loop gain requency response o non-inverting amp Fig loop gain requency response o dierntiator 22/27

23 3.13 Total Harmonic Distortion plus Noise (THD + N) I shows how much harmonic component and noise component are contained in output signal. THD + N = (Sum o harmonic component and noise component) / (Output voltage) Harmonics is generated by nonlinearity o op-amp circuit. It results rom the act that the current - voltage static characteristic o transistor is exponential unction (or bipolar transistor), and ampliication actor is a nonlinear unction with reerence to input voltage, etc. Noise is generated not only by disturbance but also by peripheral components such as semiconductor element within IC and resistor. Output rom op-amp contains theses components, which distort the waveorm. When an ampliier is conigured with op-amp, not only input signal but also noise component is ampliied. Thereore, when a circuit with great ampliication actor is conigured, distortion actor becomes greater i output signal level is small. Figure (a) shows an example o output amplitude - requency characteristics using the gain as a parameter. Output signal is limited by the slew rate o op-amp. Thereore, when a signal has a great requency or when output signal has a great amplitude, distortion actor becomes great. Figure (b) shows a distortion actor characteristic using the signal requency as a parameter. R1 R2 =1kHz =1kHz output voltage spectrum basic signal(desired output signal) output voltage spectrum basic signal(desired output signal) harmonis components noise voltage harmonis components noise voltage is also ampliied by voltage gain. (a) Output voltage spectrum (b) Output voltage spectrum under voltage ollower constructed under non-inverting anp constructed Fig Image o THD+N 1.1 Av=dB Av=1dB Av=2dB 1.1 2Hz 1kHz 2kHz THD+N [%].1 THD+N [%] Output Voltage [Vrms] Output Voltage [Vrms] THD+N is relatively large value due to small input signal level THD is increased due to slew rate. (a) THD+N dependence o voltage gain (=1kHz) (b) THD+N dependence o signal requency (Av=2dB) Fig BA4558R THD + N vs. output voltage (V+=15V,V-=-15V,RL=1kΩ,DIN AUDIO FILTER) 23/27

24 In addition, it is possible that the distortion actor becomes extremely high depending on output circuit coniguration and load condition. Figure shows the output circuit and distortion actor o op-amp o BA4558R and BA294. BA4558R has an output circuit coniguration called push-pull circuit o class AB. In this output circuit coniguration, idling current is always allowed to low in the output transistor to turn it on, which suppresses crossover distortion generated when source current and sink current are switched. BA294 type has an output coniguration called push-pull circuit o class C, and perorms operation o class A when output sink current is small. When sink current exceeds several ten µa, great current PNP transistor Q4 turns on and crossover distortion is generated. Especially, when it is used by split power supplies, care should be taken because intake current may become great. This crossover distortion can be suppressed by always turning on PNPTr by use o pull-up resistor or by restricting intake current within several tenµ A. Q4 Q1 R1 R2 Q2 Q3 RL Class AB output stage. Due to Q2, Q3 is always ON state, cross over distortion is suppressed. t THD+N [%] Output Voltage [Vrms] (a) BA4558RF output stage (b) BA4558RF THD+N vs output voltage ( =15[V], =-15[V], RL=1[kΩ], signal requency 1[kHz], 2[Hz]~2[kHz]LPF ) Fig BA4558RF output stage and THD+N cross over distortion caused by switching o Q3 ans Q4. Q4 is ON state, when output sink current over about 1μA. THD is increased by discontinuous waveorm (harmonic component). 1 THD is increased by cross over distortion. Q1 Q5 Q2 R1 5μA Q3 Q4 Isource Rp RL (a) BA294F output stage I Q4 is always ON state with pull-up resistorrp or insertion pull down resistor RL tovee cross over distortion is suppressed. t THD+N [%] t RL=1kΩ RL=1kΩ pull dow n to VEE Rp=3kΩpull up resistor Output Voltage [Vrms] Cross over distiortion is suppressed by insertion o pull up resister or pull down resistor to VEE. (b) BA294F THD+N-output voltage ( =15[V], =-15[V], RL=1[kΩ], signal requency1[khz], 2[Hz]~2[kHz]LPF ) Fig BA294F output stage and THD+N 24/27

25 3.14 Equivalent input noise source (input reerred noise source) Output noise rom op-amp is converted into input noise voltage source, which makes an equivalent input noise source. equivalent input noise source is divided into input equivalent input noise voltage and equivalent input noise current. Noise contains a wide range o requency component, and is normally represented by requency spectrum. Noise is generated not only by disturbance, but also by chronologically discontinuous movement o electron. Noise generated by resistor and semiconductor element is mainly thermal noise, shot noise, and licker noise (1/ noise). Principal mechanism by which noise is generated includes the ollowing: Thermal noise Shot noise Flicker noise : Thermal random movement o electron in resistor. Distributed in a wide range o requency area (white noise). Noise generated in resistor o resistance R is Vnr2/Δ = 4kTR, Inr2/Δ = 4kT/R. : Noise observed in active element, which is caused by electron passing depletion layer discontinuously (chronologically). It is ound in orward current o diode, etc. Distributed in a wide range o requency area (white noise). When we put DC current lowing in active element at I, In2/Δ = 2qI is established. : Noise observed in active element, which is caused when trap generated by crystal deect captures and emits electron at random. Noise distributed in low-requency area. It is also called 1/ noise because noise power density is inversely proportional to requency. It is considered to be caused by crystal deect between base and emitter o bipolar transistor. When we put DC current lowing in element at I (base current as or bipolar transistor), In2 / Δ = k Ia / is established. Where, k: Boltzmann constant, T: absolute temperature, K and a: constant determined by process, and Δ: requency range which is interested in. Op-amp consists o passive element such as resistor and active element such as transistor, and emits noise. The model o op-amp including equivalent input noise source is shown in igure Noise has no polarity, and input noise source must be considered on both + input voltage and - input voltage. Considering that op-amp ampliies the dierence between + input voltage and - input voltage, input conversion noise voltage can be collected either on + input terminal or - input terminal. Normally, equivalent input noise voltage is considered on + input terminal side. Consider the processing input terminal or the reason or considering both noise voltage and noise current. Noise appears on output even when input terminal is shorted or opened with no input signal applied to op-amp. When input terminal is shorted, input noise current source can be ignored, so that output noise is generated rom input noise voltage source. When high resistance is connected to the input terminal, the input noise current source generates a great voltage all and is ampliied and output, so that output noise is dominantly aected by input noise current source. Equivalent input noise source Vn,n In,n In,p Vn,p Noiseless opamp (a)output noise voltage o op-amp (b) Model o equivalent input noise source Vn, In licker noise distributed over low requency region In,n In,p thermal noise, shot noise distributed over wide bandwidth Vn=Vn,p+Vn,n (c) Model o equivalent input noise source ( voltage noise contains both non-inverting input and inverting input one.) (d)frequency spectrum o noise source Fig Noise sauce model o op-amp 25/27

26 Consider the output noise voltage on non-inverting ampliier in igure Put the thermal noise generated rom resistor R1, R2, and R3 respectively at In1, In2, and In3. It is impossible to superimpose voltage and amperage on noise, but it is possible to superimpose by power. When we convert all noise sources as equivalent input noise voltage source Vnt, it is as ollows: Vnt 2 =Vni 2 +R3 2 (In3 2 +Inp 2 )+(R1 // R2) 2 (Inn 2 +In1 2 +In2 2 ) (3.13.1) =Vni 2 +R3 2 Inp 2 +(R1 // R2) 2 Inn 2 +4kT {R3+(R1 // R2)} (3.13.2) =Vni 2 +{R3 2 +(R1 // R2) 2 } In 2 +4kT {R3+(R1 // R2)}(assuming Inp=Inn) (3.13.3) where, Vni 2 =Vnw 2 (cv/+1) In 2 =Inw 2 (ci/+1) Boltzmann s constant k cv ci is the corner requency o noise voltage and noise current, respectively. (Fig (c)) The voltage gain o non-inverting ampliier is represented A(), output noise voltage is ollowing, Vno={ A() 2 Vnt2 d }1/2 I non-inverting ampliier is assumed one order integrator, that is A()=A / ( 1+j / a ), output voltage noise within requency bandwidth L to H is approximated bellow equation. Vno=(1+R2/R1) {Vnw 2 (cv log(a/l)+1.57a-l)+(r32+(r1//r2)2) In 2 (cv log(a/l)+1.57a-l) +4kT (R3+(R1//R2)) (1.57A-L) } 1/2 (3.13.4) Fig (a), (b) is speciied equivalent input noise voltage characteristics examples. In1 In2 R1 R2 R1 R2 Inn Vno In3 R3 Inp Vni R3 Vni (a) noise source o non-inverting ampliier (b) equivalent input noise voltage o (a) Vn 2 4kT {R3+(R1//R2)} Noise voltage caused by resistor R1,R2,R3 Vn 2 Output noise voltage is limited op-amp requency response. Thereore, high requecy compornent o noise voltage is rejected. output noise voltage Vno 2 Vni 2 licker noise Vnw 2 (cv/+1) In 2 licker noise Inw 2 (cv/+1) A 2 Vnw 2 Inw 2 cv ci Equivalent input noise voltage o op-amp Equivalent input current voltage o op-amp (c) compornent o equivalent input noise L equivalnet input noise voltage Vnt 2 voltage gain o ampliier A() 2 (d) ouput noise voltage H Fig noise eect or non-inverting ampliier 26/27

27 Input Reerred Noise Voltage (nv/ Hz) Frequency [Hz] (a) BA4558R equivalent input noise voltage vs. requency ( =15V, =-15V, 2dB non-inverting amp) Input Reerred Noise Voltage Vn [μvrms] Input Signal Source Resistor [Ω] (b) BA4558R equivalent input noise voltage vs. signal source resistance ( =15V, =-15V,2dBnon-inverting amp, 2Hz~2kHzLPF) Fig Example o equivalent input noise spectrum 27/27

28 Notice Notes No copying or reproduction o this document, in part or in whole, is permitted without the consent o ROHM Co.,Ltd. The content speciied herein is subject to change or improvement without notice. The content speciied herein is or the purpose o introducing ROHM's products (hereinater "Products"). I you wish to use any such Product, please be sure to reer to the speciications, which can be obtained rom ROHM upon request. Examples o application circuits, circuit constants and any other inormation contained herein illustrate the standard usage and operations o the Products. The peripheral conditions must be taken into account when designing circuits or mass production. Great care was taken in ensuring the accuracy o the inormation speciied in this document. However, should you incur any damage arising rom any inaccuracy or misprint o such inormation, ROHM shall bear no responsibility or such damage. The technical inormation speciied herein is intended only to show the typical unctions o and examples o application circuits or the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever or any dispute arising rom the use o such technical inormation. The Products speciied in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, oice-automation equipment, communication devices, electronic appliances and amusement devices). The Products speciied in this document are not designed to be radiation tolerant. While ROHM always makes eorts to enhance the quality and reliability o its Products, a Product may ail or malunction or a variety o reasons. Please be sure to implement in your equipment using the Products saety measures to guard against the possibility o physical injury, ire or any other damage caused in the event o the ailure o any Product, such as derating, redundancy, ire control and ail-sae designs. ROHM shall bear no responsibility whatsoever or your use o any Product outside o the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manuactured to be used with any equipment, device or system which requires an extremely high level o reliability the ailure or malunction o which may result in a direct threat to human lie or create a risk o human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, uelcontroller or other saety device). ROHM shall bear no responsibility in any way or use o any o the Products or the above special purposes. I a Product is intended to be used or any such special purpose, please contact a ROHM sales representative beore purchasing. I you intend to export or ship overseas any Product or technology speciied herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you or your accessing to ROHM product inormations. More detail product inormations and catalogs are available, please contact us. ROHM Customer Support System R112A