EE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces

Transcription

1 EE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces Lecture 20 Case Studies Ethernet Borivoje Nikolić April 1, Class Material Posted some background material on the web site For now Ethernet, will fill in the past topics 2

2 Outline History of Ethernet 3 History of Ethernet Mb/s prototype in Xerox PARC Xerox X-Wire, by R. Metcalfe Used in Xerox Alto (first networked workstation) R. M. Metcalfe, D. R. Boggs, "Ethernet: distributed packet switching for local computer networks," Communications of the ACM, July IEEE 802 Project formed (LAN) IEEE Ethernet LANs Mb/s Ethernet over thick coax (10Base5) Yellow garden hose bus structure ( Thicknet ) 1985 Thin wire coax (10Base2) Cheapernet, Thinnet 4

3 History of Ethernet Base-T approved Ethernet-over-twisted-pair, star (dedicated wire) configuration Quickly dominated the market Base-T Fast Etgernet, 100Mb/s Base-X optical Gb/s Ethernet There existed 10Base-F before Base-T Gb-Ethernet over copper (UTP) 2004 (expected) 10GBase-T over UTP 5 History of Ethernet Ethernet was neither the first nor the only networking standard Token Ring (802.5) co-existed for a long time Primarily used by IBM So did Token Bus (802.4) Ethernet is lower cost In parallel, there was the development of bridges, hubs, switches, routers, 6

4 Where do the Names Come From? n-signal-phy n data-rate (1, 10, 100, 1000, 10G) signal {BASE, BROAD} BASE baseband systems BROAD broadband, modulated (not really used) phy physical medium Used to be the length of the medium (in 100 s of m) 1Base5, 10Base5 500m long, 10Base2 185m Now is the code of the medium T - UTP 7 100Base-T 100Base-T generic designation for 100Mb/s Ethernet 100Base-TX - 2 pairs of Cat-5 UTP up to 100m, 4b/5b encoding 100Base-T2 2 pairs of Cat-3 UTP up to 100m 100Base-T4 4 pairs of Cat-3 UTP up to 100m 100Base-FX 2 multimode fibers, up to 2km, 4b/5b encoding First implementations of 100Base-TX, 100Base-FX were multi-chip, then became single chips, then multiple ports on a single chip, then negligible, 8

5 10/100Base-T Transceivers Everitt, JSSC 12/ /100Base-T Transceivers Transmitter Receiver 10

6 MLT Waveform 0 no transition; 1 - transition 4/5 code rate 25% overhead 8ns (125MHz signaling) 11 Receiver Block Diagram Loss is and 100m UTP5 Magnetic coupling: Signal is low-pass filetred 12

7 Slicers 13 Wander and Gain Control 14

8 100Base-T Equalizer 15 Equalization 20m 100m 16

9 Gigabit Ethernet standard Media Access Control (MAC) Full-duplex / Half Duplex Gigabit Media Independent Interface (GMII) MAC PHY 1000BASE-X 8b/10b Encode / Decoder 1000BASE-T Encode / Decoder 1000BASE-CX Transceiver 1000BASE-FX Transceiver 1000BASE-LX Transceiver 1000BASE-SX Transceiver 1000BASE-T Transceiver 802.3z 802.3ab From K. Azadet, VLSI-TSA Distance Targets Fiber PHY : SX : 850nm multi-mode62.5um 275m 50um 500m LX : 1300nm multi-mode62.5um 550m 50um 550m FX : 1300nm single-mode (9um) 5km Short Haul : CX : specialized STP (Twinax) 30m Long Haul copper : T : UTP CAT-5 100m From K. Azadet, VLSI-TSA

10 Gigabit Ethernet network architecture DTE T CSMA/CD DTE T DTE T Repeater (half-duplex) 1000BASE-SX 1000BASE-CX DTE T T Switch (full-duplex) DTE T T DTE DTE CSMA/CD : Carrier Sense Multiple Access / with Collision Detection DTE : Data Terminal Equipment T : 100BASE-TX or 1000BASE-T : office environment : offices : computer room or closet DTE T Switch (full-duplex) T DTE T DTE From K. Azadet, VLSI-TSA Base-T Channel 100Base-Tx : 100 Mb/s full-duplex over 2 pairs UTP-5, 100m Tx Rx 125Mb/s NEXT 125Mb/s Rx Tx 1000Base-T : 1000 Mb/s full-duplex over 4 pairs UTP-5, 100m Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx hybrid Echo NEXT 250Mb/s FEXT hybrid Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx 20

11 UTP CAT-5 Cable CAT-5 cable is specified in ISO/IEC and EIA/TIA 568-A, up to 100MHz Echo Channel Attenuation NEXT 21 UTP CAT-6 cable CAT-5 attenuation CAT-5 NEXT CAT-6 attenuation CAT-6 NEXT 22

12 Modulation Baseband modulation 5-level PAM Pulse shaping filter: z -1 Rise-Fall time: 3-5ns Baud-rate = 125MHz 125MBaud x 2bit/symbol = 250Mb/s (1Gb/s over 4 pairs) PAM-5 carries 2bit + redundancy Four PAM-5 symbols represent a 4D lattice of 625 points = 8bit data + 1bit parity (TCM) + extra overhead for control From K. Azadet, VLSI-TSA Modulation Baseband modulation 5-level PAM Pulse shaping filter: z -1 Rise-Fall time: 3-5ns Receive signal after 100m CAT-6 cable Receive signal after analog equalization (no echo) 24

13 1000BASE-T Encoder/Decoder 4-D PAM5 Transmit GMII Receive scrambling De-scrambling TCM + bit to symbol mapping Viterbi + symbol to bit mapping Front-end analog and digital signal processing UTP cable (4 pairs) GMII: Gigabit Media Independent Interface (8bit) 25 Reference implementation (for one pair) Analog Digital 3 NEXT Cancellers From other transmitters From other receivers Analog Frontend T&H A/D FIFO FFE + Combined DFE/TCM decoder UTP Hybrid 25M 125M DPLL 125M Timing recovery Echo Canceller Physical Control Sublayer (PCS) GMII D/A Pulse shaping z -1 26

14 Design example A/D: 8bit, 125MS/s D/A: 8bit linearity, 125MS/s FFE taps: 8 DFE taps: 14 NEXT taps: 80 Echo taps: 60 Simulated SNR: 27.7dB Total Echo/NEXT taps per transceiver: 1200 taps (125MHz)!! M.Hatamian et al. : Design Considerations for Gigabit Ethernet 1000BASE-T Twisted Pair Transceivers, CICC Trellis Encoder GMII Tx_D[0] Tx_D[1] Tx_D[2] Tx_D[3] Tx_D[4] Tx_D[5] Tx_D[6] Tx_D[7] SD[0] SD[1] SD[2] SD[3] SD[4] SD[5] SD[6] SD[7] D = delay D + D + D Parity SD[8] Convolutional encoding to convert scrambled octet data into 9bit word Bit two signal mapping by set partitioning 28

15 Subset Mapping Y X Y X Y Subset X-Primary Symbol Y-Primary Symbol Total No. of Points No. of used points D0 XXXX YYYY D1 XXXY YYYX D2 XXYY YYXX D3 XXYX YYXY D4 XYYX YXXY D5 XYYY YXXX D6 XYXY YXYX D7 XYXX YXYY PAM 5 levels partitioned into two 1D subsets: X={-1,+1}, Y={-2,0,+2} Eight 4D subsets are obtained by grouping combinations of the four 1D subsets together Squared distance between points in a 4D subset >=4 Squared distance between even 4D subsets >=2 Squared distance between odd 4D subsets >=2 29 4D 8-State Trellis Diagram D 0 D 2 D 4 D 6 D 1 D 3 D 5 D 7 D 2 D 0 D 6 D 4 D 3 D 1 D 7 D 5 D 4 D 6 D 0 D 2 D 5 D 7 D 1 D 3 D 6 D 4 D 2 D 0 D 7 D 5 D 3 D 1 D 0 D 2 D 4 D 6 D 2 D 0 D 6 D 4 D 4 D 6 D 0 D 2 D 6 D 4 D 2 D 0 D 1 D 3 D 5 D 7 D 3 D 1 D 7 D 5 D 5 D 7 D 1 D 3 D 7 D 5 D 3 D 1 4D 8-State trellis coded modulation technique by Ungerboeck Minimum squared distance between valid sequences: 4 Gain due to MLSE: 6dB. 30

16 TCM coding gain d 2 =2 d 2 =2 d min 2 = 4 Minimum squared distance between valid sequences: 4 Gain (compared to uncoded PAM-5) due to MLSE: 6dB. 31 BER Performance: Gaussian Channel packet error rate uncoded DFE + VD DFP + 1 tap PDFD L tap PDFD SNR (db) Concatenation of DFE + Viterbi: coding gain ~ 1dB instead of 6dB!! 32

17 Joint Equalization and FEC Digitized signal FFE + 8-Path Viterbi Decoder Received data DFE #1 DFE #8 8 parallel DFE s (8 states) Each state has its own DFE DFE inputs use survivor paths 33 Implementation of 14-tap PDFD in 0.25µm Complexity (Gates) Critical path (ns) DFU (51%) 3.52 (25%) 1D-BMU (18%) 4.34 (31%) 4D-BMU (8%) 1.71 (12%) ACSU (10%) 2.63 (19%) SMU (13%) 1.77 (13%) TOTAL

18 Complexity reduction by prefilter postcursors tail removal 1 postcursor 4 soft inputs 4 Decision-feedback prefilter 4 1-tap PDFD bits 35 Decision-feedback prefilter From FFE -f 2 -f 3 -f 14 -f 1 To 1-tap PDFD 36

19 BER performance with prefilter BLER uncoded U=0 (DFETCM) U=1 U=2 U=10 (full PDFE) SNR (db) 37 Conventional DFE: critical path D 7 D 6 D 5 D 4 D 3 D 2 D 1 + y(n) Critical path details: t MAC + t CPA + t slicer < t clk Example in 0.25um CMOS: Total = 1.6ns + 2.8ns + 1.6ns = 6ns (assumes the transposed form implementation, which reduces the critical path to one multiply-accumulate) 38

20 Look-ahead DFE D 7 D 6 D 5 D 4 D 3 D 2 2D 1 + D D1 MUX y(n) + -2D 1 + Critical path details: t CPA + t MUX + t slicer < t clk 2.8ns + 0.7ns + 1.6ns = 5.1ns 39 Block processing + look-ahead DFE A/D out F 7 F 5 F 3 F 1 y(2n-2) D 7 D 5 D 3 D y(2n-1) F 6 F 4 F 2 F 0 F 7 F 5 F 3 F 1 D 8 D 6 D 4 D 2 y(2n-3) y(2n-2) D 8 D 6 D 4 D D 1 + D1 + -D1 MUX y(2n) F 6 F 4 F 2 F 0 0 D 7 D 5 D 3 y(2n-3) FFE DFE + -2D 1 + Critical path details: t MAC + t CPA + t MUX + t slicer < 2 t clk 1.6ns + 2.8ns + 0.7ns + 1.6ns = 6.7ns 40

21 PDFD critical path Viterbi trellis decoder: 4 soft inputs 1D-BMU 4x2= 8 1D-BMs 8 4D-BMs 4D-BMU ACSU SMU bits 14-tap PDFD: 8x4=32 soft decision-feedbacks DFU 8x4x14= 448 symbols 4 soft inputs 1D-BMU 8x4x2= 64 1D-BMs 4D-BMU 8x4= 32 4D-BMs ACSU SMU bits 41 Look-ahead 1-tap PDFD Calculation of 1D-BMs outside critical loop 8x4=32 symbols 4 1D LABMU 4x2x5= 40 1D-BMs MUXU 8x4x2= 64 1D-BMs 4D-BMU 8x4= 32 4D-BMs ACSU SMU bits 42

22 Look-ahead computation of 1D branch metrics For a single dimension: z n 2f 1 f 1 f 1 2f 1 A B A B A B A B A B SQR SQR SQR SQR SQR SQR SQR SQR SQR SQR 1D-BM(A,-2) 1D-BM(B,-2) 1D-BM(A,-1) 1D-BM(B,-1) 1D-BM(A,0) 1D-BM(B,0) 1D-BM(A,1) 1D-BM(B,1) 1D-BM(A,2) 1D-BM(B,2) In total 40 1D-BMs 43 Selection of 1D branch metrics For state 0 and a single dimension: 1D-BM(A,-2) 1D-BM(A,-1) 1D-BM(A,0) 1D-BM(A,1) 1D-BM(A,2) 1D-BM(B,-2) 1D-BM(B,-1) 1D-BM(B,0) 1D-BM(B,1) 1D-BM(B,2) 1D-BM(A,state 0) from SMU: aˆ n 1 (state 0) 1D-BM(B,state 0) In total 64 2:1 MUXs 44

23 Implementation in 0.25µm CMOS Complexity Critical path (Gates) (ns) 14-tap PDFD DFP + 1-tap PDFD (I) DFP + 1-tap LA-PDFD (II) Cable Capacity (CAT6 / Class D) Source: Avaya/ IEEE GT group 46

24 10Gb/s Ethernet 1000Base-T 5-level PAM (2b/symbol) 8-state trellis over 4 pairs Full-duplex echo canceller 125Mbaud, ~80MHz BW No FEXT cancellation 10GBase-T 10-level PAM (3 b/symbol) 8-state trellis over 4 pairs Full-duplex echo canceller 833Mbaud, ~450MHz BW FEXT Cancellation required Throughput = 4pairs x 833Mbaud x 3b/baud = 10Gb/s 47 CAT-5e Cable Loss Jones, 10GBase-T, IEEE meetings 48

25 CAT-5e NEXT Jones, 10GBase-T, IEEE meetings 49 CAT-5e FEXT Jones, 10GBase-T, IEEE meetings 50

26 EMI Jones, 10GBase-T, IEEE meetings 51