CD4049UB, CD4050B. CMOS Hex Buffer/Converters. Applications. [ /Title (CD40 49UB, CD405 0B) /Subject. Ordering Information

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1 CD4049UB, CD4050B Data sheet acquired from Harris Semiconductor SCHS046I August Revised May 2004 [ /Title (CD40 49UB, CD405 0B) /Subject (CMO S Hex Buffer/ Converters) /Autho r () /Keywords (Harris Semiconductor, CD400 0, metal gate, CMOS CMOS Hex Buffer/Converters The CD4049UB and CD4050B devices are inverting and non-inverting hex buffers, respectively, and feature logiclevel conversion using only one supply voltage (V CC ). The input-signal high level (V IH ) can exceed the V CC supply voltage when these devices are used for logic-level conversions. These devices are intended for use as CMOS to DTL/TTL converters and can drive directly two DTL/TTL loads. (V CC = 5V, V OL 0.4V, and I OL 3.3mA.) The CD4049UB and CD4050B are designated as replacements for CD4009UB and CD4010B, respectively. Because the CD4049UB and CD4050B require only one power supply, they are preferred over the CD4009UB and CD4010B and should be used in place of the CD4009UB and CD4010B in all inverter, current driver, or logic-level conversion applications. In these applications the CD4049UB and CD4050B are pin compatible with the CD4009UB and CD4010B respectively, and can be substituted for these devices in existing as well as in new designs. Terminal No. 16 is not connected internally on the CD4049UB or CD4050B, therefore, connection to this terminal is of no consequence to circuit operation. For applications not requiring high sink-current or voltage conversion, the CD4069UB Hex Inverter is recommended. Features CD4049UB Inverting CD4050B Non-Inverting High Sink Current for Driving 2 TTL Loads High-To-Low Level Logic Conversion 100% Tested for Quiescent Current at 20V Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and 25 o C 5V, 10V and 15V Parametric Ratings Applications CMOS to DTL/TTL Hex Converter CMOS Current Sink or Source Driver CMOS High-To-Low Logic Level Converter Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD4049UBF3A -55 to Ld CERDIP CD4050BF3A -55 to Ld CERDIP CD4049UBD -55 to Ld SOIC CD4049UBDR -55 to Ld SOIC CD4049UBDT -55 to Ld SOIC CD4049UBDW -55 to Ld SOIC CD4049UBDWR -55 to Ld SOIC CD4049UBE -55 to Ld PDIP CD4049UBNSR -55 to Ld SOP CD4049UBPW -55 to Ld TSSOP CD4049UBPWR -55 to Ld TSSOP CD4050BD -55 to Ld SOIC CD4050BDR -55 to Ld SOIC CD4050UBDT -55 to Ld SOIC CD4050BDW -55 to Ld SOIC CD4050BDWR -55 to Ld SOIC CD4050BE -55 to Ld PDIP CD4050NSR -55 to Ld SOP CD4050BPW -55 to Ld TSSOP CD4050BPWR -55 to Ld TSSOP NOTE: When ordering, use the entire part number. The suffix R denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinouts CD4049UB (PDIP, CERDIP, SOIC, SOP, TSSOP) TOP VIEW CD4050B (PDIP, CERDIP, SOIC, SOP) TOP VIEW V CC 1 16 NC V CC 1 16 NC G = A 2 15 L = F G = A 2 15 L = F A 3 14 F A 3 14 F H = B 4 13 NC H = B 4 13 NC B 5 12 K = E B 5 12 K = E I = C 6 11 E I = C 6 11 E V SS C J = D D V SS C J = D D 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright 2004, Texas Instruments Incorporated

2 CD4049UB, CD4050B Functional Block Diagrams CD4049UB CD4050B A 3 2 G = A A 3 2 G = A B 5 4 H = B B 5 4 H = B C 7 6 I = C C 7 6 I = C D 9 10 J = D D 9 10 J = D E K = E E K = E F L = F F L = F V CC 1 V CC 1 V SS 8 V SS 8 NC = 13 NC = 16 NC = 13 NC = 16 Schematic Diagrams V CC V CC IN R P N OUT IN R P N P N OUT V SS V SS FIGURE 1A. SCHEMATIC DIAGRAM OF CD4049UB, 1 OF 6 IDENTICAL UNITS FIGURE 1B. SCHEMATIC DIAGRAM OF CD4050B, 1 OF 6 IDENTICAL UNITS 2

3 CD4049UB, CD4050B Absolute Maximum Ratings Supply Voltage (V+ to V-) V to 20V DC Input Current, Any One Input ±10mA Operating Conditions Temperature Range o C to 125 o C Thermal Information Package Thermal Impedance, θ JA (see Note1): E (PDIP) Package o C/W D (SOIC) Package o C/W DW (SOIC) Package o C/W NS (SOP) Package o C/W PW (TSSOP) Package o C/W Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C SOIC - Lead Tips Only CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD DC Electrical Specifications LIMITS AT INDICATED TEMPERATURE ( o C) TEST CONDITIONS 25 PARAMETER V O (V) V IN (V) V CC (V) MIN TYP MAX UNITS Quiescent Device Current I DD (Max) - 0, µa - 0, µa - 0, µa - 0, µa Output Low (Sink) Current I OL (Min) 0.4 0, ma 0.4 0, ma 0.5 0, ma 1.5 0, ma Output High (Source) Current I OH (Min) 4.6 0, ma 2.5 0, ma 9.5 0, ma , ma Out Voltage Low Level V OL (Max) - 0, V - 0, V - 0, V Output Voltage High Level V OH (Min) - 0, V - 0, V - 0, V Input Low Voltage, V IL (Max) CD4049UB V V V Input Low Voltage, V IL (Max) CD4050B V V V 3

4 CD4049UB, CD4050B DC Electrical Specifications (Continued) LIMITS AT INDICATED TEMPERATURE ( o C) TEST CONDITIONS 25 PARAMETER V O (V) V IN (V) V CC (V) MIN TYP MAX UNITS Input High Voltage, V IH Min CD4049UB V V V Input High Voltage, V IH Min CD4050B V V V Input Current, I IN Max - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 µa AC Electrical Specifications T A = 25 o C, Input t r, t f = 20ns, C L = 50pF, R L = 200kΩ TEST CONDITIONS LIMITS (ALL PACKAGES) PARAMETER V IN V CC TYP MAX UNITS Propagation Delay Time Low to High, t PLH CD4049UB ns ns ns ns ns Propagation Delay Time Low to High, t PLH CD4050B ns ns ns ns ns Propagation Delay Time High to Low, t PHL CD4049UB ns ns ns ns ns Propagation Delay Time High to Low, t PHL CD4050B ns ns ns ns ns Transition Time, Low to High, t TLH ns ns ns Transition Time, High to Low, t THL ns ns ns 4

5 CD4049UB, CD4050B AC Electrical Specifications T A = 25 o C, Input t r, t f = 20ns, C L = 50pF, R L = 200kΩ (Continued) TEST CONDITIONS LIMITS (ALL PACKAGES) PARAMETER V IN V CC TYP MAX UNITS Input Capacitance, C IN CD4049UB Input Capacitance, C IN CD4050B pf pf Typical Performance Curves T A = 25 o C T A = 25 o C SUPPLY VOLTAGE (V CC ) = 5V SUPPLY VOLTAGE (V CC ) = 5V V O, OUTPUT VOLTAGE (V) MINIMUM MAXIMUM V O, OUTPUT VOLTAGE (V) MINIMUM MAXIMUM V I, INPUT VOLTAGE (V) V I, INPUT VOLTAGE (V) FIGURE 2. MINIMUM AND MAXIMUM VOLTAGE TRANSFER CHARACTERISTICS FOR CD4049UB FIGURE 3. MINIMUM AND MAXIMUM VOLTAGE TRANSFER CHARACTERISTICS FOR CD4050B I OL, OUTPUT LOW (SINK) CURRENT (ma) T A = 25 o C 15V 10V GATE TO SOURCE VOLTAGE (V GS ) = 5V I OL, OUTPUT LOW (SINK) CURRENT (ma) T A = 25 o C 15V 10V GATE TO SOURCE VOLTAGE (V GS ) = 5V V DS, DRAIN TO SOURCE VOLTAGE (V) V DS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN CHARACTERISTICS 5

6 CD4049UB, CD4050B Typical Performance Curves (Continued) V DS, DRAIN TO SOURCE VOLTAGE (V) V DS, DRAIN TO SOURCE VOLTAGE (V) T A = 25 o C GATE TO SOURCE VOLTAGE V GS = -5V -10V -15V OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS T A = 25 o C GATE TO SOURCE VOLTAGE V GS = -5V -10V -15V OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS V O, OUTPUT VOLTAGE (V) o C V CC = 5V 125 o C SUPPLY VOLTAGE V CC = 10V T A = -55 o C -55 o C V O, OUTPUT VOLTAGE (V) o C 125 o C V CC = 5V -55 o C SUPPLY VOLTAGE V CC = 10V T A = -55 o C V I, INPUT VOLTAGE (V) V I, INPUT VOLTAGE (V) FIGURE 8. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS AS A FUNCTION OF TEMPERATURE FOR CD4049UB FIGURE 9. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS AS A FUNCTION OF TEMPERATURE FOR CD4050B POWER DISSIPATION PER INVERTER (µw) T A = 25 o C SUPPLY VOLTAGE V CC = 15V 10 2 LOAD CAPACITANCE C L = 50pF (11pF FIXTURE + 39pF EXT) C L = 15pF 10 (11pF FIXTURE + 4pF EXT) V 10V 5V f, INPUT FREQUENCY (khz) POWER DISSIPATION PER INVERTER (µw) T A = 25 o C 15V; 1MHz 15V; 100kHz 10V; 100kHz 15V; 10kHz 10V; 10kHz 15V; 1kHz SUPPLY VOLTAGE V CC = 5V FREQUENCY (f) = 10kHz t r, t f, INPUT RISE AND FALL TIME (ns) FIGURE 10. TYPICAL POWER DISSIPATION vs FREQUENCY CHARACTERISTICS FIGURE 11. TYPICAL POWER DISSIPATION vs INPUT RISE AND FALL TIMES PER INVERTER FOR CD4049UB 6

7 CD4049UB, CD4050B Typical Performance Curves (Continued) POWER DISSIPATION PER INVERTER (µw) T A = 25 o C 15V; 1MHz 15V; 100kHz 10V; 100kHz 15V; 10kHz 10V; 10kHz 15V; 1kHz SUPPLY VOLTAGE V CC = 5V FREQUENCY (f) = 10kHz t r, t f, INPUT RISE AND FALL TIME (ns) Test Circuits FIGURE 12. TYPICAL POWER DISSIPATION vs INPUT RISE AND FALL TIMES PER INVERTER FOR CD4050B V CC V SS INPUTS V CC INPUTS V IH V IL V CC OUTPUTS + DVM - I DD V SS V SS FIGURE 13. QUIESCENT DEVICE CURRENT TEST CIRCUIT NOTE: Test any one input with other inputs at V CC or V SS. FIGURE 14. INPUT VOLTAGE TEST CIRCUIT CMOS 10V LEVEL TO DTL/TTL 5V LEVEL V CC = 5V V CC I INPUTS V CC OUTPUTS 10V = V IH COS/MOS IN CD4049 OUTPUT TO DTL/TTL INPUTS 5V = V OH V SS 0 = V IL V SS 0 = V OL V SS NOTE: Measure inputs sequentially, to both V CC and V SS connect all unused inputs to either V CC or V SS. FIGURE 15. INPUT CURRENT TEST CIRCUIT In Terminal - 3, 5, 7, 9, 11, or 14 Out Terminal - 2, 4, 6, 10, 12 or 15 V CC Terminal - 1 V SS Terminal - 8 FIGURE 16. LOGIC LEVEL CONVERSION APPLICATION 7

8 CD4049UB, CD4050B Test Circuits (Continued) V DD 500µF I 0.1µF C L 10kHz, 100kHz, 1MHz CD4049UB C L INCLUDES FIXTURE CAPACITANCE FIGURE 17. DYNAMIC POWER DISSIPATION TEST CIRCUITS 8

9 9 CD4049UB, CD4050B

10 PACKAGE OPTION ADDENDUM 15-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty CD4049UBD ACTIVE SOIC D Green (RoHS & CD4049UBDE4 ACTIVE SOIC D Green (RoHS & CD4049UBDG4 ACTIVE SOIC D Green (RoHS & CD4049UBDR ACTIVE SOIC D Green (RoHS & CD4049UBDRE4 ACTIVE SOIC D Green (RoHS & CD4049UBDRG4 ACTIVE SOIC D Green (RoHS & CD4049UBDT ACTIVE SOIC D Green (RoHS & CD4049UBDTE4 ACTIVE SOIC D Green (RoHS & CD4049UBDTG4 ACTIVE SOIC D Green (RoHS & CD4049UBDW ACTIVE SOIC DW Green (RoHS & CD4049UBDWE4 ACTIVE SOIC DW Green (RoHS & CD4049UBDWG4 ACTIVE SOIC DW Green (RoHS & CD4049UBDWR ACTIVE SOIC DW Green (RoHS & CD4049UBDWRE4 ACTIVE SOIC DW Green (RoHS & CD4049UBDWRG4 ACTIVE SOIC DW Green (RoHS & CD4049UBE ACTIVE PDIP N Pb-Free (RoHS) CD4049UBEE4 ACTIVE PDIP N Pb-Free (RoHS) Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) N / A for Pkg Type N / A for Pkg Type CD4049UBF ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type CD4049UBF3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type CD4049UBF3AS2283 OBSOLETE CDIP J 16 TBD Call TI Call TI CD4049UBF3AS2534 OBSOLETE CDIP J 16 TBD Call TI Call TI CD4049UBM OBSOLETE SOIC D 16 TBD Call TI Call TI CD4049UBM96 OBSOLETE SOIC D 16 TBD Call TI Call TI CD4049UBNSR ACTIVE SO NS Green (RoHS & CD4049UBNSRE4 ACTIVE SO NS Green (RoHS & CD4049UBNSRG4 ACTIVE SO NS Green (RoHS & CD4049UBPW ACTIVE TSSOP PW Green (RoHS & Addendum-Page 1

11 PACKAGE OPTION ADDENDUM 15-Oct-2009 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty CD4049UBPWE4 ACTIVE TSSOP PW Green (RoHS & CD4049UBPWG4 ACTIVE TSSOP PW Green (RoHS & CD4049UBPWR ACTIVE TSSOP PW Green (RoHS & CD4049UBPWRE4 ACTIVE TSSOP PW Green (RoHS & CD4049UBPWRG4 ACTIVE TSSOP PW Green (RoHS & CD4050BD ACTIVE SOIC D Green (RoHS & CD4050BDE4 ACTIVE SOIC D Green (RoHS & CD4050BDG4 ACTIVE SOIC D Green (RoHS & CD4050BDR ACTIVE SOIC D Green (RoHS & CD4050BDRE4 ACTIVE SOIC D Green (RoHS & CD4050BDRG4 ACTIVE SOIC D Green (RoHS & CD4050BDT ACTIVE SOIC D Green (RoHS & CD4050BDTE4 ACTIVE SOIC D Green (RoHS & CD4050BDTG4 ACTIVE SOIC D Green (RoHS & CD4050BDW ACTIVE SOIC DW Green (RoHS & CD4050BDWE4 ACTIVE SOIC DW Green (RoHS & CD4050BDWG4 ACTIVE SOIC DW Green (RoHS & CD4050BDWR ACTIVE SOIC DW Green (RoHS & CD4050BDWRE4 ACTIVE SOIC DW Green (RoHS & CD4050BDWRG4 ACTIVE SOIC DW Green (RoHS & CD4050BE ACTIVE PDIP N Pb-Free (RoHS) CD4050BEE4 ACTIVE PDIP N Pb-Free (RoHS) Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) N / A for Pkg Type N / A for Pkg Type CD4050BF ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type CD4050BF3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type CD4050BF3AS2283 OBSOLETE CDIP J 16 TBD Call TI Call TI CD4050BF3AS2534 OBSOLETE CDIP J 16 TBD Call TI Call TI CD4050BM OBSOLETE SOIC D 16 TBD Call TI Call TI CD4050BNSR ACTIVE SO NS Green (RoHS & Addendum-Page 2

12 PACKAGE OPTION ADDENDUM 15-Oct-2009 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty CD4050BNSRE4 ACTIVE SO NS Green (RoHS & CD4050BNSRG4 ACTIVE SO NS Green (RoHS & CD4050BPW ACTIVE TSSOP PW Green (RoHS & CD4050BPWE4 ACTIVE TSSOP PW Green (RoHS & CD4050BPWG4 ACTIVE TSSOP PW Green (RoHS & CD4050BPWR ACTIVE TSSOP PW Green (RoHS & CD4050BPWRE4 ACTIVE TSSOP PW Green (RoHS & CD4050BPWRG4 ACTIVE TSSOP PW Green (RoHS & Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) JM38510/05553BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type JM38510/05554BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

13 PACKAGE MATERIALS INFORMATION 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) CD4049UBDR SOIC D Q1 CD4049UBDWR SOIC DW Q1 CD4049UBNSR SO NS Q1 CD4049UBPWR TSSOP PW Q1 CD4050BDR SOIC D Q1 CD4050BDWR SOIC DW Q1 CD4050BNSR SO NS Q1 CD4050BPWR TSSOP PW Q1 W (mm) Pin1 Quadrant Pack Materials-Page 1

14 PACKAGE MATERIALS INFORMATION 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD4049UBDR SOIC D CD4049UBDWR SOIC DW CD4049UBNSR SO NS CD4049UBPWR TSSOP PW CD4050BDR SOIC D CD4050BDWR SOIC DW CD4050BNSR SO NS CD4050BPWR TSSOP PW Pack Materials-Page 2

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17 MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,10 M 0, ,50 4,30 6,60 6,20 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 POST OFFICE BOX DALLAS, TEXAS 75265

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22 PACKAGE OPTION ADDENDUM 10-Aug-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan CD4049UBD ACTIVE SOIC D Green (RoHS & CD4049UBDE4 ACTIVE SOIC D Green (RoHS & CD4049UBDG4 ACTIVE SOIC D Green (RoHS & CD4049UBDR ACTIVE SOIC D Green (RoHS & CD4049UBDRE4 ACTIVE SOIC D Green (RoHS & CD4049UBDRG4 ACTIVE SOIC D Green (RoHS & CD4049UBDT ACTIVE SOIC D Green (RoHS & CD4049UBDW ACTIVE SOIC DW Green (RoHS & CD4049UBDWE4 ACTIVE SOIC DW Green (RoHS & CD4049UBDWG4 ACTIVE SOIC DW Green (RoHS & (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) -55 to 125 CD4049UBM -55 to 125 CD4049UBM -55 to 125 CD4049UBM -55 to 125 CD4049UBM -55 to 125 CD4049UBM -55 to 125 CD4049UBM -55 to 125 CD4049UBM -55 to 125 CD4049UBM -55 to 125 CD4049UBM -55 to 125 CD4049UBM CD4049UBDWR ACTIVE SOIC DW 16 TBD Call TI Call TI -55 to 125 CD4049UBM Device Marking (4/5) Samples CD4049UBDWRE4 ACTIVE SOIC DW 16 TBD Call TI Call TI -55 to 125 CD4049UBM CD4049UBE ACTIVE PDIP N Pb-Free (RoHS) CD4049UBEE4 ACTIVE PDIP N Pb-Free (RoHS) N / A for Pkg Type -55 to 125 CD4049UBE N / A for Pkg Type -55 to 125 CD4049UBE CD4049UBF ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD4049UBF CD4049UBF3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD4049UBF3A CD4049UBF3AS2283 OBSOLETE CDIP J 16 TBD Call TI Call TI CD4049UBF3AS2534 OBSOLETE CDIP J 16 TBD Call TI Call TI CD4049UBM OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 Addendum-Page 1

23 PACKAGE OPTION ADDENDUM 10-Aug-2016 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) CD4049UBM96 OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 CD4049UBNSR ACTIVE SO NS Green (RoHS & CD4049UBNSRG4 ACTIVE SO NS Green (RoHS & CD4049UBPW ACTIVE TSSOP PW Green (RoHS & CD4049UBPWG4 ACTIVE TSSOP PW Green (RoHS & CD4049UBPWR ACTIVE TSSOP PW Green (RoHS & CD4049UBPWRE4 ACTIVE TSSOP PW Green (RoHS & CD4050BD ACTIVE SOIC D Green (RoHS & CD4050BDE4 ACTIVE SOIC D Green (RoHS & CD4050BDR ACTIVE SOIC D Green (RoHS & CD4050BDRG4 ACTIVE SOIC D Green (RoHS & CD4050BDT ACTIVE SOIC D Green (RoHS & CD4050BDW ACTIVE SOIC DW Green (RoHS & CD4050BDWR ACTIVE SOIC DW Green (RoHS & CD4050BDWRE4 ACTIVE SOIC DW Green (RoHS & CD4050BE ACTIVE PDIP N Pb-Free (RoHS) CD4050BEE4 ACTIVE PDIP N Pb-Free (RoHS) -55 to 125 CD4049UB -55 to 125 CD4049UB -55 to 125 CM049UB -55 to 125 CM049UB -55 to 125 CM049UB -55 to 125 CM049UB -55 to 125 CD4050BM -55 to 125 CD4050BM -55 to 125 CD4050BM -55 to 125 CD4050BM -55 to 125 CD4050BM -55 to 125 CD4050BM -55 to 125 CD4050BM -55 to 125 CD4050BM N / A for Pkg Type -55 to 125 CD4050BE N / A for Pkg Type -55 to 125 CD4050BE CD4050BF ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD4050BF Device Marking (4/5) Samples CD4050BF3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD4050BF3A Addendum-Page 2

24 PACKAGE OPTION ADDENDUM 10-Aug-2016 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp CD4050BF3AS2283 OBSOLETE CDIP J 16 TBD Call TI Call TI CD4050BF3AS2534 OBSOLETE CDIP J 16 TBD Call TI Call TI (3) Op Temp ( C) CD4050BM OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 CD4050BNSR ACTIVE SO NS Green (RoHS & CD4050BPW ACTIVE TSSOP PW Green (RoHS & CD4050BPWR ACTIVE TSSOP PW Green (RoHS & CD4050BPWRE4 ACTIVE TSSOP PW Green (RoHS & -55 to 125 CD4050B -55 to 125 CM050B -55 to 125 CM050B -55 to 125 CM050B JM38510/05553BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 05553BEA JM38510/05554BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 05554BEA M38510/05553BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 05553BEA M38510/05554BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 05554BEA Device Marking (4/5) Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 3

25 PACKAGE OPTION ADDENDUM 10-Aug-2016 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD4049UB, CD4049UB-MIL, CD4050B, CD4050B-MIL : Catalog: CD4049UB, CD4050B Military: CD4049UB-MIL, CD4050B-MIL NOTE: Qualified Version Definitions: Catalog - TI's standard catalog product Military - QML certified for Military and Defense Applications Addendum-Page 4

26 PACKAGE MATERIALS INFORMATION 10-Aug-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant CD4049UBDR SOIC D Q1 CD4049UBPWR TSSOP PW Q1 CD4050BDR SOIC D Q1 CD4050BDWR SOIC DW Q1 CD4050BPWR TSSOP PW Q1 Pack Materials-Page 1

27 PACKAGE MATERIALS INFORMATION 10-Aug-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD4049UBDR SOIC D CD4049UBPWR TSSOP PW CD4050BDR SOIC D CD4050BDWR SOIC DW CD4050BPWR TSSOP PW Pack Materials-Page 2

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