System Host Board PCI Express Specification PICMG 1.3 Revision 0.9 January 28, 2005

Transcription

1 System Host Board PCI Express Specification PICMG 1.3 Revision 0.9 January 28, 2005

2 Copyright 2005, PCI Industrial Computer Manufacturers Group. The attention of adopters is directed to the possibility that compliance with or adoption of PICMG specifications may require use of an invention covered by patent rights. PICMG shall not be responsible for identifying patents for which a license may be required by any PICMG specification, or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. PICMG specifications are prospective and advisory only. Prospective users are responsible for protecting themselves against liability for infringement of patents. NOTICE: The information contained in this document is subject to change without notice. The material in this document details a PICMG specification in accordance with the license and notices set forth on this page. This document does not represent a commitment to implement any portion of this specification in any company's products. WHILE THE INFORMATION IN THIS PUBLICATION IS BELIEVED TO BE ACCURATE, PICMG MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO ANY WARRANTY OF TITLE OR OWNERSHIP, IMPLIED WARRANTY OF MERCHANTABILITY OR WARRANTY OF FITNESS FOR PARTICULAR PURPOSE OR USE. In no event shall PICMG be liable for errors contained herein or for indirect, incidental, special, consequential, reliance or cover damages, including loss of profits, revenue, data or use, incurred by any user or any third party. Compliance with this specification does not absolve manufacturers of equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.). PICMG,, and the PICMG and logos are trademarks of the PCI Industrial Computer Manufacturers Group. All other brand or product names may be trademarks or registered trademarks of their respective holder.

3 Contents PICMG 1.3 R0.9 1 INTRODUCTION Overview of the Specification Applicable Documents Administration Special Word Usage Name And Logo Usage Signal Naming Conventions Intellectual Property Terminology FEATURE SET Form Factors System Composition Connectors Optional ATX or BTX Power Supply Support ELECTRICAL REQUIREMENTS PCIe Compliance Signals Overview SHB Design Rules PCIe Signals PCIe Differential Clocks to Link Association PCIe Insertion Loss USB Insertion Loss SATA Insertion Loss /100/1000 Ethernet Insertion Loss Optional JTAG/Boundary Scan Signals Optional IPMB Signals Optional ATX/BTX Power Supply Support Vaux Supply Optional USB and SATA Signals Optional SMBus Signals Optional IPMB Signals Optional WAKE# Signal...22 i

4 SHB_RST# Signal PCI REQ#/GNT# Signal Additions PCI M66EN Signal PCI-X PCIXCAP Signal Non-PCI Bus Implementation Pull-up Resistors Requirements SHB PCI(-X) Clock Feedback (CLKFO/CLKFI) Reserved Pins Reserved-Ground Pins Backplane Design Rules PCB Characteristics PCI IDSEL Assignment for Primary PCI Busses PCI Interrupt Binding Primary Bus Interrupt Binding Secondary Bus Interrupt Binding PCI(-X) Electrical Keying (VIO) bit PCI(-X) PCI(-X) M66EN and PCIXCAP Signals Optional JTAG/Boundary Scan Signals Optional IPMB Signals Pull-up Resistors Requirements Backplane PCI(-X) Slot Clock Feedback ATX/BTX Power Supply Support Vaux Supply SHB_RST# Signal Power Distribution SMCLK and SMDAT Optional USB, SATA, and Ethernet Signals WAKE# Signal PCIe Link Configuration Pins Reserved Pins PCI_RST# Signal PCI EXPRESS AND PCI(-X) INTERFACES Connector Pinout PHYSICAL CHARACTERISTICS SHB Backside Component Height Restriction...35

5 5.2 Full-Size SHB Half-Size SHB Backplane Mechanicals REVISION HISTORY...42 iii

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7 Tables Table 1 Subcommittee Members...4 Table 2 SHB Connectors...11 Table 3 SHB Slot Signal Groups...13 Table 4 PCIe Link Configurations...15 Table 5 Differential Clock to PCIe Link Association...16 Table 6 Allocation of PCIe Interconnect Path Insertion Loss...17 Table 7 Allocation of USB Interconnect Path Insertion Loss...18 Table 8 Allocation of SATA Interconnect Path Insertion Loss...19 Table 9 Allocation of Ethernet Interconnect Path Insertion Loss...20 Table 10 ATX/BTX Signals...21 Table 11 Pull-up Resistors on an SHB...24 Table 12 PCI(-X) Keying Rules...24 Table 13 Interrupts on a Primary Backplane Bus...26 Table 14 Interrupt on a PCI-PCI Bridge Secondary Side...26 Table 15 Pull-up Resistors on an Backplane...27 Table 16 PCIe Port Configuration Straps...29 Table 17 Connector A Allowable PCIe Configuration Combinations...29 Table 18 Connector Pinout...32 v

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9 Figures Figure 1 Possible Link Configurations...16 Figure 2 PCIe Insertion Loss...17 Figure 3 USB Insertion Loss...18 Figure 4 SATA Insertion Loss...19 Figure 5 Ethernet Insertion Loss...20 Figure 6 Full-Size SHB Mechanical Drawing...36 Figure 7 Half-Size SHB Mechanical Drawing...37 Figure 8 13-Slot Backplane Mechanical Drawing...38 Figure 9 20-Slot Backplane Mechanical Drawing...39 Figure 10 2U Backplane Mechanical Drawing...40 vii

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11 1 Introduction PICMG 1.3 R0.9 1 INTRODUCTION This specification provides a common set of electrical and mechanical characteristics for the hardware designer. The architecture generally follows the PCI Express and PCI(-X) Local Bus specifications. Drawing from economies of scale with commercial PCI(-X) and PCI Express peripheral cards, and allowing for the existing base of enclosures, power supplies and etcetera, this specification maximizes flexibility in designs. 1.1 Overview of the Specification The SHB is designed to interface with PCI Express peripherals on a backplane. The PCI Express interconnects with the backplane can operate at x1, x4, x8, x16, and others depending on the capabilities of both the SHB and the backplane. The optional PCI(-X) portion of the SHB interconnect with the backplane allows for 32- bit operation. The clock rate between the SHB and the backplane can be 33MHz, 66MHz, 100MHz, and 133MHz, depending on how the backplane and SHB are designed. There is also a pin used to enable PCI-X operation if both the SHB and the backplane are capable of operating in this mode. The dimensions of the SHB (both full and half size) are specified. Other miscellaneous I/O (i.e. SATA, USB, IPMB, SMBUS, Geographic Addressing, and PCI wake up) to the backplane is specified. Implementation of this I/O is not required. 1

12 1 Introduction 1.2 Applicable Documents The specification assumes that the reader has a good knowledge of the following specifications: PCI Bus Power Management Interface Specification, Revision 1.1; PCI Express Base Spec, Revision 1.1; PCI Express Card Electromechanical Spec, Revision 1.1; PCI Express Advanced Switching Spec Proposal, Revision 1.0; PCI Local Bus Specification, Revision 2.2; PICMG Policies and Procedures for Specification Development, Revision 1.1, PCI Industrial Computer Manufacturers Group (PICMG ), 401 Edgewater Place, Suite 500, Wakefield, MA USA, Tel: , Fax: , PCI-to-PCI Bridge Architecture Specification, Revision 1.1; PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b; ATX Specification, Revision 2.03; ATX/ATX12V Power Supply Design Guide, Revision 1.0; IPMI Intelligent Platform Management Bus Communications Protocol, Specification V1.0; The I2C Bus Specification; PCI BIOS ROM Specification, Revision 2.1; ISA Bus Specification P996; Balanced Technology Extended (BTX) Interface Specification, Revision 1.0a; System Management Bus (SMBus) Specification, Version 2.

13 1 Introduction PICMG 1.3 R Administration The Specification (PICMG 1.3) is an open specification supported by the PCI Industrial Computer Manufacturers Group (PICMG ). The subcommittee maintains this specification. For information on how to become a member of the subcommittee contact PICMG. PCI Industrial Computer Manufacturers Group (PICMG ), 401 Edgewater Place, Suite 500, Wakefield, MA USA, Tel: , Fax: , 3

14 1 Introduction Table 1 Subcommittee Members Adlink Advantech Bustronic Cypress Point Research Diversified Technology FCI Foxconn GDA Technologies GE Fanuc Intel Kontron Microbus Molex One Stop Systems Portwell PMC-Sierra Quantum 3D RadiSys SBS Technologies Trenton Technology Tyco

15 1 Introduction PICMG 1.3 R Special Word Usage In this specification the following key words (in bold text) will be used: may: indicates flexibility of choice with no implied preference. should: indicates flexibility of choice with a strongly preferred implementation. shall: indicates a mandatory requirement. Designers shall implement such mandatory requirements to ensure interchangeability and to claim conformance with this specification. 1.5 Name And Logo Usage The PCI Industrial Computer Manufacturers Group s policy regarding the use of the registered trademarks, PICMG,, and the PICMG, logos is as follows: Any company may claim compatibility with PICMG, whether a member of the PICMG or not. Refer to PICMG Policies and Procedures Rev 1.1 Section for claims of compliance language. Permission to use the PICMG and logos is automatically granted to designated members only as stipulated on the most recent Membership Privileges document, during the period of time for which their membership dues are paid. A PICMG member s distributors and sales representatives may use the PICMG and logos in promoting a PICMG member s products sold under the name of the member. The PICMG and logos shall be printed in black or in color as illustrated on the Logo Page that is available from the PICMG at the address above. The center bar of the logos containing the phrase PICMG or SHB Express is set horizontally and the aspect ratio of the logo shall be maintained, but the size may be varied. Nothing may be added to or deleted from the PICMG and logos. Since the PICMG and logos, and the PICMG and SHB Express names are registered trademarks of the PICMG, the following statement shall be included in all published literature and advertising material in which the logos appears: PICMG, and the PICMG and logos are trademarks of the PCI Industrial Computer Manufacturers Group. 1.6 Signal Naming Conventions All signals are active high unless denoted by a trailing #. An active-high signal that is active (i.e., high), or an active-low signal that is active (i.e., low) is referred to herein as an asserted signal and the opposite signal state is referred to as deasserted. Differential signals are denoted by a trailing + or -. 5

16 1 Introduction 1.7 Intellectual Property The Intellectual Property guidelines outlined in the PICMG Policies and Procedures for Specification Development would preclude the (PICMG 1.3) Specification from including any intellectual property not subject to a commitment by its owners to license under reasonable and non-discriminatory terms. The Specification conforms to the Intellectual Property guidelines outlined in the PICMG Policies and Procedures for Specification Development, R1.1.

17 1 Introduction PICMG 1.3 R Terminology It is expected that the reader has a basic understanding of the PCI Express specification. All dimensions are specified in millimeters then inches in the following format: mm (inch). For example, 25.4mm (1 ). The following terms are used in specific ways throughout this document: Backplane Downstream Expansion board Link PCI The board with the SHB slot and expansion slots. 1. The relative position of an interconnect/system element (Port/component) that is farther from the Root Complex. The Ports on a Switch that are not the Upstream Port are Downstream Ports. All Ports on a Root Complex are Downstream Ports. The Downstream component on a Link is the component farther from the Root Complex. 2. A direction of information flow where the information is flowing away from the Root Complex. A standard PCI, PCI-X, or PCIe board PICMG 1.3 System Host Board PCI Express specification. A collection of one or more PCIe Lanes. In this specification, PCI is a generic designation that covers 32-bit (or 64bit on backplane only) PCI at 33/66MHz. A more specific designation is used when required. PCIe In this specification, PCIe is a generic designation that covers x1, x4, x8, x16 PCI Express Base. A more specific designation is used when required PCIe Lane One PCIe Lane contains two differential lines for Transmitter and two differential lines for Receiver. PCI-X In this specification, PCI-X is a generic designation that covers 32-bit (or 64bit on backplane only) PCI-X at 33/66/100/133MHz. A more specific designation is used when required. PCI(-X) In this specification, PCI(-X) is a generic designation that covers 32-bit (or 64bit on backplane only) PCI at 33/66MHz, as well as 32-bit PCI-X at 33/66/100/133MHz. A more specific designation is used when required. Port 1. Logically, an interface between a component and a PCI Express Link. 2. Physically, a group of Transmitters and Receivers located on the same chip that define a Link. Primary Bus 1. A PCI(-X) bus segment directly attached to the SHB through connector D 7

18 1 Introduction 2. A PCI(-X) bus segment directly attached to a PCIe-to-PCI(-X) bridge. Root Complex Hierarchically the originator of the PCIe fabric. SHB System Host Board. Refers to the removable CPU board that is the root complex of the system. SHB slot The slot on an backplane where you put the SHB. An SHB or electrically compliant board may populate this slot. Upstream 1. The relative position of an interconnect/system element (Port/component) that is closer to the Root Complex. The Port on a Switch that is closest topologically to the Root Complex is the Upstream Port. The Port on an Endpoint or Bridge is an Upstream Port. The Upstream component on a Link is the component closer to the Root Complex. 2. A direction of information flow where the information is flowing towards the Root Complex. xn A link with N physical lanes. N can be 1, 2, 4, 8, or 16 in this SHB Express specification (i.e. x1, x4, x8, or x16).

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20 2 Feature Set 2 FEATURE SET 2.1 Form Factors The SHB s are defined in two form factors: full-size and half-size SHB s (See Section 5). The full-size SHB length is identical to the ISA long board length and height. Half-size SHB form factor is based on the half-size PCIe and PCI board in length, while following the ISA board height. 2.2 System Composition An system is composed of one SHB and an backplane. Expansion slots have 20.32mm (0.8 ) board center-to-center spacing as defined in the PCI Express Card Electromechanical Specification. The SHB should provide as many connections as possible with a minimum of one lane each of PCIe to the backplane. Physically the SHB slot may be located at any slot in the backplane. Electrically all SHB PCIe connections shall be the root complex AND/OR the most upstream port of the backplane. Mechanically, Connectors A, B, C, and, optionally, D should be present for a full-size SHB. Mechanically, Connectors A and B should be present for a half-size SHB. A SHB Connector D should provide arbitration, clock distribution, and reset functions for all primary PCI(-X) expansion boards. A SHB is responsible for performing system initialization by managing each local board s IDSEL signal on the PCI(-X) backplane. Physically the SHB slot may be located at any slot in the backplane. Electrically it shall be at the end of the primary PCI(-X) bus. Each Connector may have up to the following: Connector A: (One link of x16 PCIe) OR (two links of x8 PCIe) OR (one link of x8 PCIe AND two links of x4 PCIe) OR (four links of x4 PCIe) Connector B: (One link of x4 PCIe) OR (four links of x1 PCIe). Connector C: Additional power and I/O. Connector D: One 32-bit PCI(-X) bus. The SHB may connect IPMB, PCI wake up, ATX support, Ethernet, USB, and SATA to the backplane. 2.3 Connectors For reference purposes, the connectors are lettered from A through D starting at the I/O bracket end of the board. Table 2 shows the physical connectors specified for the SHB. Mechanically all SHB connectors are defined in the PCI Express Card Electromechanical Specification.

21 2 Feature Set PICMG 1.3 R0.9 Table 2 SHB Connectors Connector Type Pin Count A x B x8 98 C x D x8 98 On the full-size SHB and backplane there should be two (2) x16 PCI Express connectors (A and C) and two (2) x8 PCI Express connectors (B and D). On the half-size SHB and backplane there shall be one x16 PCI Express Connector (A) and one x8 PCI Express Connector (B). See Section 4.1 for a detailed pinout of all four connectors. 2.4 Optional ATX or BTX Power Supply Support A SHB may implement ATX or BTX power supply support. Also, an backplane may implement ATX or BTX support and the system power supply may be ATX or BTX. All ATX/non-ATX/BTX/non-BTX combinations are valid and covered to avoid interoperability problems while keeping this feature fully operational. 11

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23 3 Electrical Requirements PICMG 1.3 R0.9 3 ELECTRICAL REQUIREMENTS 3.1 PCIe Compliance Connectors A and B of the SHB and backplane that utilizes PCIe shall adhere to the PCI Express Base Specification. An SHB and backplane, if utilizing the PCI connection shall adhere to the PCI Local Bus Specification and to the PCI-to-PCI Bridge Architecture Specification. Depending on their capabilities, they might have to adhere to the PCI-X Addendum to the PCI Local Bus Specification and the PCI Bus Power Management Interface Specification. This chapter documents additional requirements and/or restrictions as needed. 3.2 Signals Overview Table 3 SHB Slot Signal Groups Type Signals Description Connector Source GND, +5V, +3.3V, +12V Power backplane +3.3Vaux Optional standby supply A backplane PWRGD, PSON#, PWRBT#, +5Vaux Optional ATX support A and B backplane TRST#, TCK, TMS, TDI, Optional JTAG support TDO A SHB SMCLK, SMDAT Optional SMBus support A SHB Match keying for PCI VIO D backplane bus Global IPMB_CL, IPMB_DA Optional IPMB support C SHB CFG[0:3] PCIe configuration straps A backplane GA[0:5] Reserved for optional geographic addressing C SHB for IPMB SHB_RST# Optional reset line A SHB RSVD Reserved A and B RSVD-G Reserved ground A backplane WAKE# Signal for link reactivation A backplane 13

24 3 Electrical Requirements PCIe PCI(-X) Miscellaneous I/O a_petp[0:15], a_petn[0:15], a_perp[0:15], a_pern[0:15] b_petp[0:7], b_petn[0:7], b_perp[0:7], b_pern[0:7] REFCLK[0:7]+, REFCLK[0:7]- AD[0:31], FRAME#, IRDY#, TRDY#, STOP#, LOCK#, DEVSEL#, PERR#, SERR#, C/BE[0:3], SDONE, SBO# REQ[0:3], GNT[0:3], CLKA, CLKB, CLKC, CLKD INTA#, INTB#, INTC#, INTD# M66EN, PCIXCAP PME# USB[0:3]P, USB[0:3]N, USBOC[0:3]# SATAHT[0:1]P, SATAHT[0:1]N, SATAHR[0:1]P, SATAHR[0:1]N a_mdi[0:3]p, a_mdi[0:3]n, b_mdi[0:3]p, b_mdi[0:3]n Point-to-point from SHB slot through the x16 PCIe Connector (A) to the target device(s) Point-to-point from SHB slot through the x8 PCIe Connector (B) to the target device(s) Clock synchronization of PCIe expansion slots Bussed on SHB slot and expansion slots Point-to-point from SHB slot to each expansion slot Bussed (rotating) on SHB slot and expansion slots Bussed on SHB slot and expansion slots Optional PCI wake-up event bussed on SHB and backplane expansion slots Optional point-to-point from SHB Connector C to a destination USB device Optional point-to-point from SHB Connector C to a destination SATA device Optional point-to-point from SHB Connector C to a destination Ethernet device A and B A A D D D D A C C C SHB SHB SHB SHB SHB backplane SHB SHB SHB SHB SHB

25 3 Electrical Requirements PICMG 1.3 R SHB Design Rules PCIe Signals Table 4 below shows the possible link configurations. Note that B0 can also be four x1 ports. Table 4 PCIe Link Configurations Configuration A3 (x4) A2 (x8) A2 (x4) A0 (x16) A1 (x4) A0 (x8) A0 (x4) Ref Clks for all ports (up to 8 clks) c1 x16 (Ref Clks) x4 c2 second x8 first x8 (Ref Clks) x4 c3 third x4 second x4 x8 (Ref Clks) first x4 c4 fifth x4 fourth x4 third x4 second x4 (Ref Clks) first x4 B3 (x1) B2 (x1) B0 (x4) B1 (x1) B0 (x1) A backplane should plumb the PCIe in the following order to maximize interoperability: c5 8th 7th 6th 5th 4th 3rd 2nd 1st All SHB s should provide at least x1 PCIe to all possible links. Below are examples of possible PCIe applications through both Connector A and B. Note that PEXx refers to the PCIe links where X is either T ransmit or R eceive, and x is either p ositive or n egative differential pairs. The ports for the A[3:0] links shall be configured in one of the following ways: a_pexx[0:15] (A0) Up to (1) x16 PCIe a_pexx[8:15] (A2) a_pexx[0:7] (A0) OR Up to (2) x8 PCIe a_pexx [12:15] (A3) a_pexx [8:11] (A2) a_pexx [0:7] (A0) OR Up to (2) x4 PCIe AND (1) x8 PCIe a_pexx [12:15] (A3) a_pexx [8:11] (A2) a_pexx [4:7] (A1) a_pexx [0:3] (A0) OR Up to (4) x4 PCIe 15

26 3 Electrical Requirements The ports for the B[3:0] links shall be configured in one of the following ways: (Ref Clocks) b_pexx[0:3] (B0) Up to (1) x4 PCIe (Ref Clocks) b_pexx3 (B3) b_pexx2 (B2) b_pexx1 (B1) b_pexx0 (B0) OR Up to (4) x1 PCIe Figure 1 Possible Link Configurations The PCIe signals (PETp[0:15], PETn[0:15], PERp[0:15], PERn[0:15], REFCLK+ and REFCLK-) that are not used shall be pulled up with a 8.2k Ohm resistor to 3.3V. All PCIe links should support x1 PCIe as a minimum. Optionally, the x16 link may support x1, x4, x8, and x16. The x8 PCIe link may support x1, x4, and x8. The x4 PCIe link may support x1 and x4. The x1 PCIe link may support x1 only PCIe Differential Clocks to Link Association If the SHB supplies a specific link to the backplane, then the SHB shall supply the associated differential clock. If a link can be broken down into multiple links, the SHB shall provide every clock that might be used on the backplane. For example, if the SHB provides A0 as a single x8, and that link could work as two x4 links, then the SHB shall provide REFCLK4 and REFCLK5. Table 5 Differential Clock to PCIe Link Association Differential Clock REFCLK0 REFCLK1 REFCLK2 REFCLK3 REFCLK4 REFCLK5 REFCLK6 REFCLK7 PCIe link B0 B1 B2 B3 A0 A1 A2 A PCIe Insertion Loss The maximum loss values in db (decibels) are specified for the SHB and the PCIe

27 3 Electrical Requirements PICMG 1.3 R0.9 connector. This budget distribution serves as a design guideline to help achieve the specified eye diagrams. Figure 2 PCIe Insertion Loss SHB L ST L BR Backplane PCI Express Connector L BT PCI Express Connector L SR Table 6 Allocation of PCIe Interconnect Path Insertion Loss Loss Symbol Loss Budget Value Comments Parameter at 1.25 GHz (db) SHB L SR < , 2 L ST < Backplane to L BR < , 3 add in card L BT < Backplane to L BR < , 4 silicon L BT < Notes: 1. The above calculations are based on the following assumptions: connector loss = 1dB, capacitor loss = 0.3dB each, fr4 material loss = 0.3dB/inch/GHz. 2. Max allowable loss on SHB including the connector to the backplane. 3. The backplane to add in card loss accounts for the loss defined in the PCI Express Card Electromechanical Specification for a PCIe slot. 4. The backplane to silicon loss assumes you are not going to a PCI Express slot, but rather to some type of silicon like a bridge or switch. Therefore the L AR = 2.65dB and L AT = 3.84dB, as defined in the PCI Express Card Electromechanical Specification, is allowed for on the backplane. 17

28 3 Electrical Requirements USB Insertion Loss The maximum loss values in db (decibels) are specified for the SHB and backplane. This budget distribution serves as a design guideline to help achieve the specified eye diagrams. Figure 3 USB Insertion Loss SHB L S Backplane L B USB Connector Overcurrent Protection PCI Express Connector Table 7 Allocation of USB Interconnect Path Insertion Loss Loss Symbol Loss Budget Value Comments Parameter at 250 MHz (db) SHB L S < , 2 Backplane to USB connector L B < 0.9 1, 3, 4 Notes: 1. The above calculations are based on the following assumption: fr4 material loss = 0.3dB/inch/GHz. 2. Max allowable loss on SHB including the connector to the backplane. 3. The Backplane to USB connector loss accounts for the loss defined in the Universal Serial Bus Revision 2.0 specification. 4. Appropriate overcurrent protection shall be provided for each USB connection available on the backplane.

29 3 Electrical Requirements PICMG 1.3 R SATA Insertion Loss The maximum loss values in db (decibels) are specified for the SHB and backplane. This budget distribution serves as a design guideline to help achieve the specified eye diagrams. Figure 4 SATA Insertion Loss SHB Backplane L S L R L B SATA Connector Repeater PCI Express Connector L S L R L B Table 8 Allocation of SATA Interconnect Path Insertion Loss Loss Parameter Symbol Loss Budget Value Comments at 1.5 GHz SATAI or 3.0 GHz SATAII (db) SHB L S < 1.4 1, 2 PCIe connector L R < 0.4 1, 3, 4 to Repeater Repeater to SATA connector L B < 1.8 1, 4 Notes: 1. The above calculations are based on the following assumptions: connector loss = 1dB, fr4 material loss = 0.3dB/inch/GHz. 2. Max allowable loss on SHB including the connector to the backplane. 3. Appropriate repeaters should be provided for each SATA connection available on the SHB. 4. Max allowable SATA loss total is 1.8 db. 19

30 3 Electrical Requirements /100/1000 Ethernet Insertion Loss The maximum loss values in db (decibels) are specified for the SHB and backplane. This budget distribution serves as a design guideline to help achieve the specified eye diagrams. Figure 5 Ethernet Insertion Loss SHB L S Backplane L B Ethernet Connector PCI Express Connector Magnetics L S L B Table 9 Allocation of Ethernet Interconnect Path Insertion Loss Loss Symbol Loss Budget Value Comments Parameter at 500 MHz (db) SHB L S < 0.9 1, 2, 3 Backplane to Ethernet connector L B < 0.9 1, 4 Notes: 5. The above calculations are based on the following assumption: fr4 material loss = 0.3dB/inch/GHz. 6. Max allowable loss on SHB including the connector to the backplane. 7. Appropriate magnetics shall be provided for each ethernet connection available on the SHB. 8. The Backplane to USB connector loss accounts for the loss defined in the IEEE Std chapter Optional JTAG/Boundary Scan Signals A SHB with no JTAG capability shall connect TDI to TDO and leave TRST#, TMS and TCK unconnected.

31 3 Electrical Requirements PICMG 1.3 R Optional IPMB Signals A SHB that does not support IPMB shall leave IPMB_CL and IPMB_DA unconnected Optional ATX/BTX Power Supply Support These pins are used to turn on and off an ATX or BTX power supply. The following signals comply with the ATX Specification. PSON# +5Vaux PWRGD PWRBT# Table 10 ATX/BTX Signals This signal is a direct connection to an ATX power supply. The SHB forces a TTL low on this pin to turn on the power supply and tri-state the pin to turn it off. An unpowered SHB shall leave this pin tristate to avoid turning the power supply on at insertion time. Standby supply from the ATX power supply. This signal is a direct connection to an ATX power supply. PWRGD is in a TTL 1 state when the supplies are stable. The SHB shall have a 2.2k pull-up resistor to +5V on this pin The PWRBT# signal is a direct connection to a momentary, normally open, pushbutton with a return to ground. The SHB shall provide appropriate pull-up resistor and debouncing circuit for the switch. The SHB assumes that the signal PWRBT# is externally protected from direct ESD (electrostatic discharge) hits. A SHB with ATX or BTX support shall provide a +5Vaux powered logic circuit to toggle the PSON# signal according to the state of PWRBT# and its internal states (soft off, wake up events, etc.). A SHB with ATX or BTX support must be able to deal with the fact that a non-atx and non-btx backplane or power supply will provide +5V rather than +5Vaux. 21

32 3 Electrical Requirements Vaux Supply Voltage shall be supplied to the +3.3Vaux pins on the SHB slot Optional USB and SATA Signals If an SHB supports USB it shall terminate USB[0:3]P and USB[0:3]N as described in the Universal Serial Bus Specification. A SHB with no support for USB and/or SATA shall leave these pins unconnected Optional SMBus Signals The SHB shall have 8.2k Ohm resistor pull-ups on SMCLK and SMDAT. The pull-ups shall be connected to 3.3Vaux unless 3.3Vaux is not supported, in which case the pullups shall be connected directly to 3.3V Optional IPMB Signals The SHB shall pull-up IPMB_CL and IPMB_DA with 8.2k Ohm resistors to 3.3Vaux unless 3.3Vaux is not supported, in which case the pull-ups shall be connected directly to 3.3V Optional WAKE# Signal The SHB shall pull-up WAKE# with an 8.2k Ohm resistor to 3.3V. The pull-up shall be connected to 3.3Vaux unless 3.3Vaux is not supported, in which case the pull-up shall be connected directly to 3.3V SHB_RST# Signal The SHB shall pull-up SHB_RST# with an 8.2k Ohm resistor to 3.3V. The SHB_RST# signal is a direct connection to a momentary, normally open, push-button with a return to ground PCI REQ#/GNT# Signal Additions A SHB should provide all four REQ#/GNT# pairs. If some REQ#/GNT# pairs are not available, the SHB shall provide the available REQ#/GNT# pairs starting from REQ0#/GNT0# through REQ3#/GNT3#. Any unused GNT# signals on a SHB shall have a strong pull-up resistor to +5V to avoid floating the GNT# signal of an expansion board. For example, a +5V SHB providing 3 pairs of REQ#/GNT# will leave REQ3# unconnected and GNT3# pulled to +5V.

33 3 Electrical Requirements PICMG 1.3 R PCI M66EN Signal A SHB that does not support 66MHz PCI signaling on a bus shall ground the corresponding M66EN pin PCI-X PCIXCAP Signal A SHB with no PCI-X capability on a bus shall ground the corresponding PCIXCAP pin Non-PCI Bus Implementation A full size SHB (with Connector D present) that does not support the PCI bus shall leave all PCI signals unconnected except for PCI_RST#, which shall be pulled to GND via a 100 Ohms resistor on the SHB. 23

34 3 Electrical Requirements Pull-up Resistors Requirements Table 11 shows the pull-up resistors required on the SHB. Table 11 Pull-up Resistors on an SHB Signals FRAME#, IRDY#, TRDY#, STOP#, LOCK#, DEVSEL#, PERR#, SERR#, REQ[0:3]#, GNT[0:3]#, INTA#, INTB#, INTC#, INTD# REQ64#, ACK64#, C/BE[4:7]#, PAR64, AD[32:63] PME# M66EN PCIXCAP PWRGD PWRBT# Table 12 shows the reference voltage for pull-ups. SHB electrical Signaling Table 12 PCI(-X) Keying Rules SHB pull-up resistors voltage +5V VIO pin Requirement Always required, value per PCI Local Bus Specification and/or chipset requirement. Always required if present, value per PCI Local Bus Specification. For power management support only. For 66Mhz PCI. For PCI-X. 2.2k pull-up resistor to +5V for ATX support. Appropriate pull-up required by the SHB ATX control circuit, if present. Backplane Signaling (VIO) Rule +5V Normal Operation. +3.3V The SHB shall stay in reset to avoid damaging off-board 3.3V PCI devices. Universal VIO pin +3.3V or +5V Normal Operation. +3.3V +3.3V rail +5V +3.3V The SHB shall stay in reset to avoid being damaged by off-board 5V PCI devices. Normal Operation.

35 3 Electrical Requirements PICMG 1.3 R SHB PCI(-X) Clock Feedback (CLKFO/CLKFI) A SHB may use the clock feedback from the backplane to minimize clock skew. If it does, it shall output a PCI clock on the CLKFO pin and read it back on the CLKFI pin. If the clock feedback is not used, CLKFO and CLKFI shall be grounded Reserved Pins A SHB shall leave unconnected all reserved pins marked as RSVD Reserved-Ground Pins A SHB shall leave unconnected all reserved pins marked as RSVD-G. 3.4 Backplane Design Rules PCB Characteristics If an backplane is PCIe ready, it shall comply with the PCIe requirements for the printed circuit board as described in the PCI Express Base Specification. The backplane shall have a characteristic impedance of 100 Ohms +/- 10% differential impedance, and conform to the PCIe rules for trace spacing for all PCIe signals. If an backplane is PCI(-X) ready, it shall comply with PCI(-X) requirements for the printed circuit board as described in the PCI Local Bus Specification and PCI-X Addendum to the PCI Local Bus Specification. The backplane shall have a characteristic impedance of 57 Ohms +/- 10% and conform to the PCI(-X) rules for trace spacing for all PCI(-X) signals PCI IDSEL Assignment for Primary PCI Busses The backplane shall make the IDSEL connection at each expansion slot or device through a resistor as defined in the PCI Local Bus Specification. This resistor shall be placed to minimize the stub on the ADxx line. The SHB shall use AD[28:31] point-topoint to each expansion slot on the primary bus. A backplane should implement slot IDSEL on the primary bus starting with AD31 and going sequentially down in a secondary ADxx number PCI Interrupt Binding The interrupt binding on the primary bus is identical to the PICMG 1.0 and 1.2 specification. The secondary binding complies with the PCI-to-PCI Bridge Architecture Specification. The primary bus is defined as either: 25

36 3 Electrical Requirements 1. A PCI(-X) bus segment directly attached to the SHB through connector D 2. A PCI(-X) bus segment directly attached to a PCIe-to-PCI(-X) bridge Primary Bus Interrupt Binding Table 13 Interrupts on a Primary Backplane Bus SHB PCI slot AD31 PCI slot AD30 PCI slot AD29 PCI slot AD28 INTA# INTD# (B8) INTC# (A7) INTB# (B7) INTA# (A6) INTB# INTA# (A6) INTD# (B8) INTC# (A7) INTB# (B7) INTC# INTB# (B7) INTA# (A6) INTD# (B8) INTC# (A7) INTD# INTC# (A7) INTB# (B7) INTA# (A6) INTD# (B8) For example, a INTA# (SHB Connector D pin A1) is connected to slot AD31 pin B8, slot AD30 pin A7, slot AD29 pin B7, and slot AD28 pin A Secondary Bus Interrupt Binding A bridge can be on the backplane or on a PCI expansion board. In both cases, it logically occupies a slot. The following Table 14 is an extract of the PCI-to-PCI Bridge Architecture Specification. Bridge primary (virtual slot) Table 14 Interrupt on a PCI-PCI Bridge Secondary Side Secondary PCI slot AD31, 27, 23, 19, 15, 11, 7, 3 Secondary PCI slot AD30, 26, 22, 18, 14, 10, 6, 2 Secondary PCI slot AD29, 25, 21, 17, 13, 9, 5, 1 Secondary PCI slot AD28, 24, 20, 16, 12, 8, 4, 0 (INTA#) INTB# (B7) INTC# (A7) INTD# (B8) INTA# (A6) (INTB#) INTC# (A7) INTD# (B8) INTA# (A6) INTB# (B7) (INTC#) INTD# (B8) INTA# (A6) INTB# (B7) INTC# (A7) (INTD#) INTA# (A6) INTB# (B7) INTC# (A7) INTD# (B8) PCI(-X) Electrical Keying (VIO) The VIO pin is a power input to the SHB and provides keying information. The VIO pin shall not be directly connected to +5V or +3.3V on the SHB. Table 12 defines the interoperability rules.

37 3 Electrical Requirements PICMG 1.3 R bit PCI(-X) REQ64#, ACK64#, PAR64, AD[32:63], and C/BE[4:7] signals shall be pulled-up or pulled-down per the PCI Local Bus Specification PCI(-X) M66EN and PCIXCAP Signals The M66EN and PCIXCAP signals shall be bussed on all connectors on a given bus. Each expansion slot shall implement a 0.01uF capacitor within 0.25 of the physical slots as per PCI-X Addendum to the PCI Local Bus Specification on the M66EN and PCIXCAP signals. If an backplane has speed limitations because of its bus topology, length, or number of slots, it should restrict bus speed by placing appropriate pull-down resistor or ground connections on M66EN and PCIXCAP signals according to the PCI-X Addendum to the PCI Local Bus Specification Optional JTAG/Boundary Scan Signals An backplane with JTAG capability may provide access to the JTAG portion of the SHB slot Optional IPMB Signals An backplane with IPMB capability may provide access to the SHB slot IPMB signals IPMB_CL and IPMB_DA. If IPMB is not supported on the backplane then these pins should be left unconnected Pull-up Resistors Requirements Table 15 shows the pull-up resistors required on the backplane. Table 15 Pull-up Resistors on an Backplane Signals AD[32:63], C/BE[4:7]#, PAR64 PCIXCAP Requirement If present, always required, value per PCI Local Bus Specification. If present, always required, value per PCI- X Addendum to the PCI Local Bus Specification if running in PCI-X mode Backplane PCI(-X) Slot Clock Feedback An Backplane may use the clock feedback from the SHB to minimize clock skew. If it does, it shall use CLKF0 and CLKF1 in making the feedback clock longer than the 1 allowed for on the SHB. 27

38 3 Electrical Requirements If the clock feedback is not used, CLKF0 and CLKF1 shall be either grounded or floating ATX/BTX Power Supply Support All backplanes with ATX, BTX or equivalent capability shall route PSON#, +5Vaux and PWROK from the ATX or BTX connector to the SHB slot. All backplanes shall have a 2 pin header with 2.54mm (0.1 ) spacing used to turn on the power supply. This header will provide a means to connect a momentary push-button (local or remote). Pin 1 shall be PWRBT# and pin 2 shall be ground. The backplane should have some form of jumper or strapping option on PSON# to be able to turn on or off an ATX, BTX, or equivalent power supply when the SHB has no power supply control capability. If the backplane (or the power supply) has no ATX or BTX connector, it shall leave the SHB slot pins PWRBT#, PSON#, and PWRGD floating. It shall also route +5V to the +5Vaux pins on the SHB slot Vaux Supply If a +3.3Vaux standby voltage is available it shall be routed to the SHB slot. If the +3.3Vaux standby voltage is not available then standard 3.3V shall be provided to the +3.3Vaux pins on the SHB slot. +3.3Vaux standby voltage may be provided to the backplane peripheral slots SHB_RST# Signal All backplanes shall have a 2 pin header with 2.54mm (0.1 ) spacing used to reset the power supply. Pin 1 shall be SHB_RST# and pin 2 shall be ground Power Distribution As per PCI Express Base Specification, an backplane shall provide +5V, +3.3V, and +12V with +/-5% tolerance. The backplane PCB should provide separate power planes for +3.3V, +5V, +12V and ground SMCLK and SMDAT If the backplane is capable of supporting SMBus (SMCLK and SMDAT signals), the signals shall be bussed between the SHB slot and the corresponding pins on expansion

39 3 Electrical Requirements PICMG 1.3 R0.9 slots (see System Management Bus (SMBus) Specification, and Intelligent Platform Management Interface Specification.). A backplane that is not capable of supporting SMBus (i.e. a backplane with no PCIe slots) shall leave these pins unconnected Optional USB, SATA, and Ethernet Signals A backplane with no support for USB, SATA and/or Ethernet shall leave these pins unconnected WAKE# Signal A backplane shall route WAKE# to all PCIe devices and SHB slot PCIe Link Configuration Pins There are four configuration signals (CFG[0:3]) that the backplane shall provide to the SHB to convey the desired PCI-Express port configurations on connectors A and B. These configuration signals are pulled up to 3.3V for a logic 1 or pulled down to signal ground for a logic 0. The recommended resistor value is 2.2k Ohm. Table 16 PCIe Port Configuration Straps CFG0 = 1 PORT A0 = x16 If CFG0 = 1, CFG1 and CFG2 don t matter CFG0 = 0 PORT A0 = x8 or x4 If CFG0 = 0, CFG1 and CFG2 determine ports A0 and A1 configuration CFG1 = 1 PORT A0 = x8 CFG1 is only used if CFG0 = 0 CFG1 = 0 PORT A0 = x4, PORT A1 = x4 CFG1 is only used if CFG0 = 0 CFG2 = 1 PORT A2 = x8 CFG2 is only used if CFG0 = 0 CFG2 = 0 PORT A2 = x4, PORT A3 = x4 CFG2 is only used if CFG0 = 0 CFG3 = 1 PORT B0 = x4 CFG3 = 0 PORT B0 through B3 = x1 Table 17 Ports A[0:3] Allowable PCIe Configuration Combinations CFG0 CFG1 CFG2 A0 MAX A1 MAX A2 MAX A3 MAX WIDTH WIDTH WIDTH WIDTH x x8 0 x x4 x4 x4 x4 Note: A dash, -, in the table above indicates a don t care state. 29

40 3 Electrical Requirements Reserved Pins An backplane shall leave unconnected all reserved pins marked as RSVD Reserved-Ground Pins An backplane shall pull-down with an 8.2k Ohm resistor all reserved pins marked as RSVD-G PCI_RST# Signal A backplane with PCI(-X) support shall pull down PCI_RST# with a 8.2k Ohm resistor for the case where Connector D is not supplied from the SHB.

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42 4 PCI Express and PCI(-X) Interfaces 4 PCI EXPRESS AND PCI(-X) INTERFACES 4.1 Connector Pinout Table 18 Connector Pinout x16 PCIe Connector A x8 PCIe Connector B x16 PCIe Connector C x8 PCIe Connector D Side B Side A Side B Side A Side B Side A Side B Side A 1 SMCLK SMDAT 1 +5Vaux +5Vaux 1 USB0P GND 1 INTB# INTA# 2 GND GND 2 GND RSVD 2 USB0N GND 2 INTD# INTC# 3 TDI TCK 3 a_petp8 GND 3 GND USB1P 3 GND VIO 4 TDO TMS 4 a_petn8 GND 4 GND USB1N 4 REQ3# GNT3# 5 TRST# WAKE# 5 GND a_perp8 5 USB2P GND 5 REQ2# GNT2# 6 PWRBT# PME# 6 GND a_pern8 6 USB2N GND 6 PCI_RST# GNT1# 7 PWRGD PSON# 7 a_petp9 GND 7 GND USB3P 7 REQ1# GNT0# 8 SHB_RST# PERST# 8 a_petn9 GND 8 GND USB3N 8 REQ0# SERR# 9 CFG0 CFG1 9 GND a_perp9 9 USBOC0# GND 9 SDONE +3.3V 10 CFG2 CFG3 10 GND a_pern9 10 GND USBOC1# 10 GND CLKFI 11 RSVD GND 11 RSVD GND 11 USBOC2# GND 11 CLKFO GND Mechanical Key Mechanical Key Mechanical Key Mechanical Key 12 GND RSVD 12 GND RSVD 12 GND USBOC3# 12 CLKC CLKD 13 b_petp0 GND 13 a_petp10 GND 13 SATAHT0P GND 13 GND +3.3V 14 b_petn0 GND 14 a_petn10 GND 14 SATAHT0N GND 14 CLKA CLKB 15 GND b_perp0 15 GND a_perp10 15 GND SATAHR0P V GND 16 GND b_pern0 16 GND a_pern10 16 GND SATAHR0N 16 AD31 PME# 17 b_petp1 GND 17 a_petp11 GND 17 SATAHT1P GND 17 AD V 18 b_petn1 GND 18 a_petn11 GND 18 SATAHT1N GND 18 M66EN AD30 19 GND b_perp1 19 GND a_perp11 19 GND SATAHR1P 19 AD27 AD28 20 GND b_pern1 20 GND a_pern11 20 GND SATAHR1N 20 AD25 GND 21 b_petp2 GND 21 a_petp12 GND 21 a_mdi0p GND 21 GND AD26 22 b_petn2 GND 22 a_petn12 GND 22 a_mdi0n GND 22 C/BE3# AD24 23 GND b_perp2 23 GND a_perp12 23 GND a_mdi1p 23 AD V 24 GND b_pern2 24 GND a_pern12 24 GND a_mdi1n 24 GND AD22 25 b_petp3 GND 25 a_petp13 GND 25 a_mdi2p GND 25 AD21 AD20 26 b_petn3 GND 26 a_petn13 GND 26 a_mdi2n GND 26 AD19 PCIXCAP 27 GND b_perp3 27 GND a_perp13 27 GND a_mdi3p 27 +5V AD18 28 GND b_pern3 28 GND a_pern13 28 GND a_mdi3n 28 AD17 AD16 29 REFCLK0+ GND 29 a_petp14 GND 29 IPMB_CL GND 29 C/BE2# GND 30 REFCLK0- GND 30 a_petn14 GND 30 IPMB_DA GND 30 GND FRAME# 31 GND REFCLK1+ 31 GND a_perp14 31 GA0 GA1 31 IRDY# TRDY# 32 RSVD-G REFCLK1-32 GND a_pern14 32 GA2 GA4 32 DEVSEL# +5V 33 REFCLK2+ GND 33 a_petp15 GND 33 GA3 GA5 33 LOCK# STOP# 34 REFCLK2- GND 34 a_petn15 GND 34 b_mdi0p GND 34 PERR# GND 35 GND REFCLK3+ 35 GND a_perp15 35 b_mdi0n GND 35 GND C/BE1# 36 RSVD-G REFCLK3-36 GND a_pern15 36 GND b_mdi1p 36 PAR AD14 37 REFCLK4+ GND 37 RSVD GND 37 GND b_mdi1n 37 SB0# GND 38 REFCLK4- GND 38 RSVD RSVD 38 b_mdi2p GND 38 GND AD12 39 GND REFCLK5+ 39 GND GND 39 b_mdi2n GND 39 AD15 AD10 40 RSVD-G REFCLK5-40 GND GND 40 GND b_mdi3p 40 AD13 GND 41 REFCLK6+ GND 41 GND GND 41 GND b_mdi3n 41 GND AD09 42 REFCLK6- GND 42 GND GND V +3.3V 42 AD11 C/BE0# 43 GND REFCLK7+ 43 GND GND V +3.3V 43 AD08 GND

43 4 PCI Express and PCI(-X) Interfaces PICMG 1.3 R0.9 x16 PCIe Connector A x8 PCIe Connector B x16 PCIe Connector C x8 PCIe Connector D Side B Side A Side B Side A Side B Side A Side B Side A 44 GND REFCLK V +12V V +3.3V 44 GND AD06 45 a_petp0 GND V +12V V +3.3V 45 AD07 AD05 46 a_petn0 GND V +12V V +3.3V 46 AD04 GND 47 GND a_perp V +12V V +3.3V 47 GND AD02 48 GND a_pern V +12V V +3.3V 48 AD03 AD01 49 a_petp1 GND V +12V V +3.3V 49 AD00 GND 50 a_petn1 GND V +3.3V 51 GND a_perp1 51 GND GND 52 GND a_pern1 52 GND GND 53 a_petp2 GND 53 GND GND 54 a_petn2 GND 54 GND GND 55 GND a_perp2 55 GND GND 56 GND a_pern2 56 GND GND 57 a_petp3 GND 57 GND GND 58 a_petn3 GND 58 GND GND 59 GND a_perp V +5V 60 GND a_pern V +5V 61 a_petp4 GND 61 +5V +5V 62 a_petn4 GND 62 +5V +5V 63 GND a_perp4 63 GND GND 64 GND a_pern4 64 GND GND 65 a_petp5 GND 65 GND GND 66 a_petn5 GND 66 GND GND 67 GND a_perp5 67 GND GND 68 GND a_pern5 68 GND GND 69 a_petp6 GND 69 GND GND 70 a_petn6 GND 70 GND GND 71 GND a_perp6 71 GND GND 72 GND a_pern6 72 GND GND 73 a_petp7 GND V +12V 74 a_petn7 GND V +12V 75 GND a_perp V +12V 76 GND a_pern V +12V 77 RSVD GND V +12V V +3.3V V +12V V +3.3V V +12V V +3.3V V +12V V +3.3V V +12V Vaux +3.3Vaux V +12V 33

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45 5 Physical Characteristics PICMG 1.3 R0.9 5 PHYSICAL CHARACTERISTICS 5.1 SHB Backside Component Height Restriction An SHB defines the backside of the board just the opposite of the PCI Express Card Electromechanical Spec. An SHB shall restrict maximum height of any component (conductive or non-conductive) on the backside to 7.62mm (0.3 ). Maximum height components on the rear of the board, should either be non-conductive, electrically isolated, or ground.

46 5 Physical Characteristics 5.2 Full-Size SHB The following figure shows the mechanical outline of a full-size SHB viewed from the primary component side. Figure 6 Full-Size SHB Mechanical Drawing

47 5 Physical Characteristics PICMG 1.3 R Half-Size SHB The following figure shows the mechanical outline of a half-size SHB viewed from the primary component side. Figure 7 Half-Size SHB Mechanical Drawing 37

48 5.4 Backplane Mechanicals 5 Physical Characteristics A backplane should follow one of the following mechanical drawings. Note that the PCIe and PCI(-X) connectors seen in Figures 5, 6, and 7 are for illustrative purposes only. Figure 8 13-Slot Backplane Mechanical Drawing

49 5 Physical Characteristics PICMG 1.3 R0.9 Figure 9 20-Slot Backplane Mechanical Drawing 39

50 Figure 10 2U Backplane Mechanical Drawing 5 Physical Characteristics Top Bottom

51 5 Physical Characteristics PICMG 1.3 R0.9 This page intentionally left blank. 41

52 6 Revision History PICMG 1.3 R0.9 6 REVISION HISTORY Revision 0.02 Revision 0.03 Revision 0.04 Revision 0.7 Revision 0.71 Revision 0.8 Revision 0.81 Revision 0.9 Initial concept. Added PCI(-X) and broke x8 PCIe into (1) x4 and (4) x1 s. Cleaned up PCI section for Connector D. Defined PCIe split on Connector A and B more clearly. Changed component side of the board to be the non-pci side of the SHB. Incorporated committee input and changed general format to be similar to standard PICMG layout. Miscellaneous clean-up, changed PCIe link configurations and added backplane dimensions. Updated dimension drawings, simulation information, defined PCIe clocking more clearly, clarified aux voltages, and miscellaneous clean-up. Updated Connectors A, B, and C pinouts. Removed 2 SATA and replaced with an ethernet connection.