Energy Metering IC with Integrated Oscillator and Positive Power Accumulation ADE7768

Transcription

1 Energy Metering IC with Integrated Oscillator and Positive Power Accumulation ADE7768 FEATURES On-chip oscillator as clock source High accuracy, supports 5 Hz/6 Hz IEC653- Less than.% error over a dynamic range of 5 to Supplies positive-only average real power on frequency outputs F and F High frequency output CF calibrates and supplies instantaneous, positive-only real power Logic output REVP indicates potential miswiring or negative power Direct drive for electromechanical counters and -phase stepper motors (F and F) Proprietary ADCs and DSPs provide high accuracy over large variations in environmental conditions and time On-chip power supply monitoring On-chip creep protection (no-load threshold) On-chip reference.45 V ( ppm/ C typical) with external overdrive capability Single 5 V supply, low power ( mw typical) Low cost CMOS process GENERAL DESCRIPTION The ADE7768 is a high accuracy, electrical energy metering IC. It is a pin reduction version of the ADE7755, enhanced with a precise oscillator circuit that serves as a clock source to the chip. The ADE7768 eliminates the cost of an external crystal or resonator, thus reducing the overall cost of a meter built with this IC. The chip directly interfaces with the shunt resistor. U.S. Patents 5,745,33; 5,76,67; 5,86,69; 5,87,469; others pending. The ADE7768 specifications surpass the accuracy requirements of the IEC653- standard. The AN-679 Application Note can be used as a basis for a description of an IEC636 (equivalent to IEC653-) low cost, watt-hour meter reference design. The only analog circuitry used in the ADE7768 is in the Σ-Δ ADCs and reference circuit. All other signal processing, such as multiplication and filtering, is carried out in the digital domain. This approach provides superior stability and accuracy over time and extreme environmental conditions. The ADE7768 supplies positive-only average real power information on the low frequency outputs, F and F. These outputs can be used to directly drive an electromechanical counter or interface with an MCU. The high frequency CF logic output, ideal for calibration purposes, provides instantaneous positive-only, real power information. The ADE7768 includes a power supply monitoring circuit on the VDD supply pin. The ADE7768 remains inactive until the supply voltage on VDD reaches approximately 4 V. If the supply falls below 4 V, the ADE7768 also remains inactive and the F, F, and CF outputs are in their nonactive modes. Internal phase matching circuitry ensures that the voltage and current channels are phase matched, while the HPF in the current channel eliminates dc offsets. An internal no-load threshold ensures that the ADE7768 does not exhibit creep when no load is present. When REVP is logic high, the ADE7768 does not generate any pulse on F, F, and CF. The ADE7768 comes in a 6-lead, narrow body SOIC package. FUNCTIONAL BLOCK DIAGRAM V DD AGND DGND 6 3 VP VN 3 + POWER SUPPLY MONITOR Σ-Δ ADC... ADE7768 MULTIPLIER SIGNAL PROCESSING BLOCK VN VP V REFERENCE Σ-Δ ADC 4kΩ... INTERNAL OSCILLATOR PHASE CORRECTION Φ HPF LPF DIGITAL-TO-FREQUENCY CONVERTER REF IN/OUT RCLKIN SCF S S REVP CF F F 533- Figure. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Specifications... 3 Timing Characteristics... 4 Absolute Maximum Ratings... 5 ESD Caution... 5 Terminology... 6 Pin Configuration and Function Descriptions... 7 Typical Performance Characteristics... 8 Functional Description... Theory of Operation... Power Supply Monitor... Internal Oscillator (OSC)... 4 Transfer Function... 4 Selecting a Frequency for an Energy Meter Application... 5 No-Load Threshold... 6 Negative Power Information... 6 Evaluation Board and Reference Design Board... 6 Outline Dimensions... 7 Ordering Guide... 7 Analog Inputs... Revision History 8/5 Sp to Rev. A Rev. A Page of

3 SPECIFICATIONS VDD = 5 V ± 5%, AGND = DGND = V, on-chip reference, RCLKIN = 6. kω,.5% ± 5 ppm/ C, TMIN to TMAX = 4 C to +85 C, unless otherwise noted. ADE7768 Table. Parameter Value Unit Test Conditions/Comments ACCURACY, Measurement Error on Channel V. % reading typ Channel V with full-scale signal (±65 mv), 5 C over a dynamic range 5 to, line frequency = 45 Hz to 65 Hz Phase Error Between Channels V Phase Lead 37 (PF =.8 Capacitive) ±. Degrees ( ) max V Phase Lag 6 (PF =.5 Inductive) ±. Degrees ( ) max AC Power Supply Rejection Output Frequency Variation (CF). % reading typ S = S =, V =. mv rms, V = 6.7 mv 5 Hz, ripple on VDD of mv Hz DC Power Supply Rejection Output Frequency Variation (CF) ±.3 % reading typ S = S =, V =. mv rms, V = 6.7 mv rms, VDD = 5 V ± 5 mv ANALOG INPUTS See the Analog Inputs section Channel V Maximum Signal Level ±3 mv max VP and VN to AGND Channel V Maximum Signal Level ±65 mv max VP and VN to AGND Input Impedance (DC) 3 kω min OSC = 45 khz, RCLKIN = 6. kω,.5% ± 5 ppm/ C Bandwidth ( 3 db) 7 khz nominal OSC = 45 khz, RCLKIN = 6. kω,.5% ± 5 ppm/ C ADC Offset Error, ±8 mv max See the Terminology and the Typical Performance Characteristics sections Gain Error ±4 % ideal typ External.5 V reference, V =. mv rms, V = 6.7 mv rms OSCILLATOR FREQUENCY (OSC) 45 khz nominal RCLKIN = 6. kω,.5% ± 5 ppm/ C Oscillator Frequency Tolerance ± % reading typ Oscillator Frequency Stability ±3 ppm/ C typ REFERENCE INPUT REFIN/OUT Input Voltage Range.65 V max.45 V nominal.5 V min.45 V nominal Input Capacitance pf max ON-CHIP REFERENCE.45 V nominal Reference Error ± mv max Temperature Coefficient ± ppm/ C typ LOGIC INPUTS 3 SCF, S, S Input High Voltage, VINH.4 V min VDD = 5 V ± 5% Input Low Voltage, VINL.8 V max VDD = 5 V ± 5% Input Current, IIN ± μa max Typically na, VIN = V to VDD Input Capacitance, CIN pf max LOGIC OUTPUTS 3 F and F Output High Voltage, VOH 4.5 V min ISOURCE = ma, VDD = 5 V, ISINK = ma, VDD = 5 V Output Low Voltage, VOL.5 V max CF Output High Voltage, VOH 4 V min ISOURCE = 5 ma, VDD = 5 V, ISINK = 5 ma, VDD = 5 V Output Low Voltage, VOL.5 V max Frequency Output Error, (CF) ± % ideal typ External.5 V reference, V =. mv rms, V = 6.7 mv rms Rev. A Page 3 of

4 Parameter Value Unit Test Conditions/Comments POWER SUPPLY For specified performance VDD 4.75 V min 5 V 5% 5.5 V max 5 V + 5% IDD 5 ma max Typically 4 ma See the Terminology section for an explanation of specifications. See the figures in the Typical Performance Characteristics section. 3 Sample tested during initial release and after any redesign or process change that may affect this parameter. TIMING CHARACTERISTICS VDD = 5 V ± 5%, AGND = DGND = V, on-chip reference, RCLKIN = 6. kω,.5% ± 5 ppm/ C, TMIN to TMAX = 4 C to +85 C, unless otherwise noted. Sample tested during initial release and after any redesign or process change that may affect this parameter. See Figure. Table. Parameter Specifications Unit Test Conditions/Comments t ms F and F pulse width (logic low) t See Table 6 sec Output pulse period. See the Transfer Function section. t3 / t sec Time between the F and F falling edges. t4, 9 ms CF pulse width (logic high). t5 See Table 7 sec CF pulse period. See the Transfer Function section. t6 μs Minimum time between the F and F pulses. The pulse widths of F, F, and CF are not fixed for higher output frequencies. See the Frequency Outputs section. The CF pulse is always 35 μs in high frequency mode. See the Frequency Outputs section and Table 7. t F t 6 t F t 3 t 4 t 5 CF 533- Figure. Timing Diagram for Frequency Outputs Rev. A Page 4 of

5 ABSOLUTE MAXIMUM RATINGS TA = 5 C, unless otherwise noted. Table 3. Parameter Value VDD to AGND.3 V to +7 V VDD to DGND.3 V to +7 V Analog Input Voltage to AGND, VP, VN, VP, and VN 6 V to +6 V Reference Input Voltage to AGND.3 V to VDD +.3 V Digital Input Voltage to DGND.3 V to VDD +.3 V Digital Output Voltage to DGND.3 V to VDD +.3 V Operating Temperature Range 4 C to +85 C Storage Temperature Range 65 C to +5 C Junction Temperature 5 C 6-Lead Plastic SOIC, Power Dissipation 35 mw θja Thermal Impedance 4.9 C/W Package Temperature Soldering See J-STD- JEDEC S standard (-layer) board data. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A Page 5 of

6 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7768 is defined by the following formula: Energy Registered by ADE7768 True Energy % Error = % True Energy Phase Error Between Channels The high-pass filter (HPF) in the current channel (Channel V) has a phase-lead response. To offset this phase response and equalize the phase response between channels, a phasecorrection network is also placed in Channel V. The phasecorrection network matches the phase to within. over a range of 45 Hz to 65 Hz, and. over a range 4 Hz to khz (see Figure 4 and Figure 5). Power Supply Rejection (PSR) This quantifies the ADE7768 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (5 V) is taken. A mv rms/ Hz signal is then introduced onto the supplies and a second reading is obtained under the same input signal levels. Any error introduced is expressed as a percentage of reading see the Measurement Error definition. For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. The supplies are then varied 5% and a second reading is obtained with the same input signal levels. Any error introduced is again expressed as a percentage of the reading. ADC Offset Error This refers to the small dc signal (offset) associated with the analog inputs to the ADCs. However, the HPF in Channel V eliminates the offset in the circuitry. Therefore, the power calculation is not affected by this offset. Frequency Output Error (CF) The frequency output error of the ADE7768 is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained from the ADE7768 transfer function. Gain Error The gain error of the ADE7768 is defined as the difference between the measured output of the ADCs (minus the offset) and the ideal output of the ADCs. The difference is expressed as a percentage of the ideal of the ADCs. Oscillator Frequency Tolerance The oscillator frequency tolerance of the ADE7768 is defined as the part-to-part frequency variation in terms of percentage at room temperature (5 C). It is measured by taking the difference between the measured oscillator frequency and the nominal frequency defined in the Specifications section. Oscillator Frequency Stability Oscillator frequency stability is defined as frequency variation in terms of the parts-per-million drift over the operating temperature range. In a metering application, the temperature range is 4 C to +85 C. Oscillator frequency stability is measured by taking the difference between the measured oscillator frequency at 4 C and +85 C and the measured oscillator frequency at +5 C. Rev. A Page 6 of

7 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin No. Mnemonic Description V DD VP VN 3 6 F 5 F 4 CF ADE7768 VN 4 TOP VIEW 3 DGND VP 5 (Not to Scale) REVP AGND 6 RCLKIN REF IN/OUT 7 S SCF 8 9 S Figure 3. Pin Configuration VDD Power Supply. This pin provides the supply voltage for the circuitry in the ADE7768. The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled with a μf capacitor in parallel with a nf ceramic capacitor., 3 VP, VN Analog Inputs for Channel V (Voltage Channel). These inputs provide a fully differential input pair. The maximum differential input voltage is ±65 mv for specified operation. Both inputs have internal ESD protection circuitry; an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage. 4, 5 VN, VP Analog Inputs for Channel V (Current Channel). These inputs are fully differential voltage inputs with a maximum signal level of ±3 mv with respect to the VN pin for specified operation. Both inputs have internal ESD protection circuitry and, in addition, an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage. 6 AGND This pin provides the ground reference for the analog circuitry in the ADE7768, that is, the ADCs and reference. This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground reference for all analog circuitry, such as antialiasing filters, current and voltage sensors, and so forth. For accurate noise suppression, the analog ground plane should be connected to the digital ground plane at only one point. A star ground configuration helps to keep noisy digital currents away from the analog circuits. 7 REFIN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of.45 V and a typical temperature coefficient of ppm/ C. An external reference source may also be connected at this pin. In either case, this pin should be decoupled to AGND with a μf tantalum capacitor and a nf ceramic capacitor. The internal reference cannot be used to drive an external load. 8 SCF Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF. See Table 7. 9, S, S These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion. With this logic input, designers have greater flexibility when designing an energy meter. See the Selecting a Frequency for an Energy Meter Application section. RCLKIN To enable the internal oscillator as a clock source to the chip, a precise low temperature drift resistor at a nominal value of 6. kω must be connected from this pin to DGND. REVP This logic output goes high when negative power is detected, that is, when the phase angle between the voltage and current signals is greater than 9. This output is not latched and is reset when positive power is once again detected. The output goes high or low at the same time that a pulse is issued on CF. 3 DGND This pin provides the ground reference for the digital circuitry in the ADE7768, that is, the multiplier, filters, and digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The digital ground plane is the ground reference for all digital circuitry, such as counters (mechanical and digital), MCUs, and indicator LEDs. For accurate noise suppression, the analog ground plane should be connected to the digital ground plane at one point only a star ground. 4 CF Calibration Frequency Logic Output. The CF logic output provides instantaneous, positive-only real power information. This output is intended for calibration purposes. See the SCF pin description. 5, 6 F, F Low Frequency Logic Outputs. F and F supply average positive-only real power information. The logic outputs can be used to directly drive electromechanical counters and -phase stepper motors. See the Transfer Function section Rev. A Page 7 of

8 TYPICAL PERFORMANCE CHARACTERISTICS V DD V 4A TO 4mA 35μΩ 6kΩ Ω + 5nF Ω 5nF Ω 5nF Ω 5nF V DD VP F 6 U F 5 ADE7768 CF 4 VN VP VN nf REVP 6.kΩ RCLKIN S 8Ω + μf U3 4 K7 3 K8 PS5- V DD kω + μf nf 7 S REF IN/OUT SCF AGND DGND nf nf nf Figure 4. Test Circuit for Performance Curves..8 PF = ON-CHIP REFERENCE..8 PF = EXTERNAL REFERENCE.6.6 ERROR (% of Reading) C +5 C 4 C ERROR (% of Reading) C 4 C +5 C.8.. CURRENT CHANNEL (% of Full Scale) Figure 5. Error as a % of Reading over Temperature with On-Chip Reference (PF = ) CURRENT CHANNEL (% of Full Scale) Figure 7. Error as a % of Reading over Temperature with External Reference (PF = ) PF =.5 IND ON-CHIP REFERENCE..8 PF =.5 IND EXTERNAL REFERENCE.6 4 C, PF =.5 IND.6 ERROR (% of Reading) C, PF =.5 IND +5 C, PF = +5 C, PF =.5 IND ERROR (% of Reading) C, PF =.5 IND +5 C, PF =.5 IND +5 C, PF = C, PF =.5 IND CURRENT CHANNEL (% of Full Scale) CURRENT CHANNEL (% of Full Scale) Figure 6. Error as a % of Reading over Temperature with On-Chip Reference (PF =.5 IND) Figure 8. Error as a % of Reading over Temperature with External Reference (PF =.5 IND) Rev. A Page 8 of

9 ERROR (% of Reading) PF =.5 IND PF = PF =.5 CAP FREQUENCY 4 3 DISTRIBUTION CHARACTERISTICS MEAN =.4788 SDs = EXTERNAL REFERENCE MIN =.993 TEMPERATURE = 5 C MAX = NO. OF POINTS = FREQUENCY (Hz) CHANNEL V OFFSET (mv) Figure 9. Error as a % of Reading over Input Frequency Figure. Channel V Offset Distribution ERROR (% of Reading) PF = ON-CHIP REFERENCE 5.5V 5V 4.75V FREQUENCY DISTRIBUTION CHARACTERISTICS MEAN = SDs =.4699 MIN = MAX = +.69 NO. OF POINTS = EXTERNAL REFERENCE TEMPERATURE = 5 C CURRENT CHANNEL (% of Full Scale) CHANNEL V OFFSET (mv) Figure. PSR with On-Chip Reference, PF = Figure 3. Channel V Offset Distribution ERROR (% of Reading) PF = EXTERNAL REFERENCE 5.5V 5V 4.75V FREQUENCY DISTRIBUTION CHARACTERISTICS MEAN = % SDs =.55% EXTERNAL REFERENCE MIN =.79% TEMPERATURE = 5 C MAX = +6.8% NO. OF POINTS = CURRENT CHANNEL (% of Full Scale) DEVIATION FROM MEAN (%) Figure. PSR with External Reference, PF = Figure 4. Part-to-Part CF Deviation from Mean Rev. A Page 9 of

10 FUNCTIONAL DESCRIPTION THEORY OF OPERATION The two ADCs in the ADE7768 digitize the voltage signals from the current and voltage sensors. These ADCs are 6-bit Σ-Δs with an oversampling rate of 45 khz. This analog input structure greatly simplifies sensor interfacing by providing a wide dynamic range for direct connection to the sensor and by simplifying the antialiasing filter design. A high-pass filter in the current channel removes any dc component from the current signal. This eliminates any inaccuracies in the real power calculation due to offsets in the voltage or current signals. The real power calculation is derived from the instantaneous power signal. The instantaneous power signal is generated by a direct multiplication of the current and voltage signals. To extract the real power component (the dc component), the instantaneous power signal is low-pass filtered. Figure 5 illustrates the instantaneous real power signal and shows how the real power information can be extracted by low-pass filtering the instantaneous power signal. In the ADE7768, this signal is compared to and only positive real power is accumulated for F, F, and CF pulse outputs. This scheme correctly calculates real power for sinusoidal current and voltage waveforms at all power factors. All signal processing is carried out in the digital domain for superior stability over temperature and time. CH CH ADC ADC HPF MULTIPLIER LPF DIGITAL-TO- FREQUENCY F F DIGITAL-TO- FREQUENCY CF MAGNITUDE Wh MAGNITUDE W ACTIVE ENERGY INSTANTANEOUS POWER Figure 6. Positive-Only Energy Accumulation Power Factor Considerations The method used to extract the real power information from the instantaneous power signal (that is, by low-pass filtering) is still valid even when the voltage and current signals are not in phase. Figure 7 displays the unity power factor condition and a displacement power factor (DPF) =.5 (a current signal lagging the voltage by 6 ). Assuming that the voltage and current waveforms are sinusoidal, the real power component of the instantaneous power signal (that is, the dc term) is given by V I cos ( 6 ) () This is the correct real power calculation. INSTANTANEOUS POWER SIGNAL POWER INSTANTANEOUS REAL POWER SIGNAL INSTANTANEOUS POWER SIGNAL p(t) INSTANTANEOUS REAL POWER SIGNAL V I V TIME TIME TIME Figure 5. Signal Processing Block Diagram The low frequency outputs (F and F) are generated by accumulating positive-only real power information. This low frequency inherently means a long accumulation time between output pulses. Consequently, the resulting output frequency is proportional to the average positive-only real power. This average positive-only real power information is then accumulated (by a counter) to generate real energy information (see Figure 6). Conversely, due to its high output frequency and shorter integration time, the CF output frequency is proportional to the instantaneous positive-only real power. This is useful for system calibration, which can be done faster under steady load conditions V I COS (6 ) POWER V CURRENT VOLTAGE INSTANTANEOUS POWER SIGNAL VOLTAGE 6 INSTANTANEOUS REAL POWER SIGNAL CURRENT Figure 7. DC Component of Instantaneous Power Signal Conveys Real Power Information, PF < TIME Rev. A Page of

11 Nonsinusoidal Voltage and Current The real power calculation method also holds true for nonsinusoidal current and voltage waveforms. All voltage and current waveforms in practical applications have some harmonic content. Using the Fourier transform, instantaneous voltage and current waveforms can be expressed in terms of their harmonic content. + Vh sin( hωt αh h v ( t) = V + ) () where: v(t) is the instantaneous voltage. V is the average value. Vh is the rms value of voltage harmonic h. α h is the phase angle of the voltage harmonic. h h o ( i( t) = I + I sin hωt + β ) (3) O where: i(t) is the instantaneous current. I is the dc component. Ih is the rms value of current harmonic h. is the phase angle of the current harmonic. β h Using Equations and 3, the real power (P) can be expressed in terms of its fundamental real power (P) and harmonic real power (PH) as P = P + PH where: P = V φ and I = α β P H h h h cos φ = V Ih cos φh φ = α β h h In Equation 5, a harmonic real power component is generated for every harmonic, provided that harmonic is present in both the voltage and current waveforms. The power factor calculation has previously been shown to be accurate in a pure sinusoid. Therefore, the harmonic real power must also correctly account for the power factor, because it is made up of a series of pure sinusoids. Note that the input bandwidth of the analog inputs is 7 khz at the nominal internal oscillator frequency of 45 khz. h (4) (5) ANALOG INPUTS Channel V (Current Channel) The voltage output from the current sensor is connected to the ADE7768 here. Channel V is a fully differential voltage input. VP is the positive input with respect to VN. The maximum peak differential signal on Channel V should be less than ±3 mv ( mv rms for a pure sinusoidal signal) for specified operation. +3mV V CM 3mV V DIFFERENTIAL INPUT ±3mV MAX PEAK COMMON-MODE ±6.5mV MAX AGND V V CM VP VN Figure 8. Maximum Signal Levels, Channel V Figure 8 shows the maximum signal levels on VP and VN. The maximum differential voltage is ±3 mv. The differential voltage signal on the inputs must be referenced to a common mode, such as AGND. The maximum common-mode signal is ±6.5 mv. Channel V (Voltage Channel) The output of the line voltage sensor is connected to the device at this analog input. Channel V is a fully differential voltage input with a maximum peak differential signal of ±65 mv. Figure 9 shows the maximum signal levels that can be connected to the ADE7768 Channel V. +65mV V CM 65mV V DIFFERENTIAL INPUT ±65mV MAX PEAK COMMON-MODE ±5mV MAX AGND V V CM VP VN Figure 9. Maximum Signal Levels, Channel V Channel V is usually driven from a common-mode voltage, that is, the differential voltage signal on the input is referenced to a common mode (usually AGND). The analog inputs of the ADE7768 can be driven with common-mode voltages of up to 5 mv with respect to AGND. However, best results are achieved using a common mode equal to AGND Rev. A Page of

12 Typical Connection Diagrams Figure shows a typical connection diagram for Channel V. A shunt is the current sensor selected for this example because of its low cost compared to other current sensors, such as the current transformer (CT). This IC is ideal for low current meters. SHUNT R F ±3mV R F AGND PHASE NEUTRAL VP C F VN C F Figure. Typical Connection for Channel V Figure shows a typical connection for Channel V. Typically, the ADE7768 is biased around the phase wire, and a resistor divider is used to provide a voltage signal that is proportional to the line voltage. Adjusting the ratio of RA, RB, B and RF is also a convenient way of carrying out a gain calibration on a meter. R A * NEUTRAL PHASE R B R F C F *R A >> R B + R F ±65mV R F C F VP VN Figure. Typical Connections for Channel V POWER SUPPLY MONITOR The ADE7768 contains an on-chip power supply monitor. The power supply (VDD) is continuously monitored by the ADE7768. If the supply is less than 4 V, the ADE7768 becomes inactive. This is useful to ensure proper device operation at power-up and power-down. The power supply monitor has built-in hysteresis and filtering, which provide a high degree of immunity to false triggering from noisy supplies. In Figure, the trigger level is nominally set at 4 V. The tolerance on this trigger level is within ±5%. The power supply and decoupling for the part should be such that the ripple at VDD does not exceed 5 V ± 5%, as specified for normal operation HPF and Offset Effects Figure 3 shows the effect of offsets on the real power calculation. As can be seen, offsets on Channel V and Channel V contribute a dc component after multiplication. Because this dc component is extracted by the LPF and used to generate the real power information, the offsets contribute a constant error to the real power calculation. This problem is easily avoided by the built-in HPF in Channel V. By removing the offsets from at least one channel, no error component can be generated at dc by the multiplication. Error terms at the line frequency (ω) are removed by the LPF and the digital-to-frequency conversion (see the Digital-to-Frequency Conversion section). Equation 6 shows how the power calculation is affected by the dc offsets in the current and voltage channels. V cos ( ω t) + V } { I cos ( ωt) + I } (6) { OS OS V I = + VOS IOS + VOS I cos ( ωt) + IOS V cos ( ωt) V I + cos ( ωt) V OS I OS V I DC COMPONENT (INCLUDING ERROR TERM) IS EXTRACTED BY THE LPF FOR REAL POWER CALCULATION I OS V V OS I FREQUENCY (RAD/s) Figure 3. Effect of Channel Offset on the Real Power Calculation The HPF in Channel V has an associated phase response that is compensated for on chip. Figure 4 and Figure 5 show the phase error between channels with the compensation network activated. The ADE7768 is phase compensated up to khz as shown. This ensures correct active harmonic power calculation even at low power factors V DD 5V 4V V INTERNAL ACTIVATION TIME INACTIVE ACTIVE INACTIVE Figure. On-Chip Power Supply Monitor 533- PHASE (Degrees) FREQUENCY (Hz) Figure 4. Phase Error Between Channels ( Hz to khz) Rev. A Page of 533-3

13 PHASE (Degrees) FREQUENCY (Hz) Figure 5. Phase Error Between Channels (4 Hz to 7 Hz) Digital-to-Frequency Conversion As previously described, the digital output of the low-pass filter after multiplication contains the positive-only real power information. However, because this LPF is not an ideal brick wall filter implementation, the output signal also contains attenuated components at the line frequency and its harmonics, that is, cos(hωt) where h =,, 3,... and so on. The magnitude response of the filter is given by H ( f ) = (7) f For a line frequency of 5 Hz, this gives an attenuation of the ω ( Hz) component of approximately db. The dominating harmonic is twice the line frequency (ω) due to the instantaneous power calculation. Figure 6 shows the instantaneous positive-only real power signal at the output of the LPF that still contains a significant amount of instantaneous power information, that is, cos(ωt). This signal is then passed to the digital-to-frequency converter where it is compared to and only positive real power is integrated (accumulated) over time to produce an output frequency. The accumulation of the signal suppresses or averages out any non-dc components in the instantaneous positive-only real power signal. The average value of a sinusoidal signal is. Thus, the frequency generated by the ADE7768 is proportional to the average positive-only real power. Figure 6 shows the digital-tofrequency conversion for steady load conditions, that is, the constant voltage and current MULTIPLIER V I V I LPF LPF TO EXTRACT REAL POWER (DC TERM) COS (ω) ATTENUATED BY LPF DIGITAL-TO- FREQUENCY F F DIGITAL-TO- FREQUENCY ω ω FREQUENCY (RAD/s) INSTANTANEOUS REAL POWER SIGNAL (FREQUENCY DOMAIN) CF FREQUENCY FREQUENCY F CF TIME TIME Figure 6. Positive-Only, Real Power-to-Frequency Conversion In Figure 6, the frequency output CF varies over time, even under steady load conditions. This frequency variation is primarily due to the cos(ωt) component in the instantaneous positive-only real power signal. The output frequency on CF can be up to 48 times higher than the frequency on F and F. This higher output frequency is generated by accumulating the instantaneous positive-only real power signal over a much shorter time while converting it to a frequency. This shorter accumulation period means less averaging of the cos(ωt) component. Consequently, some of this instantaneous power signal passes through the digital-to-frequency conversion. This is not a problem in the application. Where CF is used for calibration purposes, the frequency should be averaged by the frequency counter, which removes any ripple. If CF is used to measure energy, such as in a microprocessor-based application, the CF output should also be averaged to calculate power. Because the F and F outputs operate at a much lower frequency, much more averaging of the instantaneous positiveonly real power signal is carried out. The result is a greatly attenuated sinusoidal content and a virtually ripple-free frequency output. Connecting to a Microcontroller for Energy Measurement The easiest way to interface the ADE7768 to a microcontroller is to use the CF high frequency output with the output frequency scaling set to 48 F, F. This is done by setting SCF = and S = S = (see Table 7). With full-scale ac signals on the analog inputs, the output frequency on CF is approximately.867 khz. Figure 7 illustrates one scheme that could be used to digitize the output frequency and carry out the necessary averaging mentioned in the previous section Rev. A Page 3 of

14 AVERAGE FREQUENCY CF FREQUENCY RIPPLE ±% temperature drift to ensure stability and linearity of the chip. The oscillator frequency is inversely proportional to the RCLKIN, as shown in Figure 8. Although the internal oscillator operates when used with RCLKIN values between 5.5 kω and kω, choosing a value within the range of the nominal value, as shown in Figure 8, is recommended. TIME 49 ADE7768 CF MCU COUNTER TIMER Figure 7. Interfacing the ADE7768 to an MCU As shown in Figure 7, the frequency output CF is connected to an MCU counter or port. This counts the number of pulses in a given integration time, which is determined by an MCU internal timer. The average power proportional to the average frequency is given by Counter Average Frequency = Average Power = (8) Time The energy consumed during an integration period is given by Counter Energy = Average Power Time = Time = Counter Time For the purpose of calibration, this integration time could be seconds to seconds, to accumulate enough pulses to ensure correct averaging of the frequency. In normal operation, the integration time could be reduced to second or seconds, depending, for example, on the required update rate of a display. With shorter integration times on the MCU, the amount of energy in each update may still have some small amount of ripple, even under steady load conditions. However, over a minute or more the measured energy has no ripple. Power Measurement Considerations Calculating and displaying power information always has some associated ripple, which depends on the integration period used in the MCU to determine average power and also on the load. For example, at light loads, the output frequency may be Hz. With an integration period of seconds, only about pulses are counted. The possibility of missing one pulse always exists, because the ADE7768 output frequency is running asynchronously to the MCU timer. This results in a -in- or 5% error in the power measurement. When REVP is logic high, the ADE7768 does not generate any pulse on F, F, and CF. INTERNAL OSCILLATOR (OSC) The nominal internal oscillator frequency is 45 khz when used with RCLKIN, with a nominal value of 6. kω. The frequency outputs are directly proportional to the oscillator frequency, thus RCLKIN must have low tolerance and low (9) FREQUENCY (khz) RESISTANCE (kω) Figure 8. Effect of RCLKIN on Internal Oscillator Frequency (OSC) TRANSFER FUNCTION Frequency Outputs F and F The ADE7768 calculates the product of two voltage signals (on Channel V and Channel V) and then low-pass filters this product to extract positive-only real power information. This positive-only real power information is then converted to a frequency. The frequency information is output on F and F in the form of active low pulses. The pulse rate at these outputs is relatively low for example,.75 Hz maximum for ac signals with S = S = (see Table 6). This means that the frequency at these outputs is generated from positive-only real power information accumulated over a relatively long period of time. The result is an output frequency that is proportional to the average positive-only real power. The averaging of the positiveonly real power signal is implicit to the digital-to-frequency conversion. The output frequency or pulse rate is related to the input voltage signals by the following equation: V Vrms F 4 Freq = () rms VREF where: Freq is the output frequency on F and F (Hz). Vrms is the differential rms voltage signal on Channel V (V). Vrms is the differential rms voltage signal on Channel V (V). VREF is the reference voltage (.45 V ± mv) (V). F 4 are one of four possible frequencies selected by using the S and S logic inputs (see Table 5) Rev. A Page 4 of

15 Table 5. F 4 Frequency Selection S S OSC Relation F 4 at Nominal OSC (Hz) OSC/9.86 OSC/8.7 OSC/ OSC/ F 4 is a binary fraction of the internal oscillator frequency. Values are generated using the nominal frequency of 45 khz. Example In this example, with ac voltages of ±3 mv peak applied to V and ±65 mv peak applied to V, the expected output frequency is calculated as follows: F 4 = OSC/ 9 Hz, S = S = Vrms =.3/ V Vrms =.65/ V VREF =.45 V (nominal reference value) Note that if the on-chip reference is used, actual output frequencies may vary from device to device due to the reference tolerance of ± mv F Freq = =.4 F.45 =.75 () Table 6. Maximum Output Frequency on F and F S S OSC Relation Max Frequency or AC Inputs (Hz).4 F.75.4 F.35.4 F3.7.4 F4.4 Values are generated using the nominal frequency of 45 khz. Frequency Output CF The pulse output CF (calibration frequency) is intended for calibration purposes. The output pulse rate on CF can be up to 48 times the pulse rate on F and F. The lower the F 4 frequency selected, the higher the CF scaling (except for the high frequency mode SCF =, S = S = ). Table 7 shows how the two frequencies are related, depending on the states of the logic inputs S, S, and SCF. Due to its relatively high pulse rate, the frequency at the CF logic output is proportional to the instantaneous positive-only real power. As with F and F, CF is derived from the output of the low-pass filter after multiplication. However, because the output frequency is high, this positive-only real power information is accumulated over a much shorter time. Therefore, less averaging is carried out in the digital-to-frequency conversion. With much less averaging of the positive-only real power signal, the CF output is much more responsive to power fluctuations (see the signal processing block diagram in Figure 5). Table 7. Maximum Output Frequency on CF SCF S S CF Max for AC Signals (Hz) 8 F, F =.4 64 F, F =. 64 F, F =.4 3 F, F =. 3 F, F =.4 6 F, F =. 6 F, F =.4 48 F, F =.867 khz Values are generated using the nominal frequency of 45 khz. SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION As shown in Table 5, the user can select one of four frequencies. This frequency selection determines the maximum frequency on F and F. These outputs are intended for driving an energy register (electromechanical or other). Because only four different output frequencies can be selected, the available frequency selection has been optimized for a meter constant of imp/kwh with a maximum current of between A and A. Table 8 shows the output frequency for several maximum currents (IMAX) with a line voltage of V. In all cases, the meter constant is imp/kwh. Table 8. F and F Frequency at imp/kwh IMAX (A) F and F (Hz) The F 4 frequencies allow complete coverage of this range of output frequencies (F, F). When designing an energy meter, the nominal design voltage on Channel V (voltage) should be set to half-scale to allow calibration of the meter constant. The current channel should also be no more than half scale when the meter sees maximum load. This allows overcurrent signals and signals with high crest factors to be accommodated. Table 9 shows the output frequency on F and F when both analog inputs are half scale. The frequencies in Table 9 align very well with those in Table 8 for maximum load. Table 9. F and F Frequency with Half-Scale AC Inputs Frequency on F and F S S F 4 (Hz) CH and CH Half-Scale AC Input.86.5 F.44 Hz.7.5 F.88 Hz F3.76 Hz F4.35 Hz Values are generated using the nominal frequency of 45 khz. Rev. A Page 5 of

16 When selecting a suitable F 4 frequency for a meter design, the frequency output at IMAX (maximum load) with a meter constant of imp/kwh should be compared with Column 4 of Table 9. The closest frequency in Table 9 determines the best choice of frequency (F 4). For example, if a meter with a maximum current of 5 A is being designed, the output frequency on F and F with a meter constant of imp/kwh is.53 Hz at 5 A and V (from Table 8). In Table 9, the closest frequency to.53 Hz in Column 4 is.76 Hz. Therefore, as shown in Table 5, F3 (3.43 Hz) is selected for this design. Frequency Outputs Figure shows a timing diagram for the various frequency outputs. The F and F outputs are the low frequency outputs that can be used to directly drive a stepper motor or electromechanical impulse counter. The F and F outputs provide two alternating low frequency pulses. The F and F pulse widths (t) are set such that if they fall below 4 ms (.4 Hz), they are set to half of their period. The maximum output frequencies for F and F are shown in Table 6. The high frequency CF output is intended for communications and calibration purposes. CF produces a 9-ms-wide active high pulse (t4) at a frequency proportional to active power. The CF output frequencies are given in Table 7. As with F and F, if the period of CF (t5) falls below 8 ms, the CF pulse width is set to half the period. For example, if the CF frequency is Hz, the CF pulse width is 5 ms. When high frequency mode is selected (SCF =, S = S = ), the CF pulse width is fixed at 35 μs. Therefore, t4 is always 35 μs, regardless of output frequency on CF. For example, for an energy meter with a meter constant of imp/kwh on F, F using F3 (3.43 Hz), the minimum output frequency at F or F would be.44% of 3.43 Hz or Hz. This would be.68 3 Hz at CF (3 F Hz) when SCF = S =, S =. In this example, the no-load threshold would be equivalent to 3 W of load or a start-up current of 3.7 ma at V. Compare this value to the IEC653- specification which states that the meter must start up with a load equal to or less than.4% Ib. For a 5 A (Ib) meter,.4% of Ib is equivalent to ma. NEGATIVE POWER INFORMATION The ADE7768 detects when the current and voltage channels have a phase shift greater than 9. This mechanism can detect an incorrect meter connection or the generation of negative power. The REVP pin output goes active high when negative power is detected and active low if positive power is detected. The REVP pin output changes state as a pulse is issued on CF. EVALUATION BOARD AND REFERENCE DESIGN BOARD An evaluation board can be used to verify the functionality and the performance of the ADE7768. Download documentation for the board from In addition, the reference design board ADE7768ARN-REF and Application Note AN-679 can be used in the design of a low cost watt-hour meter that surpasses IEC653- accuracy specifications. Download the application note from NO-LOAD THRESHOLD The ADE7768 includes a no-load threshold and start-up current feature that eliminates any creep effects in the meter. The ADE7768 is designed to issue a minimum output frequency. Any load generating a frequency lower than this minimum frequency does not cause a pulse to be issued on F, F, or CF. The minimum output frequency is given as.44% for each of the F 4 frequency selections (see Table 5). Rev. A Page 6 of

17 OUTLINE DIMENSIONS. (.3937) 9.8 (.3858) 4. (.575) 3.8 (.496) (.44) 5.8 (.83).5 (.98). (.39) COPLANARITY..7 (.5) BSC.75 (.689).35 (.53).5 (.) SEATING.3 (.) PLANE.5 (.98).7 (.67) 8.5 (.97) 45.5 (.98).7 (.5).4 (.57) COMPLIANT TO JEDEC STANDARDS MS--AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 9. 6-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-6) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Temperature Range Package Description Package Option ADE7768AR 4 C to +85 C 6-Lead Standard Small Outline Package [SOIC_N] R-6 ADE7768AR-RL 4 C to +85 C 6-Lead Standard Small Outline Package [SOIC_N] REEL R-6 ADE7768ARZ 4 C to +85 C 6-Lead Standard Small Outline Package [SOIC_N] R-6 ADE7768ARZ-RL 4 C to +85 C 6-Lead Standard Small Outline Package [SOIC_N] REEL R-6 ADE7768AR-REF Reference Board EVAL-ADE7768EB Evaluation Board Z = Pb-free part. Rev. A Page 7 of

18 NOTES Rev. A Page 8 of

19 NOTES Rev. A Page 9 of

20 NOTES 5 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D533 8/5(A) Rev. A Page of