EST7502B PC Power Supply PWM with Supervisor
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1 GENERAL DESCRIPTION The EST7502B is a pulse width modulation (PWM) control circuit with complete protection circuits for used in the SMPS (Switched Mode Power Supply). It contains various functions, which are Over Voltage Protection, Under Voltage Protection, Power Good Output (PGO), Remote On/Off control and etc. It can minimize external components of switching power supply systems in personal computer. Over Voltage Protection (OVP) monitors 3.3V, 5V, 12V and PT input voltage level. Under Voltage Protection (UVP) monitors 3.3V, 5V and 12V input voltage level. Power Good Output monitors the voltage level of power supply. FEATURES Complete PWM Control and Protection Circuitry Over Voltage Protection for 3.3V / 5V / 12V / PT Under Voltage Protection for 3.3V / 5V / 12V 280ms PG Time Delay Power Good Output is Open Drain Output PWM Control Output are Open Drain Output 280 ms Time Delay for UVP Remote ON/OFF function De bounce Time Soft-Start function built-in 16 Pin Dual In line Package PIN CONFIGURATION V VADJ V OPNEGIN V OPOUT PT 4 13 VCC GND 5 12 DET RT 6 11 PG C SS C2 8 9 ORDERING INFORMATION ORDER NUMBER Package Shipping Top Marking EST7502B DIP V2
2 PIN DESCRIPTION Pin No. Pin Name TYPE FUNCTION 1 V33 I OVP/UVP input FOR 3.3V. 2 V5 I OVP/UVP input for 5V. 3 V12 I OVP/UVP input for 12V. 4 PT I Extra OVP protection input. 5 GND P Ground. 6 RT O Oscillation frequency set by external resistor. 7 C1 O PWM open drain output 1. 8 C2 O PWM open drain output 2. 9 I Remote on/off input. = low that means the main SMPS is turned-on. = high, the main SMPS is turned-off. 10 SS O Soft start function set by external capacitor. 11 PG O Power good signal. PG= high means power good. PG= low means power fail. 12 DET I Extra protection input. 13 VCC P Supply voltage. 14 OPOUT O OP compensation output. 15 OPNEGIN I OP compensation negative input. 16 VADJ I OP compensation positive input, feedback voltage sense input V2
3 BLOCK DIAGRAM [1] V33 - UV [2] V5 - UV [3] V12 - UV UVP 110us 280ms delay - OV - OV OVP 510us IN CLR OUT S R Q - OV - OV [4] PT 0.62V - 280ms delay QOUT 5K PG [11] IN OUT [9] [12] DET 0.62V - 36mS Delay 4.5mS Delay ONF ON Vss SS [10] [6] [16] [15] RT VADJ OPNEGIN 2.45V ERROR AMP - OSC CLR PWM CONTROL PWMCMP - D C Q QN C1 C2 [7] [8] [14] OPOUT - DETCMP SOFT_START CONTROLLER ABSOLUTE MAXIMUM RATINGS, VCC=5.5V CHARACTERISTICS SYMBOL VALUE Unit Supply voltage VCC 5.5 V Drain output voltage Vcc1, Vcc2 5.5 V Drain output current Icc1, Icc2 200 ma Power dissipation Pd 200 mw Operating temperature Topr -20 ~ 85 Storage temperature Tstg -65 ~ V2
![45V ERROR AMP - OSC CLR PWM CONTROL PWMCMP - D C Q QN C1 C2 [7] [8] [14] OPOUT - DETCMP SOFT_START CONTROLLER ABSOLUTE MAXIMUM RATINGS, VCC=5.](/docs-images/47/20968986/images/page_3.jpg "5V CHARACTERISTICS SYMBOL VALUE Unit Supply voltage VCC 5.5 V Drain output voltage Vcc1, Vcc2 5.")
4 ELECTRICALCHARACTERISTICS,TA=25, V CC =5V, CHARACTERISTICS SYMBOL TEST CONDITION Min. Typ. Max. Unit ERROR AMP SECTION OPEN LOOP VOLTAGE GAIN 0.5V ~ 3.5V db CROSS OVER POINT 0dB 1000 KHZ OPNEG BIAS VOLTAGE OPNEG OPEN V POWER SUPPLY REJECTION RATIO PSRR 45 db OUTPUT SECTION OUTPUT SATURATION VOLTAGE Vdssat Id=200mA V DRAIN OFF-STATE CURRENT Idoff Vcc=Vd=Vs=0V 2 10 ua RISING TIME Tr ns FALLING TIME Tf ns PROTECTION SECTION OVER VOLTAGE PROTECTION (OVP) V V V V V V PT V Tg.ov 510 us UNDER VOLTAGE PROTECTION V V (UVP) V V V V Tg.uv 120 us UVP DISABLE VOLTAGE PT V UVP DELAY TIME Td.uvp ms OTE ON/OFF SECTION HIGH INPUT VOLTAGE Vremh 1.8 V LOW INPUT VOLTAGE Vreml 0.7 V PULL HIGH VOLTAGE Vremo V DELAY TIME Td on/off 40 ms POWER GOOD SECTION DETECT INPUT VOLTAGE Vdet 0.68 V PG OUTPUT PULL UP RESISTOR Rpup, pg 5 KΩ PG OUTPUT LOAD RESISTOR Rpg KΩ PG DELAY TIME ms SINK CURRENT Ipg.sink VPG=0.2V 10 ma SOFT START SECTION SINK CURRENT OF SS Iss.sink RT=100KΩ 15 ua SOURCE CURRENT OF SS Iss.source 310 ua VCC Under Voltage Lockout(UVLO) Start-up voltage 4.2 V TOTAL DEVICE STANDBY SUPPLY CURRENT Icc =5V ma OSCILLATION SECTION OSCILLATION FREQUENCY Fosc RT=100KΩ KHZ V2
5 APPLICATION NOTE 1. Input impedance: Pin No. Pin Name Input impedance 1 V33 52KΩ 2 V5 81KΩ 3 V12 52KΩ 4 PT 24 KΩ4.6 KΩ 2. Sawtooth OSC. Function: 3.OTE ON/OFF: ONF trem trem ON toff toff SS V2
6 4. Under Voltage Protection Delay Time: ON UVP td,uvp 5. Pulse Width Modulation Block: The output pulse width modulation is generated by comparison of the saw tooth waveform from the capacitor C T to the feedback of the voltage. Therefore, an increase in feedback control signal amplitude cause a linear decrease of the output pulse width. Also, the SS(DTC and Soft-Start) limits the output pulse width. The timing diagram is shown as below: CT DTC PWM OUT FF-CLK FF-Q FF-QN C1 C2 6. The function of PT : This signal is prepared for extra OVP/OPP (V PT > 1.28V) or another Disable Under Voltage Protection function (V PT < 0.62V) V2
7 7. Reference Application Circuit: 8. In some application power system, adding an external resistor (R9) could reduce the peak value spike from the environments to pin 9 () and avoid pin 9 ( ) damaged by the external noise. EXTERNAL DIMENSIONS DIM INCHES MILLIMETERS MIN MAX MIN MAX A B C D F G 0.100BSC 2.54BSC H 0.050BSC 1.27BSC J K L M S DIP-16 Outline Dimensions V2
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