Ultra-Low Noise, Precision OPERATIONAL AMPLIFIERS

Transcription

1 OPA7 OPA7 OPA7 OPA7 Ultra-Low Noise, Precision OPERATIONAL AMPLIFIERS SBOS5B JANUARY 9 REVISED FEBRUARY 5 FEATURES LOW NOISE:.5nV/ Hz max at khz LOW OFFSET: µv max LOW DRIFT:.µV/ C HIGH OPEN-LOOP GAIN: 7dB min HIGH COMMON-MODE REJECTION: db min HIGH POWER-SUPPLY REJECTION: 9dB min FITS OP-7, OP-5, AD5, AND AD57 SOCKETS APPLICATIONS PRECISION INSTRUMENTATION DATA ACQUISITION TEST EQUIPMENT PROFESSIONAL AUDIO EQUIPMENT TRANSDUCER AMPLIFIERS RADIATION HARD EQUIPMENT DESCRIPTION The OPA7 and OPA7 are ultra-low noise, high-precision monolithic operational amplifiers. Laser-trimmed thin-film resistors provide excellent long-term voltage offset stability and allow superior voltage offset compared to common zener-zap techniques. A unique bias current cancellation circuit allows bias and offset current specifications to be met over the full 55 C to +5 C temperature range. The OPA7 is internally compensated for unity-gain stability. The decompensated OPA7 requires a closed-loop gain 5. The Texas Instrument OPA7 and OPA7 are improved replacements for the industry-standard OP-7 and OP-7. Trim Trim 7 +V CC In +In V CC Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 9-5, Texas Instruments Incorporated

2 ABSOLUTE MAXIMUM RATINGS () Supply Voltage... ±V Internal Power Dissipation ()... 5mW Input Voltage... ±V CC Short-Circuit Duration ()... Indefinite Differential Input Voltage ()... ±.7V Differential Input Current ()... ±5mA Storage Temperature Range C to +5 C Operating Temperature Range... C to +5 C Lead Temperature: P (soldering, s)... + C U (soldering, s)... + C NOTES: () Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. () Maximum package power dissipation versus ambient temperature. () To common with ±V CC = 5V. () The inputs are protected by back-to-back diodes. Current limiting resistors are not used in order to achieve low noise. If differential input voltage exceeds ±.7V, the input current should be limited to 5mA. PACKAGE/ORDERING INFORMATION () PACKAGE PACKAGE PRODUCT PACKAGE-LEAD θ JA DRAWING MARKING OPA7 DIP- C/W P OPA7GP OPA7 SO- C/W D OPA7U OPA7 DIP- C/W P OPA7GP OPA7 SO- C/W D OPA7U NOTE: () For the most current package and ordering information, see the Package Option Addendum located at the end of this document, or see the TI website at. PIN CONFIGURATION Top View ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Offset Trim In +In V CC 7 5 NC = No Connection Offset Trim +V CC NC OPA7, OPA7 SBOS5B

3 ELECTRICAL CHARACTERISTICS At V CC = ±5V and T A = +5 C, unless otherwise noted. OPA7 OPA7 PARAMETER CONDITIONS MIN TYP MAX UNITS INPUT NOISE () Voltage, f O = Hz.. nv/ Hz f O = Hz. 5. nv/ Hz f O = khz..5 nv/ Hz f B =.Hz to Hz.9.5 µv PP Current, () f O = Hz.7 pa/ Hz f O = Hz. pa/ Hz f O = khz.. pa/ Hz OFFSET VOLTAGE () Input Offset Voltage ±5 ± µv Average Drift () T A MIN to T A MAX ±. ±. () µv/ C Long Term Stability ().. µv/mo Supply Rejection ±V CC = to V 9 db ±V CC = to V ± ± µv/v BIAS CURRENT Input Bias Current ±5 ± na OFFSET CURRENT Input Offset Current 75 na IMPEDANCE Common-Mode.5 GΩ pf VOLTAGE RANGE Common-Mode Input Range ± ±. V Common-Mode Rejection V IN = ±VDC db OPEN-LOOP VOLTAGE GAIN, DC R L kω 7 db R L kω db FREQUENCY RESPONSE Gain-Bandwidth Product (5) OPA7 5 () MHz OPA7 5 () MHz Slew Rate (5) V O = ±V, R L = kω OPA7, G = +.7 ().9 V/µs OPA7, G = +5 ().9 V/µs Settling Time,.% OPA7, G = + 5 µs OPA7, G = +5 5 µs RATED OUTPUT Voltage R L kω ± ±. V R L Ω ± ±. V Resistance DC, Open Loop 7 Ω Short Circuit Current R L = Ω 5 () ma POWER SUPPLY Rated Voltage ±5 VDC Voltage Range, Derated Performance ± ± VDC Current, Quiescent I O = madc. 5.7 ma TEMPERATURE RANGE Specification +5 C Operating +5 C NOTES: () Measured with industry-standard noise test circuit (Figures and ). Due to errors introduced by this method, these current noise specifications should be used for comparison purposes only. () Offset voltage specification are measured with automatic test equipment after approximately.5 seconds from power turnon. () Unnulled or nulled with kω to kω potentiometer. () Long-term voltage offset vs time trend line does not include warm-up drift. (5) Typical specification only on plastic package units. Slew rate varies on all units due to differing test methods. Minimum specification applies to open-loop test. () This parameter specified by design. OPA7, OPA7 SBOS5B

4 ELECTRICAL CHARACTERISTICS At V CC = ±5V and C T A +5 C, unless otherwise noted. OPA7 OPA7 PARAMETER CONDITIONS MIN TYP MAX UNITS INPUT VOLTAGE () Input Offset Voltage ± ± () µv Average Drift () T A MIN to T A MAX ±. ±. () µv/ C Supply Rejection ±V CC =.5 to V ±V CC =.5 to V 9 () db BIAS CURRENT Input Bias Current ± ±5 () na OFFSET CURRENT Input Offset Current 5 () na VOLTAGE RANGE Common-Mode Input Range ±.5 () ±. V Common-Mode Rejection V IN = ±VDC 9 () db OPEN-LOOP GAIN, DC Open-Loop Voltage Gain R L kω () db RATED OUTPUT Voltage R L = kω ±. () ±. V Short Circuit Current V O = VDC 5 ma TEMPERATURE RANGE Specification +5 C NOTES: () Offset voltage specification are measured with automatic test equipment after approximately.5s from power turn-on. () Unnulled or nulled with kω to kω potentiometer. () This parameter specified by design. OPA7, OPA7 SBOS5B

5 TYPICAL PERFORMANCE CURVES At T A = +5 C, ±V CC = ±5VDC, unless otherwise noted. + INPUT OFFSET VOLTAGE WARM-UP DRIFT INPUT VOLTAGE NOISE vs NOISE BANDWIDTH (.Hz to Indicated Frequency) Offset Voltage Change (µv) +5 5 Voltage Noise (µvrms). R S = Ω 5 Time From Power Turn-On (min). k k k Noise Bandwidth (Hz) Voltage Noise (nv/ Hz) TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY vs SOURCE RESISTANCE R - + R R SOURCE = x R Hz khz Resistor Noise Only Voltage Noise (nv/ Hz) 5 VOLTAGE NOISE SPECTRAL DENSITY vs SUPPLY VOLTAGE khz Hz k k ±5 ± ±5 ± Source Resistance ( Ω) Supply Voltage (V ) CC Voltage Noise (nv/ Hz) 5 VOLTAGE NOISE SPECTRAL DENSITY vs TEMPERATURE Hz khz Ambient Temperature ( C) Current Noise (pa/ Hz)... INPUT CURRENT NOISE SPECTRAL DENSITY Current Noise Test Circuit kω 5kΩ 5kΩ kω DUT I n = (e no ) (nv) M Ω x Warning: This industry-standard equation. is inaccurate and these figures should be used for comparison purposes only!. k k Frequency (Hz) e no OPA7, OPA7 5 SBOS5B

6 TYPICAL PERFORMANCE CURVES (Cont.) At T A = +5 C, ±V CC = ±5VDC, unless otherwise noted. INPUT VOLTAGE NOISE SPECTRAL DENSITY OPEN-LOOP FREQUENCY RESPONSE Voltage Noise (nv/ Hz) Voltage Gain (db) OPA7 OPA7 k Frequency (Hz) k k k M M M Frequency (Hz) BIAS AND OFFSET CURRENT vs TEMPERATURE 5 OPA7 CLOSED-LOOP VOLTAGE GAIN AND PHASE SHIFT vs FREQUENCY (G = ) Absolute Bias Current (na) 5 5 Bias Offset 5 5 Absolute Offset Current (na) Voltage Gain (db) Gain Phase Shift (degrees) Ambient Temperature ( C) k k k M M M Frequency (Hz) 5 OPA7 CLOSED-LOOP VOLTAGE GAIN AND PHASE SHIFT vs FREQUENCY (G = ) COMMON-MODE REJECTION vs FREQUENCY Voltage Gain (db) G = 5 Gain Ø Phase Shift (degrees) Common-Mode Rejection (db) OPA7 OPA7 k k k M M M Frequency (Hz) k k k M M Frequency (Hz) OPA7, OPA7 SBOS5B

7 TYPICAL PERFORMANCE CURVES (Cont.) At T A = +5 C, ±V CC = ±5VDC, unless otherwise noted. POWER SUPPLY REJECTION vs FREQUENCY OPEN-LOOP VOLTAGE GAIN vs SUPPLY VOLTAGE Power Supply Rejection (db) OPA7 V CC +V CC Voltage Gain (db) 5 R L = kω R L = Ω k k k M M 5 ±5 ± ±5 ± ±5 Frequency (Hz) Supply Voltage (V ) CC 5 OPEN-LOOP VOLTAGE GAIN vs TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 5 Voltage Gain (db) 5 R L = kω Supply Current (ma) +5 C +5 C 55 C Ambient Temperature ( C) ±5 ± ±5 ± Supply Voltage (V CC ) +5 COMMON-MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE + OPA7 SMALL SIGNAL TRANSIENT RESPONSE Common-Mode Range (V) T = +5 C A T = +5 C A T = 55 C A T = +5 C A T = 55 C A T = +5 C A Voltage (mv) + + A VCL = + C L = 5pF 5 ±5 ± ±5 ± Supply Voltage (V ) CC Time (µs) OPA7, OPA7 7 SBOS5B

8 TYPICAL PERFORMANCE CURVES (Cont.) At T A = +5 C, ±V CC = ±5VDC, unless otherwise noted. + OPA7 SMALL SIGNAL TRANSIENT RESPONSE + OPA7 LARGE SIGNAL TRANSIENT RESPONSE + + Voltage (mv) + A V = +5 C L = 5pF Voltage (V) + A = + VCL Time (µs) Time (µs) +5 OPA7 LARGE SIGNAL TRANSIENT RESPONSE + Voltage (V) +5 5 A = +5 V 5 5 Time (µs) OPA7, OPA7 SBOS5B

9 APPLICATIONS INFORMATION OFFSET VOLTAGE ADJUSTMENT The OPA7 and OPA7 offset voltages are laser-trimmed and require no further trim for most applications. Offset voltage drift will not be degraded when the input offset is nulled with a kω trim potentiometer. Other potentiometer values from kω to MΩ can be used, but V OS drift will be degraded by an additional.µv/ C to.µv/ C. Nulling large system offsets by use of the offset trim adjust will degrade drift performance by approximately.µv/ C per millivolt of offset. Large system offsets can be nulled without drift degradation by input summing. The conventional offset voltage trim circuit is shown in Figure. For trimming very small offsets, the higher resolution circuit shown in Figure is recommended. The OPA7 and OPA7 can replace 7-type operational amplifiers by removing or modifying the trim circuit. THERMOELECTRIC POTENTIALS The OPA7 and OPA7 are laser-trimmed to microvolt-level input offset voltages, and for very-low input offset voltage drift. Careful layout and circuit design techniques are necessary to prevent offset and drift errors from external thermoelectric potentials. Dissimilar metal junctions can generate small EMFs if care is not taken to eliminate either their sources (lead-to-pc, wiring, etc.) or their temperature difference (see Figure ). Short, direct mounting of the OPA7 and OPA7 with close spacing of the input pins is highly recommended. Poor layout can result in circuit drifts and offsets which are an order of magnitude greater than the operational amplifier alone..µf kω Ω DUT Voltage Gain Total = 5, kω.7µf OPA kω.kω µf.µf Scope x R IN = MΩ.µF kω.kω NOTE: All capacitor values are for nonpolarized capacitors only. FIGURE..Hz to Hz Noise Test Circuit..Hz TO Hz NOISE s/div nv/div FIGURE. Low Frequency Noise. OPA7, OPA7 9 SBOS5B

10 NOISE: BIPOLAR VERSUS FET Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in many cases, so consider the effect of source resistance on overall operational amplifier noise performance. At low source impedances, the lower voltage noise of a bipolar operational amplifier is superior, but at higher impedances the high current noise of a bipolar amplifier becomes a serious liability. Above about 5kΩ, the OPA low-noise FET operational amplifier is recommended for lower total noise than the OPA7, as shown in Figure 5. +V CC 7 () OPA7/7 NOTE: () kω to MΩ Trim Potentiometer (kω Recommended). ±mv Typical Trim Range COMPENSATION Although internally compensated for unity-gain stability, the OPA7 may require a small capacitor in parallel with a feedback resistor (R F ) which is greater than kω. This capacitor will compensate the pole generated by R F and C IN and eliminate peaking or oscillation. INPUT PROTECTION Back-to-back diodes are used for input protection on the OPA7 and OPA7. Exceeding a few hundred millivolts differential input signal will cause current to flow, and without external current limiting resistors, the input will be destroyed. Accidental static discharge, as well as high current, can damage the amplifier s input circuit. Although the unit may still be functional, important parameters such as input offset voltage, drift, and noise may be permanently damaged, as will any precision operational amplifier subjected to this abuse. Transient conditions can cause feedthrough due to the amplifier s finite slew rate. When using the OPA7 as a unity-gain buffer (follower) a feedback resistor of kω is recommended, as shown in Figure. V CC FIGURE. Offset Voltage Trim. R F kω +V CC () NOTE: () kω Trim Potentiometer. Input + OPA7.9V/µs 7.7kΩ OPA7/7.7kΩ FIGURE. Pulsed Operation. V CC ±µv Typical Trim Range FIGURE. High Resolution Offset Voltage Trim. Voltage Noise Spectral Density, E O Typical at khz (nv/ Hz) k R S E O OPA + Resistor OPA7 + Resistor k k k M M Source Resistance, R S (Ω) E O = e n + (i n R S ) + ktr S OPA7 + Resistor OPA + Resistor Resistor Noise Only Resistor Noise Only F O = khz G db at khz. Metal film resistors. Film capacitors. R L and C L per cartridge manufacturer s recommendations. Ω Moving Magnet Cartridge FIGURE 7. Low-Noise RIAA Preamplifier. Input kω R L 7.7kΩ.µF C L 97.kΩ OPA7 kω OPA7.µF µf kω FIGURE 5. Voltage Noise Spectral Density Versus Source Resistance. FIGURE. Unity-Gain Inverting Amplifier. OPA7, OPA7 SBOS5B

11 Input kω 5Ω kω OPA7 G 5dB at khz. Metal film resistors. Film capacitors. R L and C L per head manufacturer s recommendations. Ω.99kΩ.µF kω OPA7 µf 5pF R L C L kω Magnetic Tape Head FIGURE 9. High Slew Rate Unity-Gain Inverting Amplifier. FIGURE. NAB Tape Head Preamplifier. Total Gain = Ω kω DUT Offset G =k Hz Low- Pass Filter Chart Recorder mv/mm 5mm/s A. 7 noise with circuit well-shielded from air currents and RFI. (Note scale change.) 5µV B. OP-7AH with circuit well-shielded from air currents and RFI..5µV C. OPA7AJ with circuit well-shielded from air currents and RFI. (Represents ultimate OPA7 performance potential.).5µv D. OPA7 with circuit unshielded and exposed to normal lab bench-top air currents. (External thermoelectric potentials far exceed OPA7 noise.).5µv E. OPA7 with heat sink and shield which protects input leads from air currents. Conditions same as (D)..5µV FIGURE. Low Frequency Noise Comparison. OPA7, OPA7 SBOS5B

12 In OPA7 Gain = Bandwidth 5kHz For Gain =, use INA differential amplifier. INA5 Differential Amplifier R F 5kΩ 5kΩ 5kΩ 5 R G Ω Input Stage Gain = + R F /R G R F 5kΩ 5kΩ +In OPA7 5kΩ FIGURE. Low Noise Instrumentation Amplifier..µF kω Ω kω Ω 5pF OPA7.µF kω OPA7 EDO Transducer MΩ Frequency Response khz to 5kHz Dexter M Thermopile Detector NOTE: Use metal film resistors and plastic film capacitor. Circuit must be well shielded to achieve low noise. Responsivity.5 x V/W Noise µvrms,.hz to Hz FIGURE. Hydrophone Preamplifier. FIGURE. Long-Wavelength Infrared Detector Amplifier. pf TTL INPUT GAIN + 9.7kΩ 5Ω Balance Trim Input D D kω S S.99kΩ OPA7.75kΩ.75kΩ TTL In DG Offset Trim kω +V CC FIGURE 5. High Performance Synchronous Demodulator. OPA7, OPA7 SBOS5B

13 Gain = V/V V OS µv Drift.7µV/ C e n nv/ Hz at Hz.9nV/ Hz at Hz.7nV/ Hz at khz Full Power Bandwidth khz Gain Bandwidth 5MHz Equivalent Noise Resistance 5Ω Input Ω kω OPA7 kω Signal-to-Noise Ratio N since amplifier noise is uncorrelated. Ω kω OPA7 kω Ω kω kω OPA7 kω OPA7 Ω kω OPA7 kω Ω kω OPA7 kω N = Each OPA7 FIGURE. Ultra-Low Noise N -Stage Parallel Amplifier. OPA7, OPA7 SBOS5B

14 5V 5V +V +V V V V V 5µs R S = 5Ω 5µs R S = 5Ω kω kω Input OPA7 5Ω 5pF OPA7 Input FIGURE 7. Unity-Gain Buffer. FIGURE. High Slew Rate Unity-Gain Buffer. +5V Ω kω µf/v Ω kω + 5Ω Input.µF VIRTEC V Planar Tunnel Diode OPA7 Video µf/v Tantalum + OPA7 RFC Ω 5pF kω kω Siemens LHI 9 FIGURE 9. RF Detector and Video Amplifier. FIGURE. Balanced Pyroelectric Infrared Detector..V + kω Airpax Magnetic Pickup OPA7 f OUT RPM N Where N = Number of Gear Teeth FIGURE. Magnetic Tachometer. OPA7, OPA7 SBOS5B

15 PACKAGE OPTION ADDENDUM -May-5 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan () Lead/Ball Finish MSL Peak Temp () OPA7GP ACTIVE PDIP P 5 TBD Call TI Level-NA-NA-NA OPA7GU ACTIVE SOIC D TBD CU NIPDAU Level--C- YEAR OPA7GU/K5 ACTIVE SOIC D 5 TBD CU NIPDAU Level--C- YEAR OPA7GP ACTIVE PDIP P 5 TBD Call TI Level-NA-NA-NA OPA7GU ACTIVE SOIC D TBD CU NIPDAU Level--C- YEAR OPA7GU/K5 ACTIVE SOIC D 5 TBD CU NIPDAU Level--C- YEAR () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all substances, including the requirement that lead not exceed.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed.% by weight in homogeneous material) () MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page

16 MECHANICAL DATA MPDIA JANUARY 995 REVISED JUNE 999 P (R-PDIP-T) PLASTIC DUAL-IN-LINE. (,).55 (9,) 5. (,). (,).7 (,7) MAX. (,5) MIN.5 (,). (7,).5 (,). (5,) MAX Gage Plane Seating Plane.5 (,) MIN. (,5) NOM. (,5).5 (,). (,5). (,5) M. (,9) MAX /D 5/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS- For the latest package information, go to POST OFFICE BOX 55 DALLAS, TEXAS 755

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